TW550792B - Apparatus for biasing ultra-low voltage logic circuits - Google Patents

Apparatus for biasing ultra-low voltage logic circuits Download PDF

Info

Publication number
TW550792B
TW550792B TW091108348A TW91108348A TW550792B TW 550792 B TW550792 B TW 550792B TW 091108348 A TW091108348 A TW 091108348A TW 91108348 A TW91108348 A TW 91108348A TW 550792 B TW550792 B TW 550792B
Authority
TW
Taiwan
Prior art keywords
transistor
power supply
integrated circuit
circuit device
patent application
Prior art date
Application number
TW091108348A
Other languages
English (en)
Chinese (zh)
Inventor
Andres Bryant
Peter Edwin Cottrell
John Joseph Ellis-Monaghan
Mark B Ketchen
Edward Joseph Nowak
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW550792B publication Critical patent/TW550792B/zh

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW091108348A 2001-04-26 2002-04-23 Apparatus for biasing ultra-low voltage logic circuits TW550792B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/842,544 US6605981B2 (en) 2001-04-26 2001-04-26 Apparatus for biasing ultra-low voltage logic circuits

Publications (1)

Publication Number Publication Date
TW550792B true TW550792B (en) 2003-09-01

Family

ID=25287594

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091108348A TW550792B (en) 2001-04-26 2002-04-23 Apparatus for biasing ultra-low voltage logic circuits

Country Status (3)

Country Link
US (1) US6605981B2 (ja)
JP (1) JP3661792B2 (ja)
TW (1) TW550792B (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI755783B (zh) * 2009-10-16 2022-02-21 日商半導體能源研究所股份有限公司 邏輯電路及半導體裝置

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6936898B2 (en) * 2002-12-31 2005-08-30 Transmeta Corporation Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions
US7334198B2 (en) 2002-12-31 2008-02-19 Transmeta Corporation Software controlled transistor body bias
US7220990B2 (en) * 2003-08-25 2007-05-22 Tau-Metrix, Inc. Technique for evaluating a fabrication of a die and wafer
JP2005109179A (ja) * 2003-09-30 2005-04-21 National Institute Of Advanced Industrial & Technology 高速低消費電力論理装置
US7348827B2 (en) * 2004-05-19 2008-03-25 Altera Corporation Apparatus and methods for adjusting performance of programmable logic devices
US7129745B2 (en) * 2004-05-19 2006-10-31 Altera Corporation Apparatus and methods for adjusting performance of integrated circuits
US7060566B2 (en) * 2004-06-22 2006-06-13 Infineon Technologies Ag Standby current reduction over a process window with a trimmable well bias
US7274073B2 (en) * 2004-10-08 2007-09-25 International Business Machines Corporation Integrated circuit with bulk and SOI devices connected with an epitaxial region
US20060119382A1 (en) * 2004-12-07 2006-06-08 Shumarayev Sergey Y Apparatus and methods for adjusting performance characteristics of programmable logic devices
US7495471B2 (en) 2006-03-06 2009-02-24 Altera Corporation Adjustable transistor body bias circuitry
US7355437B2 (en) * 2006-03-06 2008-04-08 Altera Corporation Latch-up prevention circuitry for integrated circuits with transistor body biasing
US7330049B2 (en) * 2006-03-06 2008-02-12 Altera Corporation Adjustable transistor body bias generation circuitry with latch-up prevention
US7671663B2 (en) * 2006-12-12 2010-03-02 Texas Instruments Incorporated Tunable voltage controller for a sub-circuit and method of operating the same
US8265135B2 (en) * 2007-01-29 2012-09-11 Intel Corporation Method and apparatus for video processing
JP5170086B2 (ja) * 2007-04-10 2013-03-27 富士通セミコンダクター株式会社 リーク電流検出回路、ボディバイアス制御回路、半導体装置及び半導体装置の試験方法
JP2008263088A (ja) * 2007-04-12 2008-10-30 Rohm Co Ltd 半導体装置
US20100321094A1 (en) * 2010-08-29 2010-12-23 Hao Luo Method and circuit implementation for reducing the parameter fluctuations in integrated circuits
TWI528723B (zh) 2013-12-27 2016-04-01 財團法人工業技術研究院 應用特徵化路徑電路的動態調整電路及產生特徵化路徑電路的方法
KR102211167B1 (ko) * 2014-08-14 2021-02-02 삼성전자주식회사 바디 바이어스 전압 생성기 및 이를 포함하는 시스템-온-칩
WO2017189124A1 (en) * 2016-04-29 2017-11-02 Stc. Unm Wafer level gate modulation enhanced detectors
US20200310482A1 (en) * 2019-03-28 2020-10-01 University Of Utah Research Foundation Voltage references and design thereof

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5397934A (en) 1993-04-05 1995-03-14 National Semiconductor Corporation Apparatus and method for adjusting the threshold voltage of MOS transistors
JP3379050B2 (ja) * 1993-11-15 2003-02-17 富士通株式会社 半導体装置
US5689209A (en) * 1994-12-30 1997-11-18 Siliconix Incorporated Low-side bidirectional battery disconnect switch
US5814845A (en) 1995-01-10 1998-09-29 Carnegie Mellon University Four rail circuit architecture for ultra-low power and voltage CMOS circuit design
DE69632098T2 (de) * 1995-04-21 2005-03-24 Nippon Telegraph And Telephone Corp. MOSFET Schaltung und ihre Anwendung in einer CMOS Logikschaltung
JP3629308B2 (ja) * 1995-08-29 2005-03-16 株式会社ルネサステクノロジ 半導体装置およびその試験方法
JP3614546B2 (ja) * 1995-12-27 2005-01-26 富士通株式会社 半導体集積回路
US5917365A (en) 1996-04-19 1999-06-29 Texas Instruments Incorporated Optimizing the operating characteristics of a CMOS integrated circuit
US5811857A (en) * 1996-10-22 1998-09-22 International Business Machines Corporation Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications
US5939934A (en) 1996-12-03 1999-08-17 Stmicroelectronics, Inc. Integrated circuit passively biasing transistor effective threshold voltage and related methods
US5929695A (en) 1997-06-02 1999-07-27 Stmicroelectronics, Inc. Integrated circuit having selective bias of transistors for low voltage and low standby current and related methods
JPH1187727A (ja) * 1997-09-12 1999-03-30 Mitsubishi Electric Corp 半導体装置
US6404269B1 (en) * 1999-09-17 2002-06-11 International Business Machines Corporation Low power SOI ESD buffer driver networks having dynamic threshold MOSFETS
US6628159B2 (en) * 1999-09-17 2003-09-30 International Business Machines Corporation SOI voltage-tolerant body-coupled pass transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI755783B (zh) * 2009-10-16 2022-02-21 日商半導體能源研究所股份有限公司 邏輯電路及半導體裝置
US11756966B2 (en) 2009-10-16 2023-09-12 Semiconductor Energy Laboratory Co., Ltd. Logic circuit and semiconductor device

Also Published As

Publication number Publication date
US20020171468A1 (en) 2002-11-21
JP3661792B2 (ja) 2005-06-22
US6605981B2 (en) 2003-08-12
JP2003008428A (ja) 2003-01-10

Similar Documents

Publication Publication Date Title
TW550792B (en) Apparatus for biasing ultra-low voltage logic circuits
KR100288818B1 (ko) 반도체 집적회로
TWI647777B (zh) 用於ｆｄ－ｓｏｉ裝置之背閘極偏壓的方法、設備及系統
US9276561B2 (en) Integrated circuit process and bias monitors and related methods
US5811857A (en) Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications
US6307233B1 (en) Electrically isolated double gated transistor
CN101515184B (zh) 低压降稳压器
Pan et al. A low voltage to high voltage level shifter circuit for MEMS application
US7145370B2 (en) High-voltage switches in single-well CMOS processes
JPH09116417A (ja) 半導体集積回路装置
TWI408546B (zh) 適應性電壓偏壓控制系統及積體電路
US9837439B1 (en) Compensation of temperature effects in semiconductor device structures
JP3107545B2 (ja) 低電力ｃｍｏｓ回路
US10054974B1 (en) Current mirror devices using cascode with back-gate bias
US10079597B1 (en) Circuit tuning scheme for FDSOI
US7906800B2 (en) Semiconductor integrated circuit
KR980012291A (ko) 반도체 장치
TWI659598B (zh) 具有降低二極管閾值電壓和通態電阻的開關電容充電泵及其操作方法
US20010035774A1 (en) Semiconductor integrated circuit
US9264045B2 (en) Buffer circuit with reduced static leakage through controlled body biasing in FDSOI technology
US6677802B2 (en) Method and apparatus for biasing body voltages
JP2002368124A (ja) 半導体装置
US20070267702A1 (en) Dynamic threshold P-channel MOSFET for ultra-low voltage ultra-low power applications
Vandana A theoretical study of low power soi technology
Adan et al. Low-voltage 0.35/spl mu/m CMOS/SOI technology for high-performance ASIC's

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent