TWI647777B - 用於fd-soi裝置之背閘極偏壓的方法、設備及系統 - Google Patents
用於fd-soi裝置之背閘極偏壓的方法、設備及系統 Download PDFInfo
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- TWI647777B TWI647777B TW106108704A TW106108704A TWI647777B TW I647777 B TWI647777 B TW I647777B TW 106108704 A TW106108704 A TW 106108704A TW 106108704 A TW106108704 A TW 106108704A TW I647777 B TWI647777 B TW I647777B
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Abstract
本發明所揭示的至少一種方法、設備及系統包括提供具有包括後閘極及前閘極的電晶體的半導體裝置。該半導體裝置包括用以處理輸入信號以提供輸出信號的信號處理單元。該信號處理單元包括第一電晶體及第二電晶體。該第一電晶體包括與第一前閘極電性耦接的第一後閘極。該信號處理單元還包括與該第一電晶體操作性耦接的第二電晶體。該第二電晶體包括與第二前閘極電性耦接的第二後閘極。該半導體裝置還包括用以在該輸出信號上提供增益的增益電路。該半導體裝置還包括用以向該第一後閘極提供第一偏置信號並向該第二後閘極提供第二偏置信號的偏置電路。
Description
本發明通常關於先進半導體裝置的製造,尤其關於針對FD-SOI裝置採用後閘極偏置。
對提供更有效操作的積體電路裝置(例如,射頻(RF)裝置,包括數位及類比功能(例如,RF和/或其它模擬功能)的片上系統等)的需求不斷增長。因此,設計人員正不斷嘗試改進半導體製程,以製造更好的積體電路裝置。半導體裝置的製造需要若干獨立的製程步驟以自半導體原材料創建封裝半導體裝置。從半導體材料的初始生長、將半導體晶體切片成獨立晶圓、製造階段(蝕刻、摻雜、離子注入等)直至封裝以及已完成裝置的最終測試的各種製程彼此如此不同而特別,以致該些製程可能執行於包含不同控制方案的不同製造位置。
一般來說,目前實施多種製程技術,其中,對於許多類型的複雜電路(包括場效應電晶體),MOS(金屬氧化物半導體)技術因在操作速度和/或功耗和/或成本效率方面的優越特性而成為目前最有前景的方法之一。在使用
例如MOS技術製造複雜積體電路期間,在包括結晶半導體層的基板上形成數百萬個電晶體,例如N溝道電晶體和/或P溝道電晶體。在製造N溝道MOS(NMOS)裝置和/或P溝道MOS(PMOS)裝置期間,設計人員常常控制製程步驟以允許增加該些裝置的電流驅動。對於NMOS裝置,可增強電子的流動以增加電流驅動。對於PMOS裝置,可增強“空穴”的流動以增加電流驅動。例如,常常形成應變矽層以供改進電荷粒子(也就是電子或空穴)的傳輸。
業界越來越一致認為,必須改進傳統方法,以提供更小的裝置以及可操作於更低電壓的裝置。目前,所謂的塊體FET是實施於許多裝置中的最普遍的設計之一。第1圖顯示形成於半導體晶圓上的典型塊體FET 100的程式化示意圖。FET 100形成於矽基板105上。在矽基板105上形成反型層(inversion layer)150。反型層150通常通過沉積氧化矽形成。閘極110形成於基板105上,由絕緣體120包圍,該絕緣體形成於該晶圓的製程期間,可由HfO2組成。
在反型層150上方形成閘極氧化物層125。
在閘極氧化物層125上方形成FET 100的閘極110。第1圖還顯示源區140及汲區130,它們形成於基板105的頂部。如果基板105為N型,則汲源區130、140將為P型,或者反之。在此配置中,在源區140及汲區130下方創建耗盡區160。
與第1圖的典型塊體FET設計相關聯的其
中一個問題包括以下事實:這些類型FET因不良的載流子限制而可呈現顯著降低的輸出電阻,從而導致較低的電壓增益以及低功率效率。另外,由於耗盡區160,即使當FET 100關閉時也可能發生電流洩漏。電流洩漏可包括汲極洩漏電流、源極洩漏電流,以及阱洩漏電流。FET 100也往往具有較高的閾值電壓。而且,當降低供應電壓以減少功率消耗時,第1圖的典型塊體FET設計往往呈現性能退化。
設計人員已建議使用所謂的絕緣體上矽(silicon-on-insulator;SOI)設計來解決第1圖的典型塊體FET設計所呈現的缺點及問題的其中一些。SOI電晶體通常形成於薄的矽層中,通過使用電性絕緣體例如二氧化矽將該矽層與半導體晶圓的主基板隔離。該薄矽層可具有從幾微米(通常針對電功率開關裝置)至小於500埃(通常針對高性能微處理器)的範圍內的厚度。SOI設計所賦予的該隔離屬性提供用以減少電流洩漏。SOI設計可提供其它優點,例如更快的電路操作以及更低的操作電壓。第2圖顯示形成於半導體晶圓上的典型全耗盡(fully depleted;FD)SOI FET 200的程式化示意圖。
FD-SOI FET 200形成於矽基板205上。FET
200包括通過沉積氧化矽形成的耗盡區250。閘極200形成於基板205上,由絕緣體220包圍,該絕緣體形成於該晶圓的製程期間,且通常由HfO2組成。
在基板205上方形成閘極氧化物層225。在閘極氧化物層225上方形成FET 200的閘極220。FET 220
還包括源區240及汲區230,它們形成於基板105的頂部。
如果基板105為N型,則汲源區230、240將為P型,或者反之。另外,FET 200包括位於汲源區230、240下方的埋置氧化物(buried oxide;BOX)區270。
在此配置中,替代第1圖的大耗盡區160,耗盡區250被限於BOX區270上方以及汲源區230、240之間。BOX區270形成於源區140、汲區130以及耗盡區250下方。BOX區的位置防止形成與第1圖的耗盡區160類似的大耗盡區。另外,在此情況下,耗盡區250為全耗盡。如果汲源區230、240為P型,則耗盡區250將為N型耗盡區,或者反之。
關於FD-SOI裝置的一個考慮問題是在高頻應用中的偏置問題。通過使用當前技術的設計,應用於FD-SOI裝置中的偏置可引起寄生電容問題。第3圖顯示針對FD-SOI裝置的高頻應用的典型高增益偏置。第3圖顯示電路300,其表示允許操作及高跨導-電流比(gm/I)以及高跨導-溝道電導比(gm/gds)的傳統偏置網路。電路300表示塊體電晶體電路或finFET電路。
第3圖顯示電路300,其能夠在高頻(也就是射頻(RF))輸入信號RFin(350)上提供增益,以提供放大的RF輸出RFout(360)。該電路包括PFET 310及NFET 320,它們通過它們的汲極節點連接。通過電阻器R3(334)向PFET 310的閘極提供輸入電壓Vgp,同時通過電阻器R2(333)向NFET 320的閘極提供輸入電壓Vgn。電阻器R2
333與電阻器R3 334是大值電阻器,以應用DC偏置並將DC電路與RF電路分開。電路300還包括電容器C4(370)及C5(372),它們經設計以提供DC阻斷/AC耦合。電路300還包括電阻器R1(330),以針對DC及RF信號提供從輸出信號RFout 360至輸入信號RFin 350的負反饋。設計人員已實施此設計以獲得AB類操作,從而實現較低的電流消耗,並使用DC偏置,從而能夠對小信號作出反應。
不過,在與電路300的該傳統設計相關聯的問題中包括以下事實:經設計以優化增益及增益效率的此偏置電路往往增加信號路徑寄生電容。電容器C1 340、C2 342及C3 344表示電路300中不同位置處的寄生電容。寄生電容器C1 340、C2 342及C3 344與基板耦接。該寄生電容存在的部分原因是存在AC耦合電容器。
理想地,希望輸入信號RFin 350中的電流經過該些電晶體,且該RFout信號上的電壓處於中電平,以使其可圍繞靜態點擺動。不過,由於存在寄生電容,輸入信號RFin 350中的電流的部分可能經過寄生電容C1 340、C2 342以及C3 344,其可導致不良的功率消耗以及降低的信號頻寬。另外,該寄生電容可引起性能退化。此外,該AC耦合電容器往往大且消耗掉寶貴的晶片實體區域並增加生產成本。
本發明可解決和/或至少減輕上述問題的其中一個或多個。
下面提供本發明的簡要總結,以提供本發明的一些態樣的基本理解。本發明內容並非詳盡概述本發明。其並非意圖識別本發明的關鍵或重要元件或劃定本發明的範圍。其唯一目的在於提供一些簡化形式的概念,作為後面所討論的更詳細說明的前序。
一般來說,本發明關於至少一種方法、設備及系統,其包括具有包括後閘極及前閘極的電晶體的半導體裝置。該半導體裝置包括用以處理輸入信號以提供輸出信號的信號處理單元。該信號處理單元包括第一電晶體及第二電晶體。該第一電晶體包括與第一前閘極電性耦接的第一後閘極。該信號處理單元還包括與該第一電晶體操作性耦接的第二電晶體。該第二電晶體包括與第二前閘極電性耦接的第二後閘極。該半導體裝置還包括用以在該輸出信號上提供增益的增益電路。該半導體裝置還包括用以向該第一後閘極提供第一偏置信號並向該第二後閘極提供第二偏置信號的偏置電路。
100、200‧‧‧FET
105、205‧‧‧基板
110、210‧‧‧閘極
120、220‧‧‧絕緣體
125、225‧‧‧閘極氧化物層
130、230‧‧‧汲區
140、240‧‧‧源區
150‧‧‧反型層
160、250‧‧‧耗盡區
270‧‧‧埋置氧化物區、BOX區
300‧‧‧電路
310‧‧‧PFET
320‧‧‧NFET
330‧‧‧電阻器R1
333‧‧‧電阻器R2
334‧‧‧電阻器R3
340‧‧‧電容器C1
342‧‧‧電容器C2
344‧‧‧電容器C3
350‧‧‧RFin
360‧‧‧RFout
370‧‧‧電容器C4
372‧‧‧電容器C5
405a‧‧‧第一電晶體
405b‧‧‧第二電晶體
410‧‧‧矽基板層、矽基板
420‧‧‧P基板層
425‧‧‧P基板端子
430‧‧‧三阱層
450a、450b、470‧‧‧後閘極
455a、455c‧‧‧N+節點
460a‧‧‧第一前閘極、前閘極
460b‧‧‧第二前閘極、前閘極
462a、462b‧‧‧絕緣體上矽結構、SOI結構
464a、464b‧‧‧源極
466a、466b‧‧‧汲極
468a、468b‧‧‧閘極
480a、480b、480c‧‧‧N阱區
470‧‧‧氧化物層
500、600‧‧‧裝置
505、605‧‧‧電晶體
510、610‧‧‧前閘極
512、612‧‧‧第一埠、閘極電壓
514、614‧‧‧汲極
516、616‧‧‧源極
520、620‧‧‧後閘極
525、530、625、630‧‧‧等效二極體
640‧‧‧N阱二極體電壓源
645‧‧‧Vdd
660‧‧‧第二埠
700‧‧‧電路
710‧‧‧PMOS電晶體、電晶體
712、717‧‧‧前閘極
714、719‧‧‧汲極
715‧‧‧NMOS電晶體、電晶體
716、718‧‧‧源極
720、722‧‧‧後閘極
725、730、732‧‧‧等效二極體
750‧‧‧輸入節點、Rfin、節點
752‧‧‧DC耦合信號、Vfg
755‧‧‧輸出節點、RFout
760‧‧‧電阻器R1
772‧‧‧P基板電壓
774‧‧‧N阱電壓
800‧‧‧裝置
810‧‧‧主電路
820‧‧‧信號處理單元
830‧‧‧PMOS電晶體、電晶體
832、842‧‧‧後閘極
834、844‧‧‧前閘極
840‧‧‧NMOS電晶體、電晶體
850‧‧‧增益級
860‧‧‧偏置電路
910‧‧‧信號處理方塊
920‧‧‧分壓器
930‧‧‧電流鏡電路、電流鏡
935‧‧‧電流-電壓轉換器
940‧‧‧第二放大器電路、放大器電路
950‧‧‧第一放大器電路、放大器電路
960‧‧‧電流鏡
1010、1110‧‧‧放大器
1020‧‧‧電壓源
1022‧‧‧RC電路
1130‧‧‧電阻器
1140‧‧‧電容器
1200‧‧‧系統
1210‧‧‧製程系統
1215‧‧‧積體電路、裝置、專案
1220‧‧‧製程控制器
1240‧‧‧積體電路設計單元、設計單元、單元
1250‧‧‧傳輸機制
參照下面結合圖式所作的說明可理解本發明,該些圖式中類似的元件符號表示類似的元件,且其中:第1圖顯示形成於半導體晶圓上的典型塊體FET的程式化示意圖;第2圖顯示形成於半導體晶圓上的典型全耗盡(fully depleted;FD)SOI FET的程式化示意圖;第3圖顯示針對FDSOI裝置的高頻應用的
典型高增益偏置電路的程式化示意圖;第4圖顯示依據本文中的實施例包括分別具有前閘極及後閘極的電晶體的積體電路的剖視圖的程式化示意圖;第5圖顯示依據本文中的實施例包括後閘極及前閘極的三阱(triple-well)電晶體設計中的未摻雜NMOS裝置的程式化示意圖;第6圖顯示依據本文中的實施例包括後閘極及前閘極的三阱電晶體設計中的未摻雜PMOS裝置的程式化示意圖;第7A圖顯示依據本文中的第一實施例的高增益高效率(high gain-high efficiency;HGGE)核心電路的程式化示意圖;第7B圖顯示依據本文中的第二實施例的高增益高效率(HGGE)核心電路的程式化示意圖;第8圖顯示依據本文中的實施例包括具有前閘極及後閘極(與偏置電路耦接以偏置該後閘極)的電晶體的主電路的程式化示意圖;第9圖顯示依據本文中的實施例的第8圖的偏置電路的程式化方塊示意圖;第10圖顯示依據本文中的實施例的第9圖的第一放大器電路的程式化方塊示意圖;第11圖顯示依據本文中的實施例的第9圖的第二放大器電路的程式化方塊示意圖;以及
第12圖顯示依據本文中的一些實施例用以製造包括FD SOI PMOS及NMOS裝置的裝置的系統的程式化示意圖。
儘管本文中所揭示的申請標的容許各種修改及替代形式,但本發明主題的特定實施例以示例形式顯示於圖式中並在本文中作詳細說明。不過,應當理解,本文中有關特定實施例的說明並非意圖將本發明限於所揭示的特定形式,相反,意圖涵蓋落入由所附申請專利範圍定義的本發明的精神及範圍內的所有修改、均等及替代。
下面說明本發明的各種示例實施例。出於清楚目的,不是實際實施中的全部特徵都在本說明書中進行說明。當然,應當瞭解,在任意此類實際實施例的開發中,必須作大量的特定實施決定以實現開發者的特定目標,例如符合與系統相關及與商業相關的約束條件,該些決定將因不同實施而異。而且,應當瞭解,此類開發努力可能複雜而耗時,但其仍然是本領域的普通技術人員借助本發明所執行的常規程式。
現在將參照圖式來說明本申請標的。圖式中示意各種結構、系統及裝置僅是出於解釋目的以及避免使本發明與本領域技術人員已知的細節混淆,但仍包括該些圖式以說明並解釋本發明的示例。本文中所使用的詞語和片語的意思應當被理解並解釋為與相關領域技術人員對這些詞語及片語的理解一致。本文中的術語或片語的連貫
使用並不意圖暗含特別的定義,亦即與本領域技術人員所理解的通常或慣用意思不同的定義。若術語或片語意圖具有特別意思,亦即不同於本領域技術人員所理解的意思,則此類特別定義會以直接明確地提供該術語或片語的特別定義的定義方式明確表示於說明書中。
本文中的實施例用以製造包括NMOS及/或PMOS裝置(例如FDSOI電晶體,如22FDSOI電晶體)的高頻電路。本文中的實施例用以利用後閘極設計來影響電晶體的前閘極電路的操作。此概念可應用於各種類型電路,例如高頻應用,包括射頻(RF)應用。
本文中的一些實施例涉及使用偏置電路來控制一個或多個前閘極的電壓的後閘極設計。例如,可將該前閘極電壓變為Vdd電壓的分數(例如,Vdd/2)。在一些實施例中,可使用後閘極改變前閘極的閾值電壓。偏置電路結合一個或多個後閘極可提供各種優點,例如減少或消除AC耦合電容器的使用,其可用以減少晶片面積使用,降低生產成本,以及改進電路性能。
本文中的實施例用以利用後閘極設計將前閘極電路的電流密度設置為預定水準。針對NMOS電路,可將後閘極電壓設為負預定電平,或者針對PMOS電路,可將後閘極電壓設為正預定電平。在一個實施例中,可實施反向後閘極偏置,以獲得較高的增益(也就是跨導[gm]*負載電阻[rd])。在一些實施例中,可實施正向後閘極偏置,以實現供應電壓(Vdd)操作的降低。通過使用負反饋回路,
PMOS後閘極偏置可用以將電壓驅動至預定電壓(例如,Vdd/2)。
本文中的實施例的一些優點包括消除或大幅減少AC耦合電容器的使用。另外,通過本文中的實施例可減少寄生電容。可減少源汲電容,以為波成形提供更快的升降時間。在本文的實施例中使用反向偏置可供以高增益及增益效率(gm/I)大幅減少或消除信號路徑損失。另外,在本文的實施例中使用正向偏置可供降低電晶體的閾值電壓,且在一些情況下,將閾值電壓降低至接近或為零。
這可在近軌至軌輸入電壓範圍上提供基本恒定的gm。可在零伏的閾值電壓實現最高fT。
現在請參照第4圖,其顯示依據本文中的實施例包括分別具有前閘極及後閘極的電晶體的積體電路的剖視圖的程式化示意圖。製備矽基板層410,以沉積用以形成FD-SOI裝置的各種層。在矽基板410上方形成P基板層420。在該P基板層的部分上方形成由P+摻雜物材料組成的P基板端子425,以使P基板端子425與P基板層420操作性耦接。
在P基板層420上方形成三阱層430。形成多個P阱結構,以定義多個後閘極450a及450b。三阱層430提供埋置N阱層,其將該後閘極470的P阱與P基板層420隔離,從而降低基板雜訊耦合。另外,在三阱層430上方形成N阱區480a、480b以及480c,以隔離後閘極450a及450b。在N阱區480a上方形成N+節點455a,且在N阱
區480c上方形成N+節點455c。
在各後閘極450a、450b上方形成氧化物層(例如SiO2)470。在後閘極450a上方形成第一前閘極460a,且在後閘極450b上方形成第二前閘極460b。後閘極450a與前閘極460a形成第一電晶體405a,其中,後閘極450b與前閘極460b形成第二電晶體405b。
第一電晶體405a包括閘極468a、源極464a以及汲極466a,它們形成於絕緣體上矽(SOI)結構462a上。
第二電晶體405b包括閘極468b、源極464b以及汲極466b,它們形成於SOI結構462b上。向後閘極450a提供後閘極電壓Vbgp(下面進一步詳細說明),並向後閘極450b提供後閘極電壓Vbgn。第4圖中所示的裝置提供後閘極/前閘極設計,其中,後閘極450a、450b分別能夠影響第一及第二電晶體405a、405b的前閘極460a、460b的閾值、操作電壓和/或電流密度,如下面進一步詳細說明。
現在請參照第5圖,其顯示依據本文中的實施例包括後閘極及前閘極的三阱電晶體設計中的未摻雜NMOS裝置的程式化示意圖。第5圖的裝置500包括電晶體505,該電晶體包括前閘極510及後閘極520。第一埠512向前閘極510提供輸入電壓。向後閘極520提供後閘極電壓Vbgn。電晶體505的源極516耦接地,而汲極514與第二埠耦接。裝置500的N阱提供等效二極體525,其中,裝置500的P基板部分提供等效二極體530。
裝置500的電路在前閘極510與汲極514之
間提供兩埠s-par(s參數),而源極516接地。在一些實施例中,可將輸入閘極電壓512及汲極電壓的DC偏置固定於Vdd的分數,例如Vdd/2。通過調整該後閘極電壓電平Vbgn可控制汲-源電流(Ids)。
對於反向偏置,該後閘極偏置電壓可從0伏掃至負電壓(例如,-5V)。對於正向偏置,該後閘極電壓可被設為正值(例如,+5V、+4V、+3V、+2V等)。後閘極520可用以影響前閘極510的閾值、操作電壓和/或電流密度。
現在請參照第6圖,其顯示依據本文中的實施例包括後閘極及前閘極的三阱電晶體設計中的未摻雜PMOS裝置的程式化示意圖。第6圖的裝置600包括電晶體605,該電晶體包括前閘極610及後閘極620。第一埠612向前閘極610提供輸入電壓。向後閘極620提供後閘極電壓Vbgp。電晶體605的源極616與Vdd 645耦接,而汲極614與第二埠660耦接。裝置600的N阱提供等效二極體625,其中,裝置600的P基板部分提供等效二極體630,其具有N阱電壓。二極體630、625與表示N阱二極體電壓源640的節點耦接。
裝置600的電路在前閘極610與在Vdd的汲極614之間提供兩埠s-par,而源極610在Vdd,且AC分量接地。通過使用第一及第二埠612、660可定義gm、gd、fT以及fmax。在一些實施例中,可將輸入閘極電壓612及汲極電壓的DC偏置固定於Vdd的分數,例如Vdd/2。通過
調整該後閘極電壓電平Vbgn可控制汲-源電流(Ids)。
對於反向偏置,該後閘極偏置電壓可從0伏掃至正電壓(例如,+5V)。對於正向偏置,該後閘極電壓可被設為負值(例如,-5V、-4V、-3V、-2V等)。後閘極620可用以影響前閘極610的閾值、操作電壓和/或電流密度。
現在請參照第7A及7B圖,第7A圖顯示依據第一實施例的高增益高效率(HGGE)核心電路的程式化示意圖。第7B圖顯示依據第二實施例與第7A圖中的電路類似的電路。請同時參照第7A及7B圖,電路700包括PMOS電晶體710及NMOS電晶體715。PMOS電晶體710包括前閘極712及後閘極720。輸入節點Rfin 750可向PMOS電晶體710的前閘極712以及NMOS電晶體715的前閘極717提供高頻輸入電壓。電阻器R1 760與該RFin信號及輸出節點755耦接,輸出節點755承載輸出信號RFout。
電晶體710包括後閘極720且電晶體715包括後閘極722。向PMOS電晶體710的後閘極720提供後閘極電壓Vbgp。向NMOS電晶體715的後閘極722提供後閘極電壓Vbgn。PMOS電晶體710的源極716與Vdd耦接,而汲極714與NMOS電晶體715的汲極719耦接。該NMOS電晶體的源極718與Vss耦接。
裝置700的N阱提供等效二極體725及等效二極體732,它們與N阱電壓774耦接。裝置700的P基板部分提供等效二極體730,其與P基板電壓772耦接。在一些實施例中,可將節點750處的輸入閘極電壓的DC
偏置固定於Vdd的分數,例如Vdd/2。通過調整後閘極電壓Vbgp及Vbgn可控制汲-汲電流(Idd)。
後閘極720及722可用以影響PMOS及NMOS電晶體710、715的前閘極712、717的閾值、操作電壓及/或電流密度。由後閘極720及722提供的電晶體710、715的偏置提供高增益及高效率操作,同時大幅降低或消除信號路徑損失。
第7B圖與第7A圖類似,除了第7B圖中缺失與Rfin信號及輸出節點755耦接的電阻器R1 760以外。
另外,第7B圖的前閘極710、715與DC耦合信號(Vfg 752)耦接,該信號可與前級放大器或獨立的偏置設置電路耦接。在(第7B圖的)此電路中,前閘極輸入電壓由該前級放大器或該獨立偏置設置電路確定,其中,輸出電壓由本文中的實施例所提供的後閘極偏置確定。
現在請參照第8圖,其顯示依據本文中的實施例包括具有前閘極及後閘極(與偏置電路耦接以偏置該後閘極)的電晶體的主電路的程式化方塊示意圖。裝置800(例如高頻RF裝置)可包括主電路810及偏置電路860。
主電路810可包括信號處理單元820(例如RF信號處理單元),其能夠處理輸入信號(例如高頻信號)RFin,並提供輸出信號RFout。
信號處理單元820可包括PMOS電晶體830及NMOS電晶體840。電晶體830、840可為FD-SOI裝置。
PMOS電晶體830包括後閘極832及前閘極834。NMOS電
晶體840包括後閘極842及前閘極844。
後閘極832、842可與偏置電路860耦接,該偏置電路向各後閘極832、842提供偏置電壓信號。與第7圖中示例的電路類似,後閘極832自偏置電路860接收偏置電壓信號Vbgp,且後閘極842自偏置電路860接收偏置電壓信號Vbgn。經過後閘極832、834的偏置電壓信號Vbgp及Vbgn可用以控制前閘極834、844的閾值、操作電壓和/或電流密度。可將信號處理單元820的輸出提供至增益級850,該增益級可緩衝及/或放大輸入信號(例如RF信號),以提供高頻輸出信號RFout。第9圖以及下面所附說明中提供有關偏置電路860的更詳細說明。
現在請參照第9圖,其顯示依據本文中的實施例的第8圖的偏置電路的程式化方塊示意圖。偏置電路860可包括按比例複製的信號處理方塊910,以匹配主電路810的信號處理單元820。分壓器920用以將Vdd的電壓電平分成Vdd的分數(例如,Vdd/2)。將該分壓電壓提供至電流鏡電路930。電流鏡930可包括電流-電壓轉換器935。
該電流鏡的輸出是與電流鏡930的電流成比例的電壓。將此電壓提供至第一放大器電路950。第一放大器電路950還接收預定電流基準電壓。基於該些輸入(與電流鏡960的電流成比例的電壓以及電流基準電壓),第一放大器電路950產生偏置信號Vbgn。
另外,將來自分壓器920的分壓電壓信號(例如,Vdd/2)提供至第二放大器電路940。另外,將來自
RFout的電壓信號提供至第二放大器電路940。基於該些輸入(分壓電壓信號以及來自RFout的電壓信號),第二放大器電路940產生偏置信號Vbgp。將偏置信號Vbgn及Vbgp提供至信號處理單元820中的RF電晶體的後閘極。第10及11圖以及下面所附說明中分別提供該第一及第二放大器電路的更詳細說明。
在一個實施例中,可將放大器電路940、950的頻寬限於低於RF通帶。該限制可以本領域的技術人員借助本發明所熟知的若干方式實現。例如,使用RC濾波器電路,限制放大器電路940、950中的放大器(例如,運算放大器)的頻寬,提供op-amp(運算放大器)回饋RF濾波、輸入濾波,以及/或者使用本領域的技術人員借助本發明所熟知的其它方式。
現在請參照第10圖,其顯示依據本文中的實施例的第9圖的第一放大器電路的程式化方塊示意圖。
第一放大器電路950包括放大器1010,其自電流-電壓轉換器935接收輸出,其中,此電壓信號與Idd或Idd的分數成比例。將此電壓信號與由電壓源1020表示的電流基準電壓信號一起提供至放大器1010的輸入。放大器1010可為負反饋電路、增益元件,或運算放大器(op amp)。放大器裝置1010的輸出信號Vbgn具有單位增益頻寬(unity gain bandwidth;UGBW),其顯著小於輸入信號RFin的頻率。
將輸出信號(Vbgn)提供至NMOS後閘極842,該輸出信號是用於NMOS電晶體840的偏置信號。
在一個實施例中,放大器1010的輸入(V=K Idd/N)還可包括RC電路1022,以控制放大器電路950的頻寬。在一個實施例中,可將放大器電路950的頻寬限於低於RF通帶。此限制可以本領域的技術人員借助本發明所熟知的若干方式實施。例如,可使用RC電路1022(例如,與第11圖中所示類似),限制放大器1010本身的頻寬,提供op-amp回饋RF濾波、輸入濾波,以及/或者使用本領域的技術人員借助本發明所熟知的其它方式。
現在請參照第11圖,其顯示依據本文中的實施例的第9圖的第二放大器電路的程式化方塊示意圖。
第二放大器電路940包括放大器1110,其自信號處理單元820接收輸出信號RFout。因此,通過PMOS後閘極832執行PMOS電晶體830的回饋調整。放大器1010可為負反饋電路、增益元件,或運算放大器(op amp)。
輸出電壓RFout通過包括電阻器1130及電容器1140的RC網路發送。將該RC網路的輸出與由電壓源1120表示的基準電壓信號Vref一起提供至放大器1110。放大器裝置1110的輸出信號Vgbp也具有UGBW,其顯著小於輸入信號RFin的頻率。將輸出信號(Vbgp)提供至PMOS後閘極832,該輸出信號是用於PMOS電晶體840的偏置信號。
放大器1010、1110的負反饋元件經配置而具有低頻寬,其基本阻止在RFin 750/RFout 755信號的較高信號頻率(例如RF頻率)的負反饋。提供此配置以使負反
饋不會將電晶體電流及電壓保持於恒定水準,其將阻止任意放大。
在一個實施例中,可將放大器電路940的頻寬限於低於RF通帶。此限制可以本領域技術人員借助本發明所熟知的若干方式實施。例如,使用RC濾波器電路(1130,1140),限制放大器1110本身的頻寬,提供op-amp回饋RC濾波、輸入濾波,以及/或者使用本領域技術人員借助本發明所熟知的其它方式。
現在請參照第12圖,其顯示依據本文中的實施例用以製造包括FD SOI PMOS及NMOS裝置的裝置的系統的程式化示意圖。半導體裝置製程系統1210可包括各種製程站,例如蝕刻製程站、光刻製程站、CMP(化學機械拋光)製程站等。由製程系統1210執行的一個或多個製程步驟可由製程控制器1220控制。製程控制器1220可為工作站電腦、臺式電腦、筆記型電腦、平板電腦,或包括能夠控制製程、接收製程回饋、接收測試結果資料、執行學習週期調整、執行製程調整等的一個或多個軟體產品的任意其它類型計算裝置。
半導體裝置製程系統1210可在媒體例如矽晶圓上生產積體電路。裝置製程系統1210生產積體電路可基於由積體電路設計單元1240提供的電路設計。製程系統1210可在傳輸機制1250例如傳送帶系統上提供加工後的積體電路/裝置1215。在一些實施例中,該傳送帶系統可為能夠傳輸半導體晶圓的複雜潔淨室傳輸系統。在一個實施
例中,半導體裝置製程系統1210可包括多個製程步驟,例如第一製程步驟、第二製程步驟等,如上所述。
在一些實施例中,被標記為“1215”的專案可代表單個晶圓,以及在其它實施例中,專案1215可代表一組半導體晶圓,例如一“批次”半導體晶圓。積體電路或裝置1215可為電晶體、電容器、電阻器、記憶體單元、處理器,以及/或者類似物。在一個實施例中,裝置1215為電晶體且介電層為該電晶體的閘極絕緣層。
系統1200的積體電路設計單元1240能夠提供可通過半導體製程系統1210製造的RF電路裝置設計。
設計單元1240可接收有關將要設計的積體電路的設計規格的數據,包括有關具有後閘極及前閘極的電晶體以及該後閘極的偏置信號的參數。設計單元1240能夠分析並執行設計調整,以提供、佈線並實施正向和/或反向偏置電壓。
尤其,設計單元1240可接收有關形成包括後閘極及前閘極的電晶體的規格的數據。另外,設計單元1240可接收有關用以偏置後閘極的偏置電壓電平、操作電壓、閾值規格以及/或者電流密度規格的數據。
在其它實施例中,設計單元1240可執行區域自動確定,其需要設計調整以提供、佈線及實施正向和/或反向偏置電壓以及定時調整,並將設計調整自動納入裝置設計中。例如,一旦積體電路設計單元1240的設計者或使用者通過使用圖形化使用者介面與積體電路設計單元1240通信來生成設計,單元1240即可執行該設計的自動
修改。
系統1200可執行涉及各種技術的各種產品的分析及製造。例如,系統1200可設計並產生資料以製造有關CMOS技術、快閃(Flash)技術、BiCMOS技術、功率裝置、控制器、處理器、RF電路,以及/或者各種其它半導體技術的裝置。
儘管在一些例子中,出於一致性及方便顯示目的,就FD SOI裝置說明本文中的電路,但本領域的技術人員將瞭解,本文中所述的概念也適用於其它SOI裝置(例如部分耗盡(partially depleted;PD)SOI裝置)並保持於本文中的實施例的範圍內。本文中所述的概念及實施例可適用於多種類型的VT(閾值)族裝置,包括但不限於FD SOI LVT(低閾值)電晶體、FD SOI SLVT(超低閾值)電晶體、FD SOI RVT(常規閾值)電晶體、FD SOI HVT(高閾值)電晶體,或這裡的組合,並保持於本文中的實施例的範圍內。
系統1100可執行涉及各種技術的包括具有主動及非主動閘極的電晶體的各種產品的製造及測試。例如,系統1100可供用以製造及測試有關CMOS技術、BiCMOS技術、功率裝置、處理器,以及/或者各種其它類型積體電路裝置(例如射頻(RF)裝置、包括RF和/或類比功能的片上系統等)的產品。
上述方法可通過指令控制,該指令儲存於非暫時性電腦可讀儲存媒體中並通過例如計算裝置中的處理器執行。本文中所述的各該操作可對應儲存於非暫時性
電腦記憶體或電腦可讀儲存媒體中的指令。在各種實施例中,該非暫時性電腦可讀儲存媒體包括磁或光碟儲存裝置,固態儲存裝置例如快閃記憶體,或一個或多個其它非易失性記憶體裝置。儲存於該非暫時性電腦可讀儲存媒體上的該電腦可讀指令可為原始程式碼、組合語言代碼、目標代碼,或由一個或多個處理器解釋且/或可執行的其它指令格式。
由於本發明可以本領域的技術人員借助本文中的教導而明白的不同但均等的方式修改並實施,因此上面所揭示的特定實施例僅為示例性質。例如,可以不同的循序執行上述製程步驟。而且,本發明並非意圖限於本文中所示的架構或設計的細節,而是如申請專利範圍所述。因此,顯然,可對上面所揭示的特定實施例進行修改或變更,且所有此類變更落入本發明的範圍及精神內。因此,申請專利範圍規定本發明請求保護的範圍。
Claims (19)
- 一種製造半導體裝置之方法,包括:在矽基板上方形成P基板層;在該P基板層上方形成三阱;形成第一P阱結構,以定義電晶體的第一後閘極,從而該三阱將該第一P阱結構與該P基板層隔離;在該第一後閘極上方形成第一氧化物層;在該第一氧化物層上方形成第一氧化物上矽(SOI)層;以及形成第一源區、第一汲區以及第一前閘區,以形成包括該第一後閘極及該第一前閘極的電晶體。
- 如申請專利範圍第1項所述之方法,還包括:形成第二P阱結構,以定義電晶體的第二後閘極,從而該三阱將該第二P阱結構與該P基板層隔離;在該第二後閘極上方形成第二氧化物層;在該第二氧化物層上方形成第二SOI層;以及形成第二源區、第二汲區以及第二前閘區,以形成包括該第一後閘極及該第一前閘極的第二電晶體。
- 如申請專利範圍第2項所述之方法,還包括在該三阱上方形成第一N阱區,以將該第一後閘極與該第二後閘極隔離。
- 如申請專利範圍第2項所述之方法,其中:在該第一P阱的部分上方形成第一P+結構,以將偏置電壓信號與該第一後閘極連接,從而控制該第一電晶體的操作閾值、操作電壓及電流密度的至少其中之一;以及在該第二P阱的部分上方形成第二P+結構,以將偏置電壓信號與該第二後閘極連接,從而控制該第二電晶體的操作閾值、操作電壓及電流密度的至少其中之一。
- 如申請專利範圍第2項所述之方法,其中:鄰近該第一P阱結構形成第二N阱區,以將該第一P阱結構與該P基板層隔離;以及鄰近該第二P阱結構形成第三N阱區,以將該第二P阱結構與該P基板層隔離。
- 如申請專利範圍第5項所述之方法,其中:在該第三N阱區的部分上方形成N+區,以提供至N阱二極體電壓的連接;以及在該P+基板的部分上方形成P+區,以提供至P基板電壓的連接。
- 如申請專利範圍第1項所述之方法,還包括形成偏置電路,該偏置電路經配置以:向該第一後閘極提供第一偏置信號,以控制該第一電晶體的閾值、操作電壓及電流密度的至少其中之一;以及向該第二後閘極提供第二偏置信號,以控制該第二電晶體的閾值、操作電壓及電流密度的至少其中之一。
- 一種半導體裝置,包括:信號處理單元,用以處理輸入信號以提供輸出信號,該信號處理單元包括:第一電晶體及第二電晶體,其中,該第一電晶體包括與第一前閘極電性耦接的第一後閘極;以及第二電晶體,與該第一電晶體操作性耦接,其中,該第二電晶體包括與第二前閘極電性耦接的第二後閘極;增益電路,用以在該輸出信號上提供增益;以及偏置電路,用以向該第一後閘極提供第一偏置信號並向該第二後閘極提供第二偏置信號,其中,該偏置電路包括:分壓器電路,用以提供分壓電壓信號;電流鏡,用以基於該分壓電壓信號提供與電流成比例的電壓信號;第一放大器電路,經配置以接收該與電流成比例的電壓信號以及電流基準電壓信號並提供該第二偏置信號;以及第二放大器電路,經配置以接收該分壓電壓信號以及該輸出信號並提供該第一偏置信號。
- 如申請專利範圍第8項所述之半導體裝置,其中,該第一電晶體為PMOS裝置且該第二電晶體為NMOS裝置。
- 如申請專利範圍第9項所述之半導體裝置,其中,該第一偏置信號為正電壓信號且該第二偏置信號為負電壓信號。
- 一種半導體裝置,包括:信號處理單元,用以處理輸入信號以提供輸出信號,該信號處理單元包括:第一電晶體及第二電晶體,其中,該第一電晶體包括與第一前閘極電性耦接的第一後閘極;以及第二電晶體,與該第一電晶體操作性耦接,其中,該第二電晶體包括與第二前閘極電性耦接的第二後閘極;增益電路,用以在該輸出信號上提供增益;以及偏置電路,用以向該第一後閘極提供第一偏置信號並向該第二後閘極提供第二偏置信號,其中,該增益電路經調整以提供該輸出信號的單位增益及放大的至少其中之一。
- 一種半導體裝置,包括:信號處理單元,用以處理輸入信號以提供輸出信號,該信號處理單元包括:第一電晶體及第二電晶體,其中,該第一電晶體包括與第一前閘極電性耦接的第一後閘極;以及第二電晶體,與該第一電晶體操作性耦接,其中,該第二電晶體包括與第二前閘極電性耦接的第二後閘極;增益電路,用以在該輸出信號上提供增益;以及偏置電路,用以向該第一後閘極提供第一偏置信號並向該第二後閘極提供第二偏置信號,其中,該輸入信號為射頻信號。
- 如申請專利範圍第8、11或12項所述之半導體裝置,其中,該第一電晶體的汲極與該第二電晶體的汲極電性耦接,其中,輸出信號節點與該第一電晶體的該汲極耦接。
- 如申請專利範圍第8項所述之半導體裝置,其中,該第二放大器電路包括:在第一輸入的RC電路,其中,該分壓電壓信號被提供給該第一輸入;以及第二輸入,其中,該輸出信號被提供給該第二輸入;以及其中,該第一放大器電路及該第二放大器電路的增益頻寬被限於低於射頻通帶。
- 如申請專利範圍第8項所述之半導體裝置,其中,該電流鏡包括電流-電壓轉換器,其經配置以將電流信號轉換成該與電流成比例的電壓信號。
- 如申請專利範圍第8、11或12項所述之半導體裝置,其中,該第一電晶體及第二電晶體是FD SOI電晶體的至少其中之一,其中,該FD SOI電晶體是FD SOI LVT電晶體、FD SOI SLVT電晶體、FD SOI RVT電晶體或FD SOI HVT電晶體的至少其中之一。
- 一種形成半導體裝置之系統,包括:半導體裝置製程系統,用以加工半導體晶圓以製造半導體裝置,其中,半導體裝置製程系統包括:設計單元,經配置以提供製造該半導體裝置的參數,該半導體裝置包括:信號處理單元,用以處理輸入信號以提供輸出信號,該信號處理單元包括:第一電晶體及第二電晶體,其中,該第一電晶體包括與第一前閘極電性耦接的第一後閘極;以及第二電晶體,與該第一電晶體操作性耦接,其中,該第二電晶體包括與第二前閘極電性耦接的第二後閘極;增益電路,用以在該輸出信號上提供增益;以及偏置電路,用以向該第一後閘極提供第一偏置信號並向該第二後閘極提供第二偏置信號;以及製程控制器,操作性耦接該半導體裝置製程系統,該製程控制器經配置而控制該半導體裝置製程系統的操作,以製造該半導體裝置。
- 如申請專利範圍第17項所述之系統,其中,該偏置電路包括:分壓器電路,用以提供分壓電壓信號;電流鏡,用以基於該分壓電壓信號提供與電流成比例的電壓信號;第一放大器電路,經配置以接收該與電流成比例的電壓信號以及電流基準電壓信號並提供該第二偏置信號;以及第二放大器電路,經配置以接收該分壓電壓信號以及該輸出信號並提供該第一偏置信號。
- 如申請專利範圍第18項所述之系統,其中,該第二放大器電路包括:在第一輸入的RC電路,其中,該分壓電壓信號被提供給該第一輸入;以及第二輸入,其中,該輸出信號被提供給該第二輸入;以及其中,該第一放大器電路及該第二放大器電路的單位增益頻寬大於該輸入信號的頻率。
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Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10079597B1 (en) * | 2017-03-15 | 2018-09-18 | Globalfoundries Inc. | Circuit tuning scheme for FDSOI |
US10312365B1 (en) * | 2018-02-02 | 2019-06-04 | Avago Technologies International Sales Pte. Limited | Laterally diffused MOSFET on fully depleted SOI having low on-resistance |
US11916026B2 (en) * | 2018-08-16 | 2024-02-27 | Qualcomm Incorporated | High voltage supply clamp |
US10777558B1 (en) | 2019-03-13 | 2020-09-15 | Globalfoundries Inc. | CMOS-based integrated circuit products with isolated P-wells for body-biasing transistor devices |
US10644374B1 (en) * | 2019-03-27 | 2020-05-05 | Globalfoundries Inc. | Multi-channel power combiner with phase adjustment |
US10734979B1 (en) * | 2019-07-03 | 2020-08-04 | Globalfoundries Inc. | Analog-to-digital inverter circuit structure with FDSOI transistors |
US10747254B1 (en) * | 2019-09-03 | 2020-08-18 | Globalfoundries Inc. | Circuit structure for adjusting PTAT current to compensate for process variations in device transistor |
US11081973B1 (en) * | 2019-10-30 | 2021-08-03 | Dialog Semiconductor B.V. | High voltage tolerant inverter |
FR3104344B1 (fr) * | 2019-12-06 | 2021-12-24 | Commissariat Energie Atomique | Circuit électronique de diviseur de tension en technologie FDSOI |
US11271079B2 (en) | 2020-01-15 | 2022-03-08 | Globalfoundries U.S. Inc. | Wafer with crystalline silicon and trap rich polysilicon layer |
US11296190B2 (en) | 2020-01-15 | 2022-04-05 | Globalfoundries U.S. Inc. | Field effect transistors with back gate contact and buried high resistivity layer |
CN111898334B (zh) * | 2020-08-04 | 2022-02-01 | 深圳比特微电子科技有限公司 | 用于系统级芯片设计的标准单元及应用其的数据处理单元、运算芯片和计算设备 |
US11556751B2 (en) | 2021-05-29 | 2023-01-17 | Nxp B.V. | RFID tag limiter |
US11411492B1 (en) * | 2021-05-29 | 2022-08-09 | Nxp B.V. | Self limiting charge pump |
FR3129004A1 (fr) * | 2021-11-05 | 2023-05-12 | Stmicroelectronics (Grenoble 2) Sas | Circuit d’alimentation |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5892260A (en) * | 1995-01-27 | 1999-04-06 | Nec Corporation | SOI-type semiconductor device with variable threshold voltages |
US7180135B1 (en) * | 2003-10-06 | 2007-02-20 | George Mason Intellectual Properties, Inc. | Double gate (DG) SOI ratioed logic with intrinsically on symmetric DG-MOSFET load |
US20080143423A1 (en) * | 2006-12-18 | 2008-06-19 | Shigenobu Komatsu | Semiconductor integrated circuit and manufacturing method therefor |
US20100201429A1 (en) * | 2005-08-01 | 2010-08-12 | Renesas Technology Corp. | Semiconductor device and semiconductor integrated circuit using the same |
US20130082780A1 (en) * | 2011-09-30 | 2013-04-04 | Ravi K. Kummaraguntla | Accuracy power detection unit |
US20140173544A1 (en) * | 2012-12-13 | 2014-06-19 | Stmicroelectronics Sa | Method for generating a topography of an fdsoi integrated circuit |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0143252B1 (ko) * | 1995-06-30 | 1998-07-01 | 김주용 | 3중웰 형성방법 |
JP4282388B2 (ja) * | 2003-06-30 | 2009-06-17 | 株式会社東芝 | 半導体記憶装置 |
JP2007179602A (ja) * | 2005-12-27 | 2007-07-12 | Hitachi Ltd | 半導体装置 |
US7479418B2 (en) * | 2006-01-11 | 2009-01-20 | International Business Machines Corporation | Methods of applying substrate bias to SOI CMOS circuits |
US7759714B2 (en) * | 2007-06-26 | 2010-07-20 | Hitachi, Ltd. | Semiconductor device |
US7791139B2 (en) * | 2007-07-27 | 2010-09-07 | Infineon Technologies Austria Ag | Integrated circuit including a semiconductor assembly in thin-SOI technology |
WO2009039169A1 (en) * | 2007-09-17 | 2009-03-26 | Innovative Silicon S.A. | Refreshing data of memory cells with electrically floating body transistors |
US20090101940A1 (en) * | 2007-10-19 | 2009-04-23 | Barrows Corey K | Dual gate fet structures for flexible gate array design methodologies |
WO2010007478A1 (en) * | 2008-06-13 | 2010-01-21 | Yale University | Improved complementary metal oxide semiconductor devices |
KR101623958B1 (ko) * | 2008-10-01 | 2016-05-25 | 삼성전자주식회사 | 인버터 및 그의 동작방법과 인버터를 포함하는 논리회로 |
US8131225B2 (en) * | 2008-12-23 | 2012-03-06 | International Business Machines Corporation | BIAS voltage generation circuit for an SOI radio frequency switch |
US8415743B2 (en) * | 2011-05-24 | 2013-04-09 | International Business Machines Corporation | ETSOI CMOS with back gates |
US8552500B2 (en) * | 2011-05-24 | 2013-10-08 | International Business Machines Corporation | Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability |
US20130140442A1 (en) * | 2011-12-02 | 2013-06-06 | Sony Corporation | Amplifying circuit and manufacturing method, solid-state imaging element, and electronic device |
US8994085B2 (en) * | 2012-01-06 | 2015-03-31 | International Business Machines Corporation | Integrated circuit including DRAM and SRAM/logic |
FR2999802A1 (fr) * | 2012-12-14 | 2014-06-20 | St Microelectronics Sa | Cellule cmos realisee dans une technologie fd soi |
US20150129967A1 (en) * | 2013-11-12 | 2015-05-14 | Stmicroelectronics International N.V. | Dual gate fd-soi transistor |
FR3024917B1 (fr) * | 2014-08-13 | 2016-09-09 | St Microelectronics Sa | Procede de minimisation de la tension de fonctionnement d'un point memoire de type sram |
-
2016
- 2016-05-06 US US15/148,668 patent/US9923527B2/en active Active
-
2017
- 2017-03-16 TW TW106108704A patent/TWI647777B/zh active
- 2017-05-08 CN CN201710317142.4A patent/CN107452798B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5892260A (en) * | 1995-01-27 | 1999-04-06 | Nec Corporation | SOI-type semiconductor device with variable threshold voltages |
US7180135B1 (en) * | 2003-10-06 | 2007-02-20 | George Mason Intellectual Properties, Inc. | Double gate (DG) SOI ratioed logic with intrinsically on symmetric DG-MOSFET load |
US20100201429A1 (en) * | 2005-08-01 | 2010-08-12 | Renesas Technology Corp. | Semiconductor device and semiconductor integrated circuit using the same |
US20080143423A1 (en) * | 2006-12-18 | 2008-06-19 | Shigenobu Komatsu | Semiconductor integrated circuit and manufacturing method therefor |
US20130082780A1 (en) * | 2011-09-30 | 2013-04-04 | Ravi K. Kummaraguntla | Accuracy power detection unit |
US20140173544A1 (en) * | 2012-12-13 | 2014-06-19 | Stmicroelectronics Sa | Method for generating a topography of an fdsoi integrated circuit |
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US9923527B2 (en) | 2018-03-20 |
TW201812951A (zh) | 2018-04-01 |
CN107452798B (zh) | 2021-01-15 |
CN107452798A (zh) | 2017-12-08 |
US20170324385A1 (en) | 2017-11-09 |
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