US20130082780A1 - Accuracy power detection unit - Google Patents
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- H03G3/30—Automatic control in amplifiers having semiconductor devices
Definitions
- This disclosure relates generally to processing radio frequency (RF) signals, and, more specifically, to RF power detection.
- RF radio frequency
- RF circuits typically perform a variety of operations to process a received signal. Such operations may include filtering the signal, demodulating it, sampling it, etc. In order to perform some of these operations, various circuits in the receiver chain may require that the RF signal have a signal strength within a particular range (e.g., a range of 60-80 dB). Often, however, an RF signal is too weak by the time it arrives at the receiver. To account for this, the receiver may attempt to amplify the signal before processing it further.
- a particular range e.g., a range of 60-80 dB
- RF circuits employ a feedback loop in which an incoming signal passes through an amplifier and then a power detector, which measures the signal's power. If the signal strength is too high or too low, the RF circuit adjusts the gain of amplifier accordingly.
- This form of feedback loop is commonly referred to as an automatic gain control (AGC) system.
- AGC automatic gain control
- the present disclosure describes structures and methods for improving the accuracy of multiplier circuits and power detection circuits.
- a power detection unit in one embodiment, includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair.
- the multiplier circuit is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages.
- sources of the first transistor pair are coupled to sources of the second transistor pair, and the sources of the second transistor pair are coupled together.
- the power detection unit includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair.
- the multiplier circuit is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages.
- the power detection unit is configured to adjust a threshold voltage of a transistor in the first transistor pair and a threshold voltage of a transistor in the second transistor pair.
- a method in still another embodiment, includes providing positive and negative voltage differential signals to gates of first and second transistor pairs in a multiplier circuit.
- the multiplier circuit is configured to output a current that varies proportionally to a square of a voltage difference between the gates of the first transistor pair and the gates of the second transistor pair.
- the method further includes determining whether the multiplier circuit produces the same current in response to the positive and negative voltage differential signals.
- the method further includes applying offset voltages to a body of a transistor in the first transistor pair and a body of a transistor in the second transistor pair based on the determining.
- FIG. 1 is a block diagram illustrating one embodiment of an RF circuit configured to amplify a received RF signal based on its power.
- FIG. 2 is a block diagram illustrating one embodiment of a power detection unit within the RF circuit.
- FIGS. 3A and 3B are block diagrams illustrating embodiments of a multiplier circuit within the power detection unit.
- FIG. 4 is a graph illustrating examples of ideal and non-ideal transfer functions of a multiplier circuit.
- FIG. 5 is a flow diagram illustrating one embodiment of a method for calibrating transistors in a multiplier circuit.
- FIG. 6 is a block diagram illustrating one embodiment of a calibration unit configured to apply offset voltages to transistors in a multiplier circuit.
- FIG. 7 is a flow diagram illustrating one embodiment of a method for calibrating output offsets for multiplier circuits.
- FIG. 8 is a block diagram illustrating one embodiment of an offset output unit configured to apply an output offset to a multiplier circuit.
- the present disclosure describes embodiments of a power detection unit and embodiments of circuitry, which may be included within such a unit.
- the accuracy of the power detection unit may be affected by various factors, which can reduce performance of the unit.
- the power detection unit in various embodiments, may employ any of variety of techniques such as described below. It is noted that, while certain techniques are described within the context of power detection, such techniques may also be applicable to other applications in some embodiments.
- RF circuit 100 in one embodiment of an automatic gain control (AGC) system that is configured to amplify a received RF input signal 102 based on its strength (i.e., power).
- AGC automatic gain control
- RF circuit 100 includes an adjustable amplifier 110 , power detection unit 120 , and a control unit 130 .
- RF circuit 100 may be used in various applications such as television receivers, cellular phones, modems, network devices, satellite radios, etc.
- RF circuit 100 may be used in wireless devices; in other embodiments, RF circuit 100 may be used in wired devices. In short, RF circuit 100 may be used in any suitable application.
- RF circuit 100 provides an incoming RF signal 102 to adjustable amplifier 110 to produce an amplified output signal 104 .
- power detection unit 120 measures the power of signal 104 and indicates the result to control unit 130 .
- Control unit 130 (which may be implement using a microcontroller, in some embodiments) is configured to then adjust the gain of amplifier 110 so that the amplified output signal 104 falls within a desired range for circuit 100 . Accordingly, control unit 130 may increase or decrease the gain of amplifier 110 depending on whether signal 104 is too strong or too weak, respectively.
- the amplified output signal 104 may then be provided to additional circuitry (not shown) in a receiver chain for further processing.
- power detection unit 120 may measure the power of signal 104 by using one or more multiplier circuits that are configured to perform a squaring operation (since the power of a signal varies proportional to the square of the signal's voltage as defined by the combination of Joule's law and Ohm's law). In many instances, the accuracy of power detection unit 120 is dependent on the accuracy of its multipliers. In various embodiments described below, power detection unit 120 may employ various techniques to improve their accuracy.
- power detection unit 120 includes multipliers 210 A and 210 B, current sources 216 A and 216 B, a comparison unit 220 , and an output offset unit 250 .
- power detection unit 120 may include additional multipliers 210 , current sources 216 , comparison units 220 , and/or output offset units 250 .
- Multiplier 210 A in one embodiment, is configured to square the voltage of a signal (such as RF signal 104 , in one embodiment) to determine its power.
- multiplier 210 A receives the signal as a voltage differential signal 202 (a signal represented by the difference between voltages V in + and V in ⁇ ), and produces a corresponding current signal I in 212 that varies proportionally to the square of the voltage of signal 202 such that I in ⁇ (V in + ⁇ V in ⁇ ) 2 .
- Multiplier 210 B in one embodiment, is configured to generate a reference signal for comparison with the signal produced by multiplier 210 A.
- multiplier 210 B receives a voltage reference signal as a differential voltage signal 204 (again, the signal represented by the difference between voltages V Ref + and V Ref ⁇ ) and produces a corresponding reference current signal I Ref 214 that varies proportionally to the square of the voltage of signal 204 such that I Ref ⁇ (V Ref + ⁇ V Ref ⁇ ) 2 .
- current sources 216 are used to shift the respective input signal independent DC currents 212 and 214 to prepare them for comparison within comparison unit 220 .
- Comparison unit 220 is configured to compare signals 212 and 214 and to generate a corresponding output signal 242 (i.e., a comparison indication) for control unit 130 .
- signals 212 and 214 pass through respective current-to-voltage converters 230 A and 230 B to produce voltages comparable by voltage comparator 240 (in other embodiments, a current comparator may be used instead).
- converters 230 produce voltages based on initial respective offset voltages (shown as V Offset 222 and V Offset 224 ; as will be described below, these reference voltages may be adjusted (e.g., using output offset unit 250 ) to compensate for when multipliers 210 produce different currents for the same input).
- comparator 240 compares the voltages and generates a corresponding output signal 242 for control unit 130 . Accordingly, in one embodiment, comparator 240 may output a voltage representative of a logical one for signal 242 if the voltage produced from current 212 is greater than the voltage produced from current 214 , and a logical zero for signal 242 otherwise.
- multipliers 210 may produce a less than ideal square function, which can affect the accuracy of power detection unit 120 .
- a multiplier 210 may produce a square function that has additional factors, which introduce non-linearity into the output current such as V 3 , V 4 , and V 5 factors.
- a multiplier 210 may also produce a square that is asymmetric (such as described in conjunction with FIG. 4 ). Both of these problems may be caused by mismatches of transistors (e.g., caused by impurities in the silicon, variances in the manufacturing of the multipliers 210 , etc.), problems with the circuitry that provides the input signals 202 and 204 for multipliers 210 , etc.
- multipliers 210 may include circuitry (or be coupled to circuitry) that is configured to correct the square function (i.e., make it closer to ideal) such as described below in conjunction with FIGS. 2-6 .
- output offset unit 250 is configured to change voltage 224 to cause converter 230 B change the DC offset of the voltage provided to comparator 240 (and, thus, the output offset of multiplier 210 B) in order to compensate for the difference in output currents.
- Output offset unit 250 is described in further detail below in conjunction with FIGS. 7 and 8 .
- multiplier 210 includes capacitors 310 A and 310 B, transistors 320 A-D, current source 330 , and DC input unit 340 , which, in turn, includes current source 342 , transistors 344 A and 344 B, resistors 346 A 1 -B 2 , and a ground reference 348 .
- capacitor 310 A is coupled to the gates of transistors 320 A and 320 C, which form a first transistor pair.
- Capacitor 310 B is coupled to the gates of transistors 320 B and 320 D, which form a second transistor pair.
- transistors 320 A and 320 B are coupled respectively to current source 330 and ground reference 334 A.
- the sources of transistors 320 A and 320 B are coupled via line 336 to sources of transistors 320 C and 320 D.
- the drains and bodies of transistors 320 C and 320 D are respectively coupled to ground reference 334 B and voltage source V DD .
- transistors 320 A and 320 B are N-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) and transistors 320 C and 320 D P-type MOSFETS (pMOSFETS).
- multiplier 210 receives voltages 302 A and 302 B of a voltage differential signal (e.g., signal 202 or signal 204 ) at capacitors 310 A and 310 B, which high-pass filter the signal to remove its DC component and leave only its AC component when it arrives at the gates of transistors 320 .
- the DC component at the gates of transistors 320 is supplied by DC input unit 340 .
- These DC and AC components change the gate-to-source voltages of transistors 320 causing them to source (i.e., pull) current from current source 330 .
- the remaining current from current source 330 which does not pass through transistors 320 , becomes the output current 304 of multiplier circuit 210 shown as I out .
- multiplier 210 is configured to vary the current I out proportionally to the square of the voltage difference between voltages 302 A and 302 B.
- transistors 320 A and 320 B may be mismatched relative to transistors 320 C and 320 D such that a body effect would normally (i.e., without the benefit of line 336 ) introduce unwanted nonlinearity into I out such as V 3 , V 4 , V 5 factors.
- a mismatch may occur, for example, if transistor 320 A has a lower threshold voltage than the threshold voltage of transistor 320 C.
- One approach for canceling out this nonlinearity is to couple to the bodies of transistors 320 A and 320 B to their respective sources, which reduces their body-to-source voltages. A problem with this approach is that it also increases the parasitic capacitances of transistors 320 A and 320 B, which can reduce RF performance.
- a better approach is to couple the sources of transistors 320 via line 336 as shown in the illustrated embodiment. In many instances, the insertion of line 336 can reduce the presence of nonlinearity without compromising RF performance.
- multiplier 210 may still produce a square function that is asymmetric due to the presence of offsets. These offsets may be introduced by the circuitry providing signals 302 , a mismatch of transistors 320 A and 320 B, a mismatch of transistors 320 C and 320 D, etc. In some embodiments, multiplier 210 may further include a threshold-voltage calibration unit 350 to compensate for these problems such as described next.
- multiplier 210 includes the same elements 302 - 348 as shown in FIG. 3A , except that the bodies of transistors 320 C and 320 D are no longer coupled to a voltage source V DD and, instead, are coupled to a calibration unit 350 via lines 352 and 354 .
- calibration unit 350 is configured to apply offset voltages (i.e., different voltages) to the bodies (i.e., back gates) of transistors 320 C and 320 D via lines 352 and 354 to change their respective threshold voltages. By changing the threshold voltages, calibration unit 350 is configured to compensate for unwanted DC offsets, which can produce an asymmetric squaring function such as described next with FIG. 4 .
- multiplier 210 may receive a voltage input (or differential voltage input) shown within the range of ⁇ 300 mV to 300 mV, in the illustrated embodiment. Multiplier 210 may then produce a corresponding current shown within the range of 10 to 35 ⁇ A, in the illustrated embodiment. Since a square function is parabolic function that produces the same output for a given input regardless of its sign, the ideal (i.e., correct) transfer function for a multiplier 210 is a squaring function centered around the 0 V origin such as transfer function 402 .
- Transfer function 402 illustrates this as it has the same output current (e.g., 24 ⁇ A) regardless of a given input's sign (e.g., ⁇ 200 mV vs. 200 mV).
- multiplier 210 may, in some instances, produce an asymmetric (i.e., non-ideal) squaring function such as transfer function 404 .
- transfer function 404 is shifted by a negative DC offset of 30 mV.
- a ⁇ 200 mV input voltage produces 20 ⁇ A current while a 200 mV input voltage produces a 26 ⁇ A current.
- calibration unit 350 may be configured to detect this shift and apply an appropriate set of offset voltages to compensate for it.
- Method 500 is one embodiment of a method that may be performed by a circuit that includes a multiplier circuits such as power detection unit 120 or a circuit that is included within a multiplier circuit such as calibration unit 350 .
- method 500 may be performed as part of an initial calibration for a circuit (such as during the circuit's startup, during testing of the circuit by automated testing equipment (ATE), etc.).
- ATE automated testing equipment
- performance of method 500 can improve the accuracy of a multiplier circuit.
- signals having positive and negative voltages are provided to gates of a multiplier circuit (e.g., as voltages 302 at gates of transistors 320 ) to cause the multiplier circuit output corresponding currents T out .
- step 520 the output currents (e.g., the 20 ⁇ A current and the 26 ⁇ A current described above) are measured to determine whether the multiplier circuit produces the same current in response to both signals—thus, indicating that the multiplier has an ideal or non-ideal transfer function.
- step 520 may include measuring the currents by using an analog-to-digital converter (ADC) as shown in substep 522 .
- ADC analog-to-digital converter
- this ADC may be located within calibration unit 350 (e.g., within control unit 670 described below). In other embodiments, this ADC may be located elsewhere within multiplier 210 or RF circuit 100 .
- step 520 may include usage of an array of comparators to measure the currents.
- step 530 offset voltages are applied (e.g., by a calibration unit 350 ) to bodies of transistors (e.g., transistors 320 C and 320 D) of the multiplier based on the determination in step 520 .
- the amount of offset voltages may be selected in substep 532 based on the currents measured by an ADC in step 522 . For example, greater offset voltages may be selected if the measured currents differ by a significant amount.
- step 530 may also include not applying offset voltages (in other words, applying the same voltage) if the currents are not different or have negligible differences within permissible tolerances that do not heavily impact the accuracy of the multiplier.
- a multiplier 210 is considered to produce an ideal transfer function if the input referred offset voltage for the multiplier is within +/ ⁇ 1 mV of 0V.
- calibration unit 350 may be configured to generate the offset voltages (e.g., during step 530 ) by passing a current through a resistor ladder that includes a plurality of resistors coupled together in series. Calibration unit 350 may select various ones of the resistors to select a desired offset voltage. In some embodiments, calibration unit 350 is further configured to change the generated offset voltage of a selected resistor by coupling a resistor in parallel with one of the plurality of resistors in the resistor ladder.
- calibration unit 350 includes current sources 610 A and 610 B, resistors 620 A-F (which are coupled together in series and may collectively be referred to herein as a “resistor ladder”), transistors 630 A-F, transistors 640 AD, and a voltage reference 650 , transistors 660 A and 660 B, and resistors 662 A and 662 B.
- Calibration unit 350 also includes a control unit 670 to manage operation of unit 350 .
- calibration unit 350 may include additional resistors 620 and transistors 630 .
- calibration unit 350 is configured to apply offset voltages to the bodies of transistors 320 C and 320 D.
- calibration unit 350 generates the voltages by passing a current from current source 610 A through resistors 620 . The voltages are generated around a common-mode voltage V cm received from reference 650 .
- Calibration unit 350 controls which voltages are selected by switching on or off transistors 630 .
- Calibration unit 350 then routes the selected voltages out to lines 352 and 354 by using transistors 640 .
- calibration unit 350 may select the voltage created by the voltage drop across resistor 620 A to by activating transistor 630 A.
- Calibration unit 350 may then route the voltage to line 354 by activating transistor 640 B.
- calibration unit 350 is configured to further control the selection of offset voltages by using transistors 660 A and 660 B to couple one or both of resistors 662 in parallel with resistors 620 C and 620 D, respectively. By doing so, calibration unit 350 is able to reduce the voltage drop across resistors 620 C and 620 D (e.g., by a half when resistors 662 and 620 have the same resistance). Thus, if a particular desired offset voltage falls between a pair of voltages selectable by using transistors 630 (e.g., between 30 mV and 35 mV), calibration unit 350 can couple a resistor 662 to change the voltage so that it falls within the desired range (e.g., 32.5 mV).
- desired range e.g. 32.5 mV
- control unit 670 is configured to determine whether offset voltages are needed and to control the selection of offset voltages using transistors 630 , 640 , and 660 . Thus, in some embodiments, control unit 670 may perform (or facilitate performance of) method 500 described above. Accordingly, in some embodiments, control unit 670 is configured to select the appropriate pair of offset voltages based on the difference in the produced currents. In other embodiments, however, control unit 670 may be configured to test multiple pairs of offset voltages until it can determine the best pair based on trial-and-error.
- control unit 670 may need to apply the same pair of offset voltages twice to test both arrangements of the voltages (i.e., the arrangement in which a first voltage and a second voltage are applied respectively to transistors 320 C and 320 D, and the arrangement in which the second voltage and the first voltage are applied respectively to transistors 320 C and 320 D).
- calibration unit 350 may be able to correct a non-ideal transfer function of a multiplier 210 , a pair of multipliers 210 may still produce different currents relative to one another given the same input.
- the method described next, in many instances, is able to account for this additional problem.
- Method 700 is one embodiment of a method that may be performed by a circuit that includes multipliers (such as power detection unit 120 ) or circuit coupled to a multiplier such as output offset unit 250 . Like method 500 , method 700 , in some embodiments, may be performed as part of an initial calibration for the circuit (such as during the circuit's startup, during testing of the circuit by automated testing equipment (ATE), etc.).
- ATE automated testing equipment
- step 710 the same input is provided to a pair of multipliers (e.g., multipliers 210 ) coupled to a comparator (e.g., comparator 240 ).
- this signal may be a voltage differential signal, and the multipliers may produce currents that vary proportional to the square of the input signal (e.g., I in 212 and I REF 214 , described above).
- step 720 adjustments are made to the output offset for one of the multipliers (e.g., multiplier 210 B; in other embodiments, adjustments to output offsets for both multipliers may be made) by a full offset value and starting from an initial value.
- output offset unit 250 may be configured to produce a range of voltages for converter 230 B. Unit 250 may start at the lower part of the range and begin increasing the voltages by a particular amount (i.e., a “full offset value”) causing converter 230 to produce a voltage with an increasing DC offset. For example, unit 250 may cause converter 230 B to increase the DC offset of produced voltages by 1 mV increments until reaching step 730 .
- step 730 a change in the output of the comparator is detected. Since the multipliers are being provided the same input in step 710 , this change in the output at the comparator indicates that the inputs of the comparator are now similar. For example, if the output of converter 230 A is 99.5 mV for the given input and the output of converter 230 B is 99 mV, an adjustment in step 720 , which causes converter 230 B to produce 100 mV, will produce a change in the output of comparator 240 —thus, indicating that the inputs are similar.
- step 740 the multiplier output offset is adjusted back by half an offset value after the change in step 730 is detected. For example, if adjustments of 1 mV are being made in step 720 and the output of converter 230 B changes from 99 mV to 100 mV, an adjustment back to 99.5 mV would be made in the illustrated embodiment since 0.5 mV is half of 1 mV. In this way, step 740 is able to better compensate for an over adjustment in step 720 . In other words, adjusting the output of converter 230 B back to 99.5 mV is closer to the 99.5 mV output by converter 230 A than the initial 100 mV output at the end of step 720 .
- output offset unit 250 is configured to produce voltages for converter 230 B by passing a current through a resistor ladder and selecting various ones of the resistors (such as described with calibration unit 350 ). In some embodiments, output offset unit 250 is also configured to change the generated voltage of a selected resistor by coupling a resistor in parallel with one of the resistors in the resistor ladder.
- output offset unit 250 includes current sources 810 A-C, transistors 820 A-D, resistors 830 A-E, transistors 840 A-C, voltage reference 850 , transistor 860 , and resistor 862 .
- Output offset unit 250 also includes a control unit 870 to manage operation of unit 250 .
- output offset unit 250 may include additional resistors 830 and transistors 840 .
- output offset unit 250 generates the offset voltages by passing a current from current source 810 A through resistors 830 . The voltages are generated around a common-mode voltage V cm received from reference 850 . Output offset unit 250 then controls which voltages are selected and provided to converter 230 B by activating transistors 840 . To reduce the number of resistors 830 (which can be substantially large, in some embodiments), output offset unit 250 , in the illustrated embodiment, is configured to use transistors 820 to change the direction of the current flowing through resistors 830 .
- output offset unit 250 is able to produce voltages lower than V cm by causing the current generated by source 810 A to flow from node 850 to current source 810 C, instead of through resistors 830 to current source 810 B.
- unit 250 may include additional resistors after node 850 to produce voltages lower than V cm .
- output offset unit 250 is also configured to couple resistor 862 in parallel with resistor 830 E to reduce the voltage drop across resistors 830 E (e.g., by a half when resistors 862 and 820 E have the same resistance).
- output offset unit 250 can couple resistor 862 to change the voltage so that it falls within the desired range (e.g., 99.5 mV).
- control unit 870 is configured to determine which output offset to apply and control transistors 820 , 840 , and 860 , accordingly. As discussed above in conjunction with method 700 , in one embodiment, control unit 870 is configured to determine the output offset based on when output 242 of comparator 240 changes.
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Abstract
Description
- 1. Technical Field
- This disclosure relates generally to processing radio frequency (RF) signals, and, more specifically, to RF power detection.
- 2. Description of the Related Art
- RF circuits typically perform a variety of operations to process a received signal. Such operations may include filtering the signal, demodulating it, sampling it, etc. In order to perform some of these operations, various circuits in the receiver chain may require that the RF signal have a signal strength within a particular range (e.g., a range of 60-80 dB). Often, however, an RF signal is too weak by the time it arrives at the receiver. To account for this, the receiver may attempt to amplify the signal before processing it further.
- In many instances, RF circuits employ a feedback loop in which an incoming signal passes through an amplifier and then a power detector, which measures the signal's power. If the signal strength is too high or too low, the RF circuit adjusts the gain of amplifier accordingly. This form of feedback loop is commonly referred to as an automatic gain control (AGC) system.
- The present disclosure describes structures and methods for improving the accuracy of multiplier circuits and power detection circuits.
- In one embodiment, a power detection unit is disclosed. The power detection unit includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair. The multiplier circuit is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages. In such an embodiment, sources of the first transistor pair are coupled to sources of the second transistor pair, and the sources of the second transistor pair are coupled together.
- In another embodiment, power detection unit is disclosed. The power detection unit includes a multiplier circuit configured to receive a first voltage of a voltage differential signal at gates of a first transistor pair and a second voltage of the voltage differential signal at gates of a second transistor pair. The multiplier circuit is configured to output a current that varies proportionally to a square of a voltage difference between the first and second voltages. The power detection unit is configured to adjust a threshold voltage of a transistor in the first transistor pair and a threshold voltage of a transistor in the second transistor pair.
- In still another embodiment, a method is disclosed. The method includes providing positive and negative voltage differential signals to gates of first and second transistor pairs in a multiplier circuit. The multiplier circuit is configured to output a current that varies proportionally to a square of a voltage difference between the gates of the first transistor pair and the gates of the second transistor pair. The method further includes determining whether the multiplier circuit produces the same current in response to the positive and negative voltage differential signals. The method further includes applying offset voltages to a body of a transistor in the first transistor pair and a body of a transistor in the second transistor pair based on the determining.
-
FIG. 1 is a block diagram illustrating one embodiment of an RF circuit configured to amplify a received RF signal based on its power. -
FIG. 2 is a block diagram illustrating one embodiment of a power detection unit within the RF circuit. -
FIGS. 3A and 3B are block diagrams illustrating embodiments of a multiplier circuit within the power detection unit. -
FIG. 4 is a graph illustrating examples of ideal and non-ideal transfer functions of a multiplier circuit. -
FIG. 5 is a flow diagram illustrating one embodiment of a method for calibrating transistors in a multiplier circuit. -
FIG. 6 is a block diagram illustrating one embodiment of a calibration unit configured to apply offset voltages to transistors in a multiplier circuit. -
FIG. 7 is a flow diagram illustrating one embodiment of a method for calibrating output offsets for multiplier circuits. -
FIG. 8 is a block diagram illustrating one embodiment of an offset output unit configured to apply an output offset to a multiplier circuit. - This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.
- The present disclosure describes embodiments of a power detection unit and embodiments of circuitry, which may be included within such a unit. As will be described below, the accuracy of the power detection unit may be affected by various factors, which can reduce performance of the unit. To account for such factors, the power detection unit, in various embodiments, may employ any of variety of techniques such as described below. It is noted that, while certain techniques are described within the context of power detection, such techniques may also be applicable to other applications in some embodiments.
- Turning now to
FIG. 1 , a block diagram of anRF circuit 100 is depicted.RF circuit 100 in one embodiment of an automatic gain control (AGC) system that is configured to amplify a receivedRF input signal 102 based on its strength (i.e., power). As shown,RF circuit 100 includes anadjustable amplifier 110,power detection unit 120, and acontrol unit 130.RF circuit 100 may be used in various applications such as television receivers, cellular phones, modems, network devices, satellite radios, etc. In some embodiments,RF circuit 100 may be used in wireless devices; in other embodiments,RF circuit 100 may be used in wired devices. In short,RF circuit 100 may be used in any suitable application. - In the illustrated embodiment,
RF circuit 100 provides anincoming RF signal 102 toadjustable amplifier 110 to produce an amplifiedoutput signal 104. In one embodiment,power detection unit 120 measures the power ofsignal 104 and indicates the result tocontrol unit 130. Control unit 130 (which may be implement using a microcontroller, in some embodiments) is configured to then adjust the gain ofamplifier 110 so that the amplifiedoutput signal 104 falls within a desired range forcircuit 100. Accordingly,control unit 130 may increase or decrease the gain ofamplifier 110 depending on whethersignal 104 is too strong or too weak, respectively. In various embodiments, the amplifiedoutput signal 104 may then be provided to additional circuitry (not shown) in a receiver chain for further processing. - In many instances, the accuracy of
power detection unit 120 is important for ensuring thatsignal 102 is amplified appropriately. Ifpower detection unit 120 were to have a large offset error,amplifier 110 might overamplify signal 102 causing saturation problems or underamplify signal 102 making it too weak to process. As will be described next in conjunction withFIG. 2 , in various embodiments,power detection unit 120 may measure the power ofsignal 104 by using one or more multiplier circuits that are configured to perform a squaring operation (since the power of a signal varies proportional to the square of the signal's voltage as defined by the combination of Joule's law and Ohm's law). In many instances, the accuracy ofpower detection unit 120 is dependent on the accuracy of its multipliers. In various embodiments described below,power detection unit 120 may employ various techniques to improve their accuracy. - Turning now to
FIG. 2 , one embodiment ofpower detection unit 120 is depicted. In the illustrated embodiment,power detection unit 120 includesmultipliers current sources comparison unit 220, and anoutput offset unit 250. In some embodiments,power detection unit 120 may includeadditional multipliers 210, current sources 216,comparison units 220, and/or output offsetunits 250. -
Multiplier 210A, in one embodiment, is configured to square the voltage of a signal (such asRF signal 104, in one embodiment) to determine its power. In the illustrated embodiment,multiplier 210A receives the signal as a voltage differential signal 202 (a signal represented by the difference between voltages Vin + and Vin −), and produces a corresponding current signal Iin 212 that varies proportionally to the square of the voltage ofsignal 202 such that Iin≈(Vin +−Vin −)2. An example illustrating this relationship is described in further detail below in conjunction withFIG. 4 . -
Multiplier 210B, in one embodiment, is configured to generate a reference signal for comparison with the signal produced bymultiplier 210A. In the illustrated embodiment,multiplier 210B receives a voltage reference signal as a differential voltage signal 204 (again, the signal represented by the difference between voltages VRef + and VRef −) and produces a corresponding reference current signal IRef 214 that varies proportionally to the square of the voltage ofsignal 204 such that IRef≈(VRef +−VRef −)2. - In the illustrated embodiment, current sources 216 are used to shift the respective input signal
independent DC currents comparison unit 220. -
Comparison unit 220, in one embodiment, is configured to comparesignals control unit 130. In the illustrated embodiment, signals 212 and 214 pass through respective current-to-voltage converters V Offset 222 andV Offset 224; as will be described below, these reference voltages may be adjusted (e.g., using output offset unit 250) to compensate for whenmultipliers 210 produce different currents for the same input). After converters 230 have produced corresponding voltages,comparator 240 compares the voltages and generates acorresponding output signal 242 forcontrol unit 130. Accordingly, in one embodiment,comparator 240 may output a voltage representative of a logical one forsignal 242 if the voltage produced from current 212 is greater than the voltage produced from current 214, and a logical zero forsignal 242 otherwise. - In some instances,
multipliers 210 may produce a less than ideal square function, which can affect the accuracy ofpower detection unit 120. For example, amultiplier 210 may produce a square function that has additional factors, which introduce non-linearity into the output current such as V3, V4, and V5 factors. Amultiplier 210 may also produce a square that is asymmetric (such as described in conjunction withFIG. 4 ). Both of these problems may be caused by mismatches of transistors (e.g., caused by impurities in the silicon, variances in the manufacturing of themultipliers 210, etc.), problems with the circuitry that provides the input signals 202 and 204 formultipliers 210, etc. In various embodiments,multipliers 210 may include circuitry (or be coupled to circuitry) that is configured to correct the square function (i.e., make it closer to ideal) such as described below in conjunction withFIGS. 2-6 . - Another problem is that
multipliers 210 may produce near-ideal square functions, but produce slightly different currents given the same input signal, which also affects the accuracy ofpower detection unit 120. In the illustrated embodiment, output offsetunit 250 is configured to changevoltage 224 to causeconverter 230B change the DC offset of the voltage provided to comparator 240 (and, thus, the output offset ofmultiplier 210B) in order to compensate for the difference in output currents. Output offsetunit 250 is described in further detail below in conjunction withFIGS. 7 and 8 . - Turning now to
FIG. 3A , one embodiment of amultiplier 210 is depicted. In the illustrated embodiment,multiplier 210 includescapacitors transistors 320A-D,current source 330, andDC input unit 340, which, in turn, includescurrent source 342,transistors 344A and 344B, resistors 346A1-B2, and aground reference 348. As shown,capacitor 310A is coupled to the gates oftransistors Capacitor 310B is coupled to the gates oftransistors transistors current source 330 andground reference 334A. The sources oftransistors line 336 to sources oftransistors transistors ground reference 334B and voltage source VDD. In one embodiment,transistors transistors - In the illustrated embodiment,
multiplier 210 receivesvoltages capacitors DC input unit 340. These DC and AC components change the gate-to-source voltages of transistors 320 causing them to source (i.e., pull) current fromcurrent source 330. The remaining current fromcurrent source 330, which does not pass through transistors 320, becomes theoutput current 304 ofmultiplier circuit 210 shown as Iout. As discussed above,multiplier 210 is configured to vary the current Iout proportionally to the square of the voltage difference betweenvoltages - In some instances,
transistors transistors transistor 320A has a lower threshold voltage than the threshold voltage oftransistor 320C. One approach for canceling out this nonlinearity is to couple to the bodies oftransistors transistors line 336 as shown in the illustrated embodiment. In many instances, the insertion ofline 336 can reduce the presence of nonlinearity without compromising RF performance. - In some instances, the
multiplier 210 may still produce a square function that is asymmetric due to the presence of offsets. These offsets may be introduced by the circuitry providing signals 302, a mismatch oftransistors transistors multiplier 210 may further include a threshold-voltage calibration unit 350 to compensate for these problems such as described next. - Turning now to
FIG. 3B , another embodiment of amultiplier 210 is depicted. In the illustrated embodiment,multiplier 210 includes the same elements 302-348 as shown inFIG. 3A , except that the bodies oftransistors calibration unit 350 vialines FIGS. 4-6 , in various embodiments,calibration unit 350 is configured to apply offset voltages (i.e., different voltages) to the bodies (i.e., back gates) oftransistors lines calibration unit 350 is configured to compensate for unwanted DC offsets, which can produce an asymmetric squaring function such as described next withFIG. 4 . - Turning now to
FIG. 4 , agraph 400 illustrating to examples of twopossible transfer functions multiplier 210 is depicted. As discussed above,multiplier 210 may receive a voltage input (or differential voltage input) shown within the range of −300 mV to 300 mV, in the illustrated embodiment.Multiplier 210 may then produce a corresponding current shown within the range of 10 to 35 μA, in the illustrated embodiment. Since a square function is parabolic function that produces the same output for a given input regardless of its sign, the ideal (i.e., correct) transfer function for amultiplier 210 is a squaring function centered around the 0 V origin such astransfer function 402.Transfer function 402 illustrates this as it has the same output current (e.g., 24 μA) regardless of a given input's sign (e.g., −200 mV vs. 200 mV). Unfortunately,multiplier 210 may, in some instances, produce an asymmetric (i.e., non-ideal) squaring function such astransfer function 404. Here,transfer function 404 is shifted by a negative DC offset of 30 mV. As a result, a −200 mV input voltage produces 20 μA current while a 200 mV input voltage produces a 26 μA current. In various embodiments,calibration unit 350 may be configured to detect this shift and apply an appropriate set of offset voltages to compensate for it. - Turning now to
FIG. 5 , a flow chart of amethod 500 for calibrating transistors in a multiplier circuit is depicted.Method 500 is one embodiment of a method that may be performed by a circuit that includes a multiplier circuits such aspower detection unit 120 or a circuit that is included within a multiplier circuit such ascalibration unit 350. In some embodiments,method 500 may be performed as part of an initial calibration for a circuit (such as during the circuit's startup, during testing of the circuit by automated testing equipment (ATE), etc.). In many instances, performance ofmethod 500 can improve the accuracy of a multiplier circuit. - In
step 510, signals having positive and negative voltages (e.g., a differential signal having a voltage of 200 mV and a differential signal having a voltage of −200 mV such as described withFIG. 4 ) are provided to gates of a multiplier circuit (e.g., as voltages 302 at gates of transistors 320) to cause the multiplier circuit output corresponding currents Tout. - In
step 520, the output currents (e.g., the 20 μA current and the 26 μA current described above) are measured to determine whether the multiplier circuit produces the same current in response to both signals—thus, indicating that the multiplier has an ideal or non-ideal transfer function. In some embodiments,step 520 may include measuring the currents by using an analog-to-digital converter (ADC) as shown in substep 522. In one embodiment, this ADC may be located within calibration unit 350 (e.g., withincontrol unit 670 described below). In other embodiments, this ADC may be located elsewhere withinmultiplier 210 orRF circuit 100. In other embodiments,step 520 may include usage of an array of comparators to measure the currents. - In
step 530, offset voltages are applied (e.g., by a calibration unit 350) to bodies of transistors (e.g.,transistors step 520. In some embodiments, the amount of offset voltages may be selected insubstep 532 based on the currents measured by an ADC in step 522. For example, greater offset voltages may be selected if the measured currents differ by a significant amount. Alternatively, step 530 may also include not applying offset voltages (in other words, applying the same voltage) if the currents are not different or have negligible differences within permissible tolerances that do not heavily impact the accuracy of the multiplier. For example, in one embodiment, amultiplier 210 is considered to produce an ideal transfer function if the input referred offset voltage for the multiplier is within +/−1 mV of 0V. - As will be described next, in one embodiment,
calibration unit 350 may be configured to generate the offset voltages (e.g., during step 530) by passing a current through a resistor ladder that includes a plurality of resistors coupled together in series.Calibration unit 350 may select various ones of the resistors to select a desired offset voltage. In some embodiments,calibration unit 350 is further configured to change the generated offset voltage of a selected resistor by coupling a resistor in parallel with one of the plurality of resistors in the resistor ladder. - Turning now to
FIG. 6 , one embodiment ofcalibration unit 350 is depicted. In the illustrated embodiment,calibration unit 350 includescurrent sources resistors 620A-F (which are coupled together in series and may collectively be referred to herein as a “resistor ladder”),transistors 630A-F, transistors 640AD, and avoltage reference 650,transistors resistors Calibration unit 350 also includes acontrol unit 670 to manage operation ofunit 350. In some embodiments,calibration unit 350 may include additional resistors 620 and transistors 630. - As discussed above, in various embodiments,
calibration unit 350 is configured to apply offset voltages to the bodies oftransistors calibration unit 350 generates the voltages by passing a current fromcurrent source 610A through resistors 620. The voltages are generated around a common-mode voltage Vcm received fromreference 650.Calibration unit 350 then controls which voltages are selected by switching on or off transistors 630.Calibration unit 350 then routes the selected voltages out tolines calibration unit 350 may select the voltage created by the voltage drop acrossresistor 620A to by activatingtransistor 630A.Calibration unit 350 may then route the voltage to line 354 by activatingtransistor 640B. - In the illustrated embodiment,
calibration unit 350 is configured to further control the selection of offset voltages by usingtransistors resistors calibration unit 350 is able to reduce the voltage drop acrossresistors calibration unit 350 can couple a resistor 662 to change the voltage so that it falls within the desired range (e.g., 32.5 mV). - In one embodiment,
control unit 670 is configured to determine whether offset voltages are needed and to control the selection of offset voltages using transistors 630, 640, and 660. Thus, in some embodiments,control unit 670 may perform (or facilitate performance of)method 500 described above. Accordingly, in some embodiments,control unit 670 is configured to select the appropriate pair of offset voltages based on the difference in the produced currents. In other embodiments, however,control unit 670 may be configured to test multiple pairs of offset voltages until it can determine the best pair based on trial-and-error. In both instances,control unit 670 may need to apply the same pair of offset voltages twice to test both arrangements of the voltages (i.e., the arrangement in which a first voltage and a second voltage are applied respectively totransistors transistors - While
calibration unit 350 may be able to correct a non-ideal transfer function of amultiplier 210, a pair ofmultipliers 210 may still produce different currents relative to one another given the same input. The method described next, in many instances, is able to account for this additional problem. - Turning now to
FIG. 7 , a flow chart of amethod 700 for calibrating output offsets for multipliers is depicted.Method 700 is one embodiment of a method that may be performed by a circuit that includes multipliers (such as power detection unit 120) or circuit coupled to a multiplier such as output offsetunit 250. Likemethod 500,method 700, in some embodiments, may be performed as part of an initial calibration for the circuit (such as during the circuit's startup, during testing of the circuit by automated testing equipment (ATE), etc.). - In
step 710, the same input is provided to a pair of multipliers (e.g., multipliers 210) coupled to a comparator (e.g., comparator 240). As discussed above, in some embodiments, this signal may be a voltage differential signal, and the multipliers may produce currents that vary proportional to the square of the input signal (e.g., Iin 212 and IREF 214, described above). - In
step 720, adjustments are made to the output offset for one of the multipliers (e.g.,multiplier 210B; in other embodiments, adjustments to output offsets for both multipliers may be made) by a full offset value and starting from an initial value. As will be described below in conjunction withFIG. 8 , in various embodiments, output offsetunit 250 may be configured to produce a range of voltages forconverter 230B.Unit 250 may start at the lower part of the range and begin increasing the voltages by a particular amount (i.e., a “full offset value”) causing converter 230 to produce a voltage with an increasing DC offset. For example,unit 250 may causeconverter 230B to increase the DC offset of produced voltages by 1 mV increments until reachingstep 730. - In
step 730, a change in the output of the comparator is detected. Since the multipliers are being provided the same input instep 710, this change in the output at the comparator indicates that the inputs of the comparator are now similar. For example, if the output ofconverter 230A is 99.5 mV for the given input and the output ofconverter 230B is 99 mV, an adjustment instep 720, which causesconverter 230B to produce 100 mV, will produce a change in the output ofcomparator 240—thus, indicating that the inputs are similar. - In
step 740, the multiplier output offset is adjusted back by half an offset value after the change instep 730 is detected. For example, if adjustments of 1 mV are being made instep 720 and the output ofconverter 230B changes from 99 mV to 100 mV, an adjustment back to 99.5 mV would be made in the illustrated embodiment since 0.5 mV is half of 1 mV. In this way,step 740 is able to better compensate for an over adjustment instep 720. In other words, adjusting the output ofconverter 230B back to 99.5 mV is closer to the 99.5 mV output byconverter 230A than the initial 100 mV output at the end ofstep 720. - As will be described below, in various embodiments, output offset
unit 250 is configured to produce voltages forconverter 230B by passing a current through a resistor ladder and selecting various ones of the resistors (such as described with calibration unit 350). In some embodiments, output offsetunit 250 is also configured to change the generated voltage of a selected resistor by coupling a resistor in parallel with one of the resistors in the resistor ladder. - Turning now to
FIG. 8 , one embodiment of output offsetunit 250 is depicted. In the illustrated embodiment, output offsetunit 250 includescurrent sources 810A-C,transistors 820A-D,resistors 830A-E,transistors 840A-C,voltage reference 850,transistor 860, andresistor 862. Output offsetunit 250 also includes acontrol unit 870 to manage operation ofunit 250. In some embodiments, output offsetunit 250 may include additional resistors 830 and transistors 840. - In the illustrated embodiment, output offset
unit 250 generates the offset voltages by passing a current fromcurrent source 810A through resistors 830. The voltages are generated around a common-mode voltage Vcm received fromreference 850. Output offsetunit 250 then controls which voltages are selected and provided toconverter 230B by activating transistors 840. To reduce the number of resistors 830 (which can be substantially large, in some embodiments), output offsetunit 250, in the illustrated embodiment, is configured to use transistors 820 to change the direction of the current flowing through resistors 830. In this way, output offsetunit 250 is able to produce voltages lower than Vcm by causing the current generated bysource 810A to flow fromnode 850 tocurrent source 810C, instead of through resistors 830 tocurrent source 810B. In other embodiments in whichunit 250 does not include transistors 820, however,unit 250 may include additional resistors afternode 850 to produce voltages lower than Vcm. - In the illustrated embodiment, output offset
unit 250 is also configured to coupleresistor 862 in parallel withresistor 830E to reduce the voltage drop acrossresistors 830E (e.g., by a half whenresistors 862 and 820E have the same resistance). Thus, if a particular desired voltage falls between a pair of voltages selectable by using transistors 830 (e.g., between 99 mV and 100 mV such as described above), output offsetunit 250 can coupleresistor 862 to change the voltage so that it falls within the desired range (e.g., 99.5 mV). - In various embodiments,
control unit 870 is configured to determine which output offset to apply and controltransistors 820, 840, and 860, accordingly. As discussed above in conjunction withmethod 700, in one embodiment,control unit 870 is configured to determine the output offset based on whenoutput 242 ofcomparator 240 changes. - Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure.
- The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.
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US20170324385A1 (en) * | 2016-05-06 | 2017-11-09 | Globalfoundries Inc. | Method, apparatus and system for back gate biasing for fd-soi devices |
US9923527B2 (en) * | 2016-05-06 | 2018-03-20 | Globalfoundries Inc. | Method, apparatus and system for back gate biasing for FD-SOI devices |
TWI647777B (en) * | 2016-05-06 | 2019-01-11 | 格羅方德半導體公司 | Method, device and system for back gate bias of FD-SOI device |
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