JP2003163550A - Amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that in order for setting an appropriate bias voltage in an amplifier circuit of the prior arts using a MOS transistor, a complex correction circuit is required on an output side, DC offset cannot be removed enough, and a gain control cannot be executed. <P>SOLUTION: An amplifier with a CMOS inverter comprising a PMOS transistor 2 and an NMOS transistor 3 is provided with a voltage control means to variably control a source potential of the PMOS transistor 2, and a voltage shifting means to raise a source potential of the NMOS transistor in order to remove DC offset. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit, and in particular, it eliminates a DC offset generated due to variations in element characteristics that occur in each manufacturing process of NMOS transistors and PMOS transistors forming a CMOS, and also provides a gain. The present invention relates to an amplifier circuit that can be controlled.

[0002]

2. Description of the Related Art An amplifier circuit using MOS transistors has many advantages in that it has a wide input dynamic range and output dynamic range, a wide operating frequency range, and good operating characteristics even at low power supply voltages. FIG. 6 is a circuit diagram showing an example of a conventional amplifier circuit using MOS transistors. This amplifier circuit is "A CMO
S Transconductance-C Filter technique for Very Hig
h Frequencies "(IEEE Journal of Solid-State Circuit
VOL-27, NO.2, Feb, 1992) described by Nauta's voltage-current converter (hereinafter referred to as VI converter). This amplifier circuit has a high gain characteristic of a CMOS inverter,
It is configured to utilize wide frequency response.

In FIG. 6, 101 is a voltage source, 102 is a grounding portion, 103, 105, 107, 109, 111, 1
Reference numeral 13 denotes PMOS transistors, 104, 106, 108, 110, 112, which form CMOS inverters, respectively.
Reference numeral 114 is an NMOS transistor forming a CMOS, 115 is one input terminal for making a differential input, 1
Reference numeral 16 is the other input terminal for making a differential input, 117 is one output terminal for making a differential output, and 118 is the other output terminal for making a differential output.

Next, the operation will be described. here,
The power supply voltage value of the voltage source 101 is set to Vdd, and Vdd / is respectively applied to the input terminals 115 and 116 so as to maximize the input dynamic range and the output dynamic range.
A bias voltage of 2 is applied and the input terminal 115
It is assumed that a + Vin differential signal and a −Vin differential signal are input to the input terminal 116. The current flowing through the output terminal 117 is Io1 in the direction of the arrow, the current flowing through the output terminal 118 is Io2 in the direction of the arrow, and the PMOS transistor 111.
And a current flowing from the CMOS inverter composed of the NMOS transistor 112 to the output terminal 117 side in the direction of the arrow Io1 ′, the PMOS transistor 109 and the N
The current flowing from the CMOS inverter composed of the MOS transistor 110 to the output terminal 118 side is indicated by the arrow I
o2 '.

The drain current coefficient of the NMOS transistor is Mn, the threshold voltage is Vtn, and PM
When the drain current coefficient of the OS transistor is Mp and the threshold voltage is Vtp, the current Io1 is the drain current flowing through the NMOS transistor 104 and the PMOS transistor 1
Is given as a difference from the drain current flowing through the transistor 03, and the current Io2 is given by the NMOS transistor 1
Drain current flowing through the PMOS transistor 10 and the PMOS transistor 10
It is given as a difference from the drain current flowing through the transistor 5 as shown in the equation (2). Therefore, the difference current Iod between the output current Io1 and the output current Io2 is given as shown in the equation (3).

[Equation 1]

As described above, voltage-current conversion can be performed by using a differential signal as an input and extracting a differential output current. Therefore, the PMOS transistor and NMO
It is known that the element characteristics of the S-transistor vary greatly due to the delicate difference in the manufacturing environment that usually occurs in each manufacturing process (hereinafter, the element characteristics of the MOS transistor that occur in each manufacturing process will be described below). Variation shall be referred to as manufacturing variation). Therefore, even if the bias voltage on the input side is set to Vdd / 2, the bias voltage on the output side deviates from Vdd / 2, and a so-called DC offset occurs.

In the above Nauta VI converter, D
In order to suppress the C offset, the output terminals 117 and 11
Four CMOS inverters are connected on the 8th side and operated so as to subtract the current for the same phase from the output current. Where CM
The in-phase component related to the output voltage of the OS inverter is Voc, the differential component is Vod, and the PMOS transistor 10
7 and NMOS transistor 108
The transconductance related to the inverter is gm3, PMO
S transistor 109 and NMOS transistor 11
0 for a CMOS inverter having a transconductance of gm4, PMOS transistor 111 and NMO
The transconductance relating to the CMOS inverter composed of the S transistor 112 is gm5, the CM composed of the PMOS transistor 113 and the NMOS transistor 114.
Assuming that the transconductance of the OS inverter is gm6, the output current Io1 ′ is given by the equation (4) and the output current Io2 ′ is given by the equation (5).

[Equation 2]

Assuming that the mutual conductances gm between the CMOS inverters are matched, equation (4)
And the coefficient (g
m5-gm6) and the coefficient (gm4-gm3) become zero and the second term disappears, so that only the current in the same phase is V-
It flows into the output side of the I converter to correct the DC offset.

[0009]

Since the conventional amplifying circuit using the MOS transistor is constructed as described above, the bias voltage on the output side where the DC offset is corrected by using four CMOS inverters is not always optimum. However, there is a problem in that the bias voltage fluctuates greatly due to manufacturing variations. Further, although the DC offset can be reduced, the gain does not change substantially based on the characteristics of the circuit element, and there is a problem that the gain control cannot be performed.

The present invention has been made to solve the above problems, and an object thereof is to obtain an amplifier circuit using a MOS transistor capable of removing DC offset and controlling gain.

[0011]

An amplifier circuit according to the present invention includes a CMOS inverter composed of a first PMOS transistor and a first NMOS transistor connected in series, a first PMOS transistor and a first NM.
A voltage control unit that variably controls the source potential of one of the MOS transistors of the OS transistor and a voltage shift unit that changes the source potential of the other MOS transistor so as to remove the DC offset are provided. is there.

In the amplifier circuit according to the present invention, the voltage control means includes a voltage control MOS transistor connected to the source of one of the MOS transistors and a variable voltage source connected to the gate of the voltage control MOS transistor. It is configured to have.

In the amplifier circuit according to the present invention, with respect to the voltage shift means, the voltage shift MOS transistor connected to the source of the other MOS transistor and the gate of the voltage shift MOS transistor by detecting the DC offset are provided. And a DC offset detecting means for applying a voltage adjusted to remove the DC offset.

In the amplifier circuit according to the present invention, with respect to the DC offset detecting means, the above-mentioned first PMOS transistor, first NMOS transistor, and voltage controlling MOS are provided.
A control circuit obtained by connecting in the same order MOS transistors that are identically formed for each of the transistors and the voltage-shifting MOS transistors,
In the control circuit, the inverting input section and the non-inverting input section are connected to the input section and the output section of the CMOS inverter composed of the first PMOS transistor and the first NMOS transistor, respectively, and the output section is provided with two voltage shifting units. It is configured to have an operational amplifier connected to the gate of each MOS transistor, and the variable voltage source is also connected to the gate of the voltage controlling MOS transistor on the comparison circuit side.

In the amplifier circuit according to the present invention, the first load MOS transistor, which is interposed between the output terminal and the voltage source and has the drain and the gate short-circuited, and the output terminal and the ground portion. A second load MOS transistor, which is interposed and has a drain and a gate short-circuited, is provided.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. In the following description, in order to clarify the correspondence relationship between each means configuring the example described in the embodiment of the present invention and each means configuring the invention described in the claims. Further, each means of the invention described in the claims corresponding to each means of the embodiment will be appropriately indicated in parentheses in the description of the embodiment of the present invention.

Embodiment 1. FIG. 1 is a diagram for explaining the operation principle of a CMOS inverter circuit having a DC offset removal function. In FIG. 1, 1 is a voltage source, 2
Is a PMOS transistor (first PMO
S transistor), 3 is an NMOS transistor forming a CMOS (first NMOS transistor), 4 is a ground portion,
Reference numeral 5 is a voltage source interposed between the source of the NMOS transistor 3 and the ground portion 4 to raise the source potential of the NMOS transistor 3 so as to remove the DC offset, 6 is an input terminal, 7 is an output terminal, and 8 is a load resistance. , 9 are voltage sources virtually set so as to apply a bias voltage generated on the output side when performing the AC signal analysis. Here, the power supply voltage value of the voltage source 1 is Vdd, the drain current of the PMOS transistor 2 is Ip, and the NMOS transistor 3 is
Is the drain current of In and the current flowing to the output terminal 7 is I
o, voltage value of voltage source 5 (hereinafter referred to as shift voltage value)
Is Vs and the input bias voltage is Vg. Further, in order to realize the bias setting for obtaining the largest dynamic range, the evaluation relating to the DC offset is performed with Vg = Vdd / 2. The CMOS shown in FIG.
The inverter circuit includes a PMOS transistor 2 and an NM
By connecting the load resistor 8 having an impedance lower than the drain resistance of the OS transistor 3, it operates as a VI converter.

The drain current Ip of the PMOS transistor 2 and the drain current In of the NMOS transistor 3 under the above conditions are given by the equations (6) and (7). As a result, the current Io given as the difference between the drain current Ip of the PMOS transistor 2 and the drain current In of the NMOS transistor 3 is given as shown in equation (8). As is clear from the equation (8), Io = 0 can be set by appropriately adjusting the shift voltage value Vs. At this time, the output voltage Vo matches the input voltage Vg. Here, the shift voltage value Vs that can be set to Io = 0 is calculated from the following equation (9).

[Equation 3]

For example, when the drain current coefficient Mp of the PMOS transistor 2 and the drain current coefficient Mn of the NMOS transistor 3 are equal, Vs = Vtp-Vtn
And the shift voltage value Vs is determined. By the way, since Vs ≧ 0 when operating with a single power source, Vtp ≧
Only when it is Vtn, the DC offset related to the output voltage can be removed. Note that Vtp <V
In the case of tn, instead of the voltage source 5, the PMO
A PMOS is connected between the source of the S transistor 2 and the voltage source 1.
By interposing a voltage shift voltage source for lowering the source potential of the transistor 2, the DC offset can be similarly removed.

When the threshold voltage Vtp of the PMOS transistor 2 and the threshold voltage Vtn of the NMOS transistor 3 are equal to each other, Vtp = Vtn = Vt is set and the shift voltage value Vs is obtained based on the above equation (10). You can By the way, when operating with a single power supply, Vs
Since ≧ 0 and Vg−Vt> 0, Mp
Only when ≦ Mn, the DC offset related to the output voltage can be removed. Note that Mp> Mn
In such a case, the DC offset is similarly removed by inserting a voltage shift voltage source for lowering the source potential of the PMOS transistor 2 between the source of the PMOS transistor 2 and the voltage source 1. Is possible.

The output current Io and the gain Ga of the CMOS inverter circuit can be obtained as follows. By setting Io = 0 in Expression (8), Expression (11) is obtained. Based on equation (11), the PMOS
Transconductance Gmp and NM of transistor 2
The transconductance Gmn of the OS transistor 3 is given as shown in Expression (12) and Expression (13), respectively. Here, the AC signal voltage added to the bias voltage Vg at the input terminal 6 is Vin, and the AC output voltage taken from the output terminal 7 is Vou.
Assuming t, from the equations (12) and (13), the output current Io and the AC output voltage Vout are given as shown in the equations (14) and (15) using the signal voltage Vin. Then, the gain Ga is given as shown in Expression (16). By removing the DC offset in this way, an amplification circuit having a gain determined by the conversion coefficient and load resistance unique to the CMOS inverter is configured. It should be noted that regarding the equations (11) to (16), Vg
It is given as an equation applicable even when ≠ Vdd / 2.

[Equation 4]

Next, an amplifier circuit capable of automatically adjusting the shift voltage value so as to remove the DC offset will be described. FIG. 2 is a circuit diagram showing an example of the configuration of an amplifier circuit having a DC offset removal function. In FIG. 2, the same reference numerals as those in FIG. 1 indicate the same or corresponding portions, and therefore their explanations are omitted. Reference numeral 11 is a bias voltage source for applying a bias voltage to the input terminal 6, 12 is a signal source, 13 is an NMOS transistor (second NMOS transistor) interposed between the source of the NMOS transistor 3 and the ground portion 4, Reference numeral 14 is a bias voltage source (bias voltage applying means) for applying the same bias voltage as the voltage source 11, 15
Is formed in the same manner as the PMOS transistor 2
The transistors (fourth PMOS transistors) 16 are formed in the same manner as the NMOS transistor 3, and the drain is connected to the drain of the PMOS transistor 15 NM.
OS transistor (third NMOS transistor), 1
Reference numeral 7 is an NMOS transistor (fourth NMOS transistor) which is formed in the same manner as the NMOS transistor 13 and has a drain connected to the source of the NMOS transistor 16 and a source connected to the ground portion 4.
The drain of the MOS transistor 15 and the drain of the NMOS transistor 16 are connected to each other, the inverting input portion is connected to the connection portion of the gate of the PMOS transistor 15 and the gate of the NMOS transistor 16, and the output portion is the gate of the NMOS transistor 13. And an operational amplifier connected to the gate of the NMOS transistor 17, 19
Is an NMOS transistor having a function of preventing a latch-up phenomenon that occurs when the power source is activated.

The bias voltage sources 11 and 14 can be realized by various methods such as resistance division of the power source voltage of the voltage source 1. Further, since the above-mentioned amplifier circuit is formed in the same chip and undergoes the same manufacturing process, the PMOS transistor 2 and the PMOS transistor 15, the NMOS transistor 3 and the NMOS transistor 16, the NMOS transistor 13 and the NMOS transistor 17 are used. And can be regarded as having the same device characteristics such as drain current coefficient and threshold voltage. Also, NM
Regarding the OS transistor 19, since the drain-source voltage becomes 0 in the steady operation and the OFF operation is performed, it does not affect the correction operation related to the DC offset at all, and the description of the operation will be omitted hereinafter. .

Next, the operation of the amplifier circuit having the DC offset removing function shown in FIG. 2 will be described. Here, the voltage of the output portion of the CMOS including the PMOS transistor 15 and the NMOS transistor 16 is Vo, and the output voltage of the operational amplifier 18 is Vn. When the output voltage Vo becomes higher than the bias voltage Vg, a voltage obtained by amplifying the voltage difference between the output voltage Vo and the bias voltage Vg is applied to the gate of the NMOS transistor 17. When the gate voltage of the NMOS transistor 17 increases, the drain resistance of the NMOS transistor decreases and the output voltage Vo increases.
Will fall. Therefore, the voltage Vn output from the operational amplifier 18 converges to a voltage value that makes the output voltage Vo and the input voltage Vg equal.

As described above, the PMOS transistor 15 and the PMOS transistor 2, the NMOS transistor 16 and the NMOS transistor 3, and the NMOS transistor 17 and the NMOS transistor 13 can be regarded as having the same element characteristics. Therefore, by applying the output voltage Vn of the operational amplifier 18 to the gate of the NMOS transistor 13, the CMO including the PMOS transistor 2 and the NMOS transistor 3 is applied.
When the input bias voltage related to the S inverter is Vg, the output bias voltage can be set to Vg, and the DC offset can be removed. That is, the PMOS transistor 15, the NMOS transistor 16, the NMOS
A circuit including the transistor 17, the operational amplifier 18, the bias voltage source 14 and the like detects a DC offset amount that appears in a chip in which the amplifier circuit shown in FIG. 2 is generated, and the DC offset amount is detected according to the DC offset amount. By applying the voltage Vn adjusted to be removed to the gate of the NMOS transistor 13 for voltage shift, it is possible to remove the DC offset of the VI conversion amplifier circuit including the PMOS transistor 2 and the NMOS transistor 3. It will be possible.

Next, FIG. 3 is a circuit diagram showing the structure of the amplifier circuit according to the first embodiment of the present invention having a DC offset removing function and a gain varying function. In FIG.
The same reference numerals as those in FIG. 2 indicate the same or corresponding portions, and thus the description thereof will be omitted. Reference numeral 21 denotes a PMOS transistor (second PMOS transistor) interposed between the source of the PNOS transistor 2 and the voltage source 1, and 22 is formed in the same manner as the PMOS transistor 21 to provide the source of the PMOS transistor 15 and the voltage source 1. Is a PMOS transistor (third PMOS transistor) interposed between
A variable voltage source connected to the gate of the MOS transistor 21 and the gate of the PMOS transistor 22.

Since the above amplifier circuit is formed in the same chip and undergoes the same manufacturing process, P
It can be considered that the MOS transistor 21 and the PMOS transistor 22 have the same element characteristics such as the drain current coefficient and the threshold voltage. In the amplifier circuit shown in FIG. 3, the PMOS transistor 21 and the voltage source 23 constitute a voltage control means for variably controlling the source potential of the PMOS transistor 2. Also PM
OS transistor 22, PMOS transistor 15, N
MOS transistor 16 and NMOS transistor 1
The circuit composed of 7 includes a PMOS transistor 21 and a PMO.
S transistor 2, NMOS transistor 3 and NM
It is provided as a reference circuit formed in the same manner as the circuit including the OS transistor 13. Also, PMO
S transistor 22, PMOS transistor 15, NM
From the OS transistor 16, the NMOS transistor 17, the operational amplifier 18, the bias voltage source 14, etc., the source potential of the PMOS transistor 2 is changed by the voltage control means and the PMOS transistor 2 and the NMO.
A DC offset detecting unit is configured to detect a DC offset generated with respect to the bias voltage Vg in the CMOS inverter including the S transistor 3 and apply a voltage adjusted to remove the DC offset to the gate of the NMOS transistor 13. It Further, the NMO is removed from the DC offset detection means and the NMOS transistor 13 so as to remove the DC offset.
A voltage shift means for raising the source potential of the S transistor 3 is configured.

Next, the operation of the amplifier circuit shown in FIG. 3 will be described. Here, the power supply voltage is Vdd, the control voltage applied by the variable voltage source 23 is Vc, the source potentials of the PMOS transistor 2 and the PMOS transistor 15 are Vsp, and the bias applied by the bias voltage source 11 and the bias voltage source 14 is Vsp. The voltage is Vg and the output voltage of the operational amplifier 18 is Vn. As I said, P
MOS transistor 22, PMOS transistor 15,
The circuit including the NMOS transistor 16 and the NMOS transistor 17 includes a PMOS transistor 21 and a PM transistor.
OS transistor 2, NMOS transistor 3 and N
It is provided as a reference circuit formed in the same way as the circuit including the MOS transistor 13, the same control voltage Vc is applied to the gates of the PMOS transistor 21 and the PMOS transistor 22, and the same control voltage Vc is applied to the gates of the NMOS transistor 13 and the NMOS transistor 17. Since the same adjustment voltage Vn is applied, the corresponding MOS transistors have the same operation with respect to the bias voltage Vg. Further, in the following description relating to the circuit operation, in order to facilitate understanding, it is assumed that the element characteristics of the PMOS transistor 21 and the PMOS transistor 2 and the element characteristics of the NMOS transistor 3 and the NMOS transistor 13 are equal to each other. Conduct numerical analysis. In the amplifier circuit according to the present invention, the PMOS transistor 21 and the PMOS transistor 2, and the NMOS transistor 3 and the NMOS transistor
It is not an essential requirement that the transistor 13 and the transistor 13 be formed identically. Even if these transistors are formed differently, it is of course possible to obtain circuit characteristics equivalent to the circuit characteristics specified by the following numerical analysis.

Equation (17) is obtained based on the fact that the drain current in the non-saturation region of the PMOS transistor 21 is equal to the drain current in the saturation region of the PMOS transistor 2, and by rearranging the equation (17), the equation (1) is obtained.
8) is obtained. Then, by solving Expression (18) for Vsp, Vsp is given as shown in Expression (19). As shown in Expression (19), the source potential Vsp of the PMOS transistor 2 and the PMOS transistor 15 is changed by appropriately changing the voltage Vc of the variable voltage source 23.
Can be controlled.

[Equation 5]

Further, as described with respect to the amplifier circuit shown in FIG. 2, by applying the voltage Vn to the gate of the NMOS transistor 13 by the DC offset detecting means, the PMOS transistor 21, the PMOS transistor 2, the NMOS transistor 3 and the NMOS transistor 3 are provided. Since the DC offset related to the VI conversion amplifier circuit including the transistor 13 and the like can be removed, in the equation (14) obtained for the output current Io of the amplifier circuit shown in FIG. If the source potential of the transistor 2 is replaced with Vsp, the output current Io of the VI conversion type amplifier circuit can be obtained as shown in the equation (20). In addition, the gain G of the VI conversion type amplifier circuit
a is given as shown in Expression (21). Formula (21)
As is apparent from the above, it is possible to control the gain Ga of the VI conversion type amplifier circuit by appropriately changing the control voltage Vc.

[Equation 6]

As described above, according to the first embodiment, the voltage control means for variably controlling the source potential of the PMOS transistor 2 and the voltage shift for raising the source potential of the NMOS transistor 3 so as to remove the DC offset. Since the voltage shift means is operated so as to remove the DC offset after appropriately changing the source potential of the PMOS transistor 2, as a result, the V-I conversion type amplifier circuit Since the gain can be controlled, there is an effect that a DC offset can be removed and an amplifier circuit capable of gain control can be obtained. Further, since it is not necessary to add a correction circuit to the output part of the CMOS inverter composed of the PMOS transistor 2 and the NMOS transistor 3, deterioration of frequency characteristics, deterioration of noise performance and increase of current consumption due to parasitic capacitance can be suppressed. It has the effect of being able to.

Further, the voltage control means is a PMOS interposed between the source of the PMOS transistor 2 and the voltage source 1.
Since it is configured to have the transistor 21 and the variable voltage source 23 connected to the gate of the PMOS transistor 21, the source potential of the PMOS transistor 2 can be changed with a simple configuration, and the circuit configuration can be simplified. There is an effect that can be done.

The voltage shift means is an NMO interposed between the source of the NMOS transistor 3 and the ground portion 4.
S transistor 13 and NM by detecting DC offset
The source potential of the NMOS transistor 3 is configured in accordance with the detected DC offset amount, since the configuration includes an offset detection unit that applies a voltage adjusted to remove the DC offset to the gate of the OS transistor 13. Can be raised to an appropriate level, so that the DC offset can be surely removed and an accurate amplifier circuit can be obtained.

Further, in the DC offset detecting means, the gate is connected to the variable voltage source 23 and the PMOS transistor 2
A PMOS transistor 22 formed in the same manner as 1 and P
A PMOS transistor 15 connected to the MOS transistor 22 and formed in the same manner as the PMOS transistor 2;
An NMOS transistor 16 connected to the PMOS transistor 15 and formed in the same manner as the NMOS transistor 3
An NMOS transistor 17 connected to the NMOS transistor 16 and formed in the same manner as the NMOS transistor 13, and a gate of the PMOS transistor 15 and NM.
A voltage source 14 for applying a DC bias voltage to the gate of the OS transistor 16 and an inverting input portion and a non-inverting input portion are connected to an input portion and an output portion of a CMOS composed of a PMOS transistor 15 and an NMOS transistor 16, respectively, and an output portion. Is the NMOS transistor 13
, And the operational amplifier 18 connected to the gate of the NMOS transistor 17, the DC offset detecting means for detecting the DC offset with high accuracy can be realized with a simple structure. This has the effect of simplifying the configuration.

Embodiment 2. FIG. 4 is a circuit diagram showing a configuration of an amplifier circuit according to a second embodiment of the present invention having a DC offset removing function and a gain varying function. Figure 4
2, the same reference numerals as those in FIG. 2 indicate the same or corresponding portions, and thus the description thereof will be omitted. 31 is a PMOS transistor (second PMOS transistor) interposed between the source of the PMOS transistor 2 and the voltage source 1, and 32 is NM
An NMOS transistor (second NMOS transistor) 33, which is interposed between the source of the OS transistor 3 and the ground portion 4, is formed in the same manner as the PMOS transistor 31 and is provided between the source of the PMOS transistor 15 and the voltage source 1. A PMOS transistor (third PMOS)
Transistors 34 are formed in the same manner as the NMOS transistor 32 and are interposed between the source of the NMOS transistor 16 and the ground portion 4 (fourth transistor).
NMOS transistor), 35 is a variable voltage source connected to the gate of the NMOS transistor 32 and the gate of the NMOS transistor 34, and 36 is PM of the non-inverting input section.
The drain of the OS transistor 15 and the drain of the NMOS transistor 16 are connected to each other, the inverting input portion is connected to the connection portion of the gate of the PMOS transistor 15 and the gate of the NMOS transistor 16, and the output portion is the gate of the PMOS transistor 31. And an operational amplifier connected to the gate of the PMOS transistor 33.

Since the above amplifier circuit is formed in the same chip and undergoes the same manufacturing process, P
MOS transistor 31 and PMOS transistor 33,
PMOS transistor 2 and PMOS transistor 15,
NMOS transistor 3 and NMOS transistor 16,
NMOS transistor 32 and NMOS transistor 34
The element characteristics such as the drain current coefficient and the threshold voltage can be considered to be the same. In the amplifier circuit shown in FIG. 4, the NMOS transistor 3
The voltage control means for variably controlling the source potential of the NMOS transistor 3 is constituted by 2 and the voltage source 35. Further, the PMOS transistor 33, the PMOS transistor 15, the NMOS transistor 16 and the NMOS
The circuit including the transistor 34 is provided as a reference circuit formed in the same manner as the circuit including the PMOS transistor 31, the PMOS transistor 2, the NMOS transistor 3, and the NMOS transistor 32. Further, from the PMOS transistor 33, the PMOS transistor 15, the NMOS transistor 16, the NMOS transistor 34, the operational amplifier 36, the bias voltage source 14, etc., the source potential of the NMOS transistor 3 is changed by the voltage control means and the PMOS transistor 2 and D generated for the bias voltage Vg in the CMOS inverter composed of the NMOS transistor 3
A DC offset detecting unit is configured to detect the C offset and apply a voltage adjusted to remove the DC offset to the gate of the PMOS transistor 31. Further, the DC offset detecting means and the PMO
The S-transistor 31 constitutes voltage shift means for lowering the source potential of the PMOS transistor 2 so as to remove the DC offset.

Next, the operation of the amplifier circuit shown in FIG. 4 will be described. Here, the power supply voltage is Vdd, the control voltage provided by the variable voltage source 35 is Vc, the source potentials of the NMOS transistor 3 and the NMOS transistor 16 are Vsn, and the bias provided by the bias voltage source 11 and the bias voltage source 14 is Vsn. The voltage is Vg and the output voltage of the operational amplifier 36 is Vp. As I said, P
MOS transistor 33, PMOS transistor 15,
The circuit including the NMOS transistor 16 and the NMOS transistor 34 includes a PMOS transistor 31 and a PM transistor.
OS transistor 2, NMOS transistor 3 and N
It is provided as a reference circuit formed in the same manner as the circuit including the MOS transistor 32. The same control voltage Vc is applied to the gates of the NMOS transistor 32 and the NMOS transistor 34, and the gates of the PMOS transistor 31 and the PMOS transistor 33 are applied to the gate. Since the same adjustment voltage Vp is applied to the bias voltage Vg,
With respect to, the corresponding MOS transistors perform the same operation. Further, in the following description regarding the circuit operation, in order to facilitate understanding, the element characteristics of the PMOS transistor 31 and the PMOS transistor 2, and the NMOS transistor 3 and the NMOS transistor 3 are described.
Numerical analysis is performed on the assumption that the device characteristics of 2 and 2 are equal to each other. In the amplifier circuit according to the present invention, it is not an essential requirement that the PMOS transistor 31 and the PMOS transistor 2 and the NMOS transistor 3 and the NMOS transistor 32 be formed in the same manner. Even if these transistors are formed differently, it is of course possible to obtain circuit characteristics equivalent to the circuit characteristics specified by the following numerical analysis.

Equation (22) is obtained based on the fact that the drain current in the non-saturation region of the NMOS transistor 32 is equal to the drain current in the saturation region of the NMOS transistor 3, and by rearranging the equation (22), the formula (2) is obtained.
3) is obtained. Then, by solving Expression (23) for Vsn, Vsn is given as shown in Expression (24). As is apparent from the equation (24), by appropriately changing the voltage Vc of the variable voltage source 35, the source potential Vs of the NMOS transistor 3 and the NMOS transistor 16 can be changed.
It becomes possible to control n.

[Equation 7]

Further, in the amplifier circuit shown in FIG. 3, V
By performing the same procedure as that for deriving the output current Io and the gain Ga of the −I conversion type amplifier circuit, the amplifier circuit shown in FIG. 4 also has the following equations (25) and (26). The output current Io and the gain Ga can be obtained. As is clear from the equation (26), the control voltage V
The gain Ga of the VI conversion type amplifier circuit can be controlled by appropriately changing c.

[Equation 8]

As described above, according to the second embodiment, the voltage control means for variably controlling the source potential of the NMOS transistor 3 and the voltage shift for lowering the source potential of the PMOS transistor 2 so as to remove the DC offset. Since the source voltage of the NMOS transistor 3 is appropriately changed and the voltage shift means is operated so as to remove the DC offset, as a result, the V-I conversion type amplifier circuit Since the gain can be controlled, there is an effect that a DC offset can be removed and an amplifier circuit capable of gain control can be obtained. Further, since it is not necessary to add a correction circuit to the output part of the CMOS inverter composed of the PMOS transistor 2 and the NMOS transistor 3, deterioration of frequency characteristics, deterioration of noise performance and increase of current consumption due to parasitic capacitance can be suppressed. It has the effect of being able to.

Further, the voltage control means is an NMOS which is interposed between the source of the NMOS transistor 3 and the ground portion 4.
Since the transistor 32 and the variable voltage source 35 connected to the gate of the NMOS transistor 32 are included in the configuration, the source potential of the NMOS transistor 3 can be changed with a simple configuration, and the circuit configuration is simplified. There is an effect that can be done.

The voltage shift means is a PMO interposed between the source of the PMOS transistor 2 and the voltage source 1.
PM by detecting S-transistor 31 and DC offset
The source potential of the PMOS transistor 2 is configured in accordance with the detected DC offset amount, since it has an offset detection unit that applies a voltage adjusted to remove the DC offset to the gate of the OS transistor 31. Can be reduced to an appropriate level, so that it is possible to reliably remove the DC offset and obtain an amplifier circuit with high accuracy.

Further, the DC offset detecting means is PM
A PMOS transistor 33 formed the same as the OS transistor 31, a PMOS transistor 15 connected to the PMOS transistor 33 and formed the same as the PMOS transistor 2, and an NMOS connected to the PMOS transistor 15 and formed the same as the NMOS transistor 3.
NM connected to the transistor 16 and the NMOS transistor 16 and the gate connected to the variable voltage source 35
An NMOS transistor 34 formed to be the same as the OS transistor 32, a voltage source 14 for applying a DC bias voltage to the gate of the PMOS transistor 15 and the gate of the NMOS transistor 16, and the PMOS transistor 1
An operational amplifier 36 having an inverting input part and a non-inverting input part connected to an input part and an output part of a CMOS composed of an NMOS transistor 5 and an NMOS transistor 16, respectively, and an output part connected to a gate of a PMOS transistor 31 and a gate of a PMOS transistor 33. Since it is configured by including, the DC offset detecting means for detecting the DC offset with high accuracy can be realized with a simple configuration, and the circuit configuration can be simplified.

Embodiment 3. The amplifier circuit according to the third embodiment of the present invention uses a MOS as a load instead of a resistor connected to the output terminal of the amplifier circuit to take out a voltage output.
It differs from the amplifier circuits according to the first and second embodiments in that a transistor is connected to the output terminal. Figure 5
FIG. 9 is a circuit diagram showing a structure of an amplifier circuit according to a third embodiment of the present invention. 5, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions, and thus the description thereof will be omitted. Reference numeral 41 denotes an NMOS transistor (first load MOS transistor) in which the drain and the gate are short-circuited, which is interposed between the voltage source 1 and the output terminal 7, and 42 is the ground portion 4 and the output terminal 7.
N interposed between the drain and the gate and short-circuited
This is a MOS transistor (second load MOS transistor). The DC offset detecting means and the like shown in FIG. 4 are omitted.

Next, the operation of the amplifier circuit shown in FIG. 5 will be described. Here, the NMOS transistors 41 and 4
If the drain current coefficient relating to 2 is Mn ′ and the transconductance is Gmn ′, the NMOS transistors 41 and 4 are
The resistance value Rd related to the load of 2 is given as shown in Expression (27). Then, based on equations (25) and (27), the gain Gb of the amplifier circuit shown in FIG. 5 is given as shown in equation (28). As is clear from the equation (28), the gain of the amplifier circuit is set based on the ratio between the drain current coefficient Mn of the NMOS transistor 3 and the NMOS transistor 32 and the drain current coefficient Mn ′ of the NMOS transistor 41 and the NMOS transistor 42. You can That is, the gain Gb can be appropriately set by changing the ratio of the channel length or the channel width of the NMOS transistors 41 and 42 to the channel length or the channel width of the NMOS transistors 3 and 32.

[Equation 9]

As described above, according to the third embodiment, the NMOS transistor 41 interposed between the output terminal 7 and the voltage source 1 and having the drain and the gate short-circuited, the output terminal 7 and the ground portion. 4 and the NMOS transistor 42 having the drain and the gate short-circuited, the load for extracting the voltage output is M.
Since it can be applied using an OS transistor,
This has the effect of enabling integration and reducing the circuit scale. In addition, the gain of the amplifier circuit is
Since it is possible to set based on the size ratio such as the channel length or channel width of the transistor, the error caused by the gain due to manufacturing variation is reduced compared to the case where the voltage output is taken out by using the resistor. Therefore, there is an effect that the precision of the amplifier circuit can be increased. A PMOS transistor may be used as the load transistor, and the same effect as an NMOS transistor can be obtained.

The amplifier circuits described in the first to third embodiments are not intended to limit the invention of the present application, but are disclosed for the purpose of illustration. The technical scope of the present invention is defined by the description of the claims, and various design modifications can be made within the technical scope described in the claims. For example, although the load MOS transistor is connected to the output terminal 7 of the amplifier circuit shown in FIG. 4 in the third embodiment, the load MOS transistor is connected to the output terminal 7 of the amplifier circuit shown in FIG. It is of course possible to adopt a configuration in which transistors are connected.

[0048]

As described above, according to the present invention, a CMOS inverter including a first PMOS transistor and a first NMOS transistor connected in series,
Voltage control means for variably controlling the source potential of one of the first PMOS transistor and the first NMOS transistor, and voltage shift for changing the source potential of the other MOS transistor so as to remove the DC offset. Since the source potential of one of the MOS transistors is appropriately changed and the voltage shift means is operated so as to remove the DC offset, as a result, the first P transistor is formed.
Since it is possible to control the gain of the amplification circuit provided as the CMOS including the MOS transistor and the first NMOS transistor, it is possible to remove the DC offset and obtain the gain controllable amplification circuit.

According to the present invention, in the voltage control means, the voltage control MOS transistor connected to the source of one of the MOS transistors and the voltage control MOS transistor.
Since it is configured to have a variable voltage source connected to the gate of the transistor, the source potential of one MOS transistor can be changed with a simple configuration, and the circuit configuration can be simplified. It has the effect of being able to.

According to the present invention, in the voltage shift means, the voltage shift MOS transistor connected to the source of the other MOS transistor and the gate of the voltage shift MOS transistor by detecting the DC offset are DC. Since it has the offset detecting means for applying the voltage adjusted so as to remove the offset, the source potential of the other MOS transistor is adjusted to an appropriate level according to the detected DC offset amount. Since it can be changed, it is possible to reliably remove the DC offset and obtain an amplifier circuit with high accuracy.

According to the present invention, the DC offset detecting means includes the first PMOS transistor and the first PMOS transistor described above.
Of the NMOS transistor, the MOS transistor for voltage control, and the MOS transistor for voltage shift, which are formed in the same order, are connected in the same order. PMOS transistor and first NMO
An inverting input section and a non-inverting input section are connected to an input section and an output section of a CMOS composed of S transistors, and an output amplifier is connected to the gates of two MOS transistors for voltage shift. Since the variable voltage source is connected to the gate of the voltage control MOS transistor on the side of the control circuit, the DC offset detecting means for detecting the DC offset with high accuracy is simple. With such a configuration, the circuit configuration can be simplified and the effect can be obtained.

According to the present invention, the first load MOS transistor, which is interposed between the output terminal and the voltage source and whose drain and gate are short-circuited, is interposed between the output terminal and the ground portion. Since the second load MOS transistor in which the drain and the gate are short-circuited is provided, the load for taking out the voltage output can be applied by using the MOS transistor, so that the circuit can be integrated and the circuit can be integrated. The effect is that the scale can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the operating principle of a CMOS inverter circuit having a DC offset removal function.

FIG. 2 is a circuit diagram showing an example of an amplifier circuit having a DC offset removal function.

FIG. 3 is a circuit diagram showing a configuration of an amplifier circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a structure of an amplifier circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of an amplifier circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a conventional amplifier circuit using MOS transistors.

[Explanation of symbols]

1 voltage source, 2 PMOS transistor (first PMO
S transistor), 3 NMOS transistors (first N
MOS transistor), 4 ground, 5 voltage source, 6
Input terminal, 7 output terminal, 8 load resistance, 9 voltage source,
11 bias voltage source, 12 signal source, 13 NMO
S transistor (second NMOS transistor), 14
Bias voltage source (bias voltage applying means), 15
PMOS transistor (fourth PMOS transistor), 16 NMOS transistor (third NMOS transistor), 17 NMOS transistor (fourth N transistor)
MOS transistor), 18, 36 Operational amplifier, 19
NMOS transistor, 21 PMOS transistor (second PMOS transistor), 22 PMOS transistor (third PMOS transistor), 23, 35
Variable voltage source, 31 PMOS transistor (second P
MOS transistor), 32 NMOS transistor (second NMOS transistor), 33 PMOS transistor (third PMOS transistor), 34 NM
OS transistor (fourth NMOS transistor), 4
1 NMOS transistor (first load MOS transistor), 42 NMOS transistor (second load MOS transistor)

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5J091 AA01 AA46 CA13 CA91 CA92                       FA03 HA10 HA17 HA19 HA25                       KA01 KA11 KA12 KA18 MA21                 5J500 AA01 AA46 AC13 AC91 AC92                       AF03 AH10 AH17 AH19 AH25                       AK01 AK11 AK12 AK18 AM21

Claims (10)

[Claims] 1. A first PMOS transistor and the first PMOS transistor.
A first NMOS transistor having a drain connected to the drain of the PMOS transistor of
An input terminal connected to the gate of the S transistor and the gate of the first NMOS transistor, the drain of the first PMOS transistor, and the first NMOS
In an amplifier circuit having an output terminal connected to a connection portion with a drain of a transistor, voltage control means for variably controlling a source potential of the first PMOS transistor, and a DC offset are removed. And a voltage shift means for increasing the source potential of the first NMOS transistor. 2. A second PM, wherein the voltage control means is interposed between the source of the first PMOS transistor and the voltage source.
The amplifier circuit according to claim 1, comprising an OS transistor and a variable voltage source connected to the gate of the second PMOS transistor. 3. The voltage shift means comprises a second N-type transistor interposed between the source of the first NMOS transistor and the ground section.
It is configured to include a MOS transistor and an offset detection unit that detects a DC offset and applies a voltage adjusted to remove the DC offset to the gate of the second NMOS transistor. The amplifier circuit according to claim 1. 4. The second PM, wherein the voltage control means is interposed between the source of the first PMOS transistor and the voltage source.
An OS transistor and a variable voltage source connected to the gate of the second PMOS transistor, and the DC offset detecting means has a source connected to the voltage source and a gate connected to the variable voltage source. The second
PM formed in the same manner as the PMOS transistor of
An OS transistor, a fourth PMOS transistor whose source is connected to the drain of the third PMOS transistor and is formed in the same manner as the first PMOS transistor, and a drain which is connected to the drain of the fourth PMOS transistor. A third NMOS transistor formed to be the same as the second NMOS transistor, and a drain connected to the source of the third NMOS transistor and a source connected to the ground portion and formed to be the same as the second NMOS transistor. No. 4, an NMOS transistor, bias voltage applying means for applying a DC bias voltage to the gate of the fourth PMOS transistor and the gate of the third NMOS transistor, and a non-inverting input section for connecting the drain of the fourth PMOS transistor and the drain of the fourth PMOS transistor. Third
Connected to the drain of the NMOS transistor, the inverting input is connected to the connection between the gate of the fourth PMOS transistor and the gate of the third NMOS transistor, and the output is the second NMOS. 4. The amplifier circuit according to claim 3, comprising an operational amplifier connected to the gate of the transistor and the gate of the fourth NMOS transistor. 5. A first load MOS transistor interposed between an output terminal and a voltage source and having a drain and a gate short-circuited; and a drain and a gate interposed between the output terminal and a ground portion. 2. The amplifier circuit according to claim 1, further comprising a second load MOS transistor shorted between and. 6. A first PMOS transistor and the first PMOS transistor.
A first NMOS transistor having a drain connected to the drain of the PMOS transistor of
An input terminal connected to the gate of the S transistor and the gate of the first NMOS transistor, the drain of the first PMOS transistor, and the first NMOS
In an amplifier circuit having an output terminal connected to a connection portion with a drain of a transistor, voltage control means for variably controlling a source potential of the first NMOS transistor, and a DC offset are removed. And a voltage shift means for lowering the source potential of the first PMOS transistor. 7. The second NM, wherein the voltage control means is interposed between the source of the first NMOS transistor and the ground portion.
7. The amplifier circuit according to claim 6, comprising an OS transistor and a variable voltage source connected to the gate of the second NMOS transistor. 8. A second P-type voltage shift means is interposed between the source of the first PMOS transistor and the voltage source.
It is configured to have a MOS transistor and an offset detection unit that detects a DC offset and applies a voltage adjusted to remove the DC offset to the gate of the second PMOS transistor. The amplifier circuit according to claim 6. 9. The second NM, wherein the voltage control means is interposed between the source of the first NMOS transistor and the ground portion.
An OS transistor and a variable voltage source connected to the gate of the second NMOS transistor are included, and the DC offset detecting means is formed in the same manner as the second PMOS transistor with the source connected to the voltage source. A third PMOS transistor having a source and the source of the third PMOS transistor
A fourth PMOS transistor connected to the drain of the transistor and formed identically to the first PMOS transistor; and a third PMOS transistor connected to the drain of the fourth PMOS transistor and formed identical to the first NMOS transistor. And a drain connected to the source of the third NMOS transistor, a source connected to the ground, a gate connected to the variable voltage source, and a fourth NMOS formed in the same manner as the second NMOS transistor. A transistor and the fourth PMOS
Bias voltage applying means for applying a DC bias voltage to the gate of the transistor and the gate of the third NMOS transistor, and a non-inverting input section for connecting the drain of the fourth PMOS transistor and the drain of the third NMOS transistor. And an inverting input connected to the gate of the fourth PMOS transistor and the third NM.
And an operational amplifier connected to a connection portion with the gate of the OS transistor and having an output portion connected to the gate of the second PMOS transistor and the gate of the third PMOS transistor. The amplifier circuit according to claim 8. 10. A first load MOS transistor interposed between an output terminal and a voltage source and having a drain and a gate short-circuited; and a drain and a gate interposed between the output terminal and a ground portion. 7. The amplifier circuit according to claim 6, further comprising a second load MOS transistor in which and are short-circuited.