TW544894B - Chip carrier with dam bar - Google Patents

Chip carrier with dam bar Download PDF

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Publication number
TW544894B
TW544894B TW091107151A TW91107151A TW544894B TW 544894 B TW544894 B TW 544894B TW 091107151 A TW091107151 A TW 091107151A TW 91107151 A TW91107151 A TW 91107151A TW 544894 B TW544894 B TW 544894B
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Taiwan
Prior art keywords
substrate
opening
wafer
dam structure
area
Prior art date
Application number
TW091107151A
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English (en)
Inventor
Yu-Po Wang
Chung-Chi Lin
Chien-Ping Huang
Original Assignee
Siliconware Precision Industries Co Ltd
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Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW091107151A priority Critical patent/TW544894B/zh
Priority to US10/175,217 priority patent/US6750533B2/en
Application granted granted Critical
Publication of TW544894B publication Critical patent/TW544894B/zh

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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

544894
五、發明說明（i) [發明領域] 本發明係有關一種基板，尤指一種適用於球栅陣 (Bal 1 Gr id Array，BGA)半導體封裝件之基板。 ' [背景技術說明] 球栅陣列（Bal 1 Grid Array，BGA)半導體封裝件之 徵在於採用高密度佈設之銲球作為輸出/輸入端（l/Q 特
Connection)，以使載接於基板上並以銲線（如金線）電， 連接至基板之晶片’得藉銲球而與外界成電性連接關係。 為保遵晶片及知線免於污染或損傷，通常進行—模' (Molding)作業，將承載有晶片及銲線之基板置入模穴、 中，並注入封裝樹脂（Molding C〇mpound)以包覆住晶\ 銲線。如第5A圖所示’自注膠口 1〇注入基板1之封裝樹月匕 (如圖中箭頭所示），其模流流速而造成對銲線丨丨之衝擊曰 力’往往導致銲線1 1偏移（S w e e p)，尤其與模流方向垂 而佈設之銲線11 (如圖中圈選處所示）所受到之模流衝擊田 甚’因而該處銲線11偏移程度亦最大。銲線偏移極可能 致相鄰銲線接觸而產生短路現象，嚴重影響封裝產α b 率。 B t 再者’如第5B圖所示’當基板1應用於多晶片模組 (Multiple Chip Module ’ MCM)之半導體封裝件而承載有 多數晶片1 2以及與各該晶片1 2連接之銲線J j時，晶片工2與 銲線11可能分布不均’因而影響封裝樹脂模流於基板1上' 之流速，該樹腊模流之流速於基板1上較空礦部位會大 於接置有晶片1 2之部位R2 ’與流速較快之模^部份呈垂直
16336.ptd 第6頁 544894 五、發明說明（2) 方向佈設之銲線111(如圖中圈選處所示），遂首當其衝模 流之衝擊，而產生最大銲線偏移程度。此流速不均之情況 亦可能導致亂流而造成封裝樹脂成型後殘留有氣洞 (Void);氣洞之形成則易使封裝產品發生氣爆（Popcorn) 現象，嚴重損害產品品質及良率。 針對銲線偏移問題，已有諸多相關技術揭露解決之方 案’例如美國專利案第6, 031，281、5, 331，205、 6, 21 1，574及 5, 736, 792 號等。
如第6圖所示，美國專利案第6, 031，281號提出於晶片 20角落之銲線區，增設一假銲線（Dummy Wire)21，此假銲 線21與角落銲線22皆連接至一相同導腳23上，且假銲線21 具有與角落銲線2 2相同之線弧高度。當角落銲線2 2受到封 裝樹脂模流之衝擊而產生偏移時，角落銲線2 2觸碰至假銲 線2 1但不會造成短路現象，如此得保全其他部分之銲線24 免於遭受角落銲線22偏移之影響，以緩和樹脂模流對銲線 2 4之衝擊。然而，此種增設假銲線之方法僅能提供對某些 銲線之保護·，且當導腳或銲線佈設密度較高（即相鄰導腳 或柜鄰銲線間距小，Fine Pi tch)時，假銲線之設置則有 實施上之困難，甚難達到保護銲線之功效。
美國專利案第5，331，205號揭露使用二次封膠製程。 如=7圖所不，將晶片30及銲線31先以樹脂材料32如環氧 樹f ί ^覆後，再進行模壓作業以形成包覆整體結構之封 裝膠从3。然而，此法製程複雜，且二次封膠之材料（即 樹脂材料32與封裝膠體33)間易產生脫層（Delaminati〇n)
544894
現象’有損產品品質。 搬= Ϊ8圖所示，美國專利案第6,211，574號係使用一種 〜a曰（如環氧樹脂）以於接近銲線4 1之中段部位形成固 · 定杳H，藉之予以固持銲線41。然而，當敷設該固定部42 - =月曰材料至知線4 1時，易傷及銲線4 1而造成銲線4 1變形 · 或影響其電性連接品質，有損產品良率。 美國專利案第5，7 3 6，7 9 2號則揭露於銲線上敷設環氧 膠黏劑（Ep0Xy Adhesive)，藉之以使銲線固定；此法具有 與上述美國專利案第6,211，574號相同之缺點，即在於可 能損及銲線、影響銲線電性連接之虞。 丨_ 因此，鑒於上述缺失，如何發展出一種得有效解決銲 線偏移問題、避免相鄰銲線發生短路之基板，以維持產品 品質及良率，實為刻不容緩、急待解決之課題。 [發明概述] 本發明之目的在於提供一種具有攔壩結構（Dam Bar) 之基板’使封裝樹脂為攔壩結構所阻擋而改變其模流 (Mold Flow)方向，以有效降低銲線偏移（Sweep)程度，防 止相鄰銲線短路（Short )，並得防止氣洞形成於封裝膠體 中，避免發生氣爆（Popcorn)現象，而維持封裝產品品質 及良率。 為達成上揭及其他目的’本發明揭露一種具有搁壤、社 構之基板，係於其一表面上形成有至少一晶片接置區及二 “ 圍繞該晶片接置區之銲線佈設區’以使接置至該晶片接置 -區之晶片，籍多數形成於該銲線佈設區之銲線而電性連接
544894 五、發明說明（4) 至該基板上，同時，於該基板表面上之晶片接置區及銲線 佈設區外之區域，形成有一注膠口及一攔壩結構，該注膠 口係供封裝膠體之模流注入，以使該晶片與銲線為該封裝 膠體所包覆，而該攔壩結構至少具有一朝該注膠口方向開 設之第一開口 ，以及彼此相對之第二開口與第三開口 ，該 第二開口與第三開口係分別以與該注膠口垂直之方向開 設，以藉該攔壩結構之設置而令該封裝膠體改變其模流方 向。 上述之攔壩結構得改變大部份封裝樹脂之模流方向， 使自注膠口注入之封裝樹脂模流，受到攔壩結構之阻擋， 而轉向以從該攔壩結構之第二開口與第三開口流入晶片接 置區及銲線佈設區内。同時，轉向流入第二開口與第三開 口之封裝樹脂模流方向大致與鄰近該開口之銲線佈設方向 平行，如此得有效降低模流對該處銲線之衝擊力，使銲線 偏移程度減至最小；基此，習知技術之缺點，即於基板上 未設置有攔壩結構時，與由注膠口注入之封裝樹脂模流方 向垂直佈設之銲線（相當於上述鄰近第二與第三開口處之 銲線），會受到之模流衝擊力最大而導致最大之銲線偏移 程度，得獲致極大改善。 再者，流入第二開口與第三開口之封裝樹脂模流，其 流速經攔壩結構之阻擋、轉向後會減慢，如此則進一步降 低模流對銲線造成之衝擊力及銲線偏移程度，因而減少相 鄰銲線間發生短路之機率；且，經由第二開口與第三開口 同時注入晶片接置區及銲線佈設區之封裝樹脂，其模流會
16336.ptd 第9頁 544894 五、發明說明（5) 〜—.〜 - 較為平順’使封裝树脂付較平均分布地勺承 本發明另一實施例之基板，係於其〜復曰曰片與録線。 數晶片接置區及圍繞各該晶片接置區之r f面上形成有多 接置至該晶片接置區之多數晶片，分別^ ^佈設區，以使 一、銲線而電性連接至該甚杯μ 3夕數形成於該銲 線佈設區之銲線而電性連接至該基板上f : ^形成於該銲 表面上之晶片接置區及銲線佈設區外之區^盼，於該基板 一攔壩結構，藉之以使封裝膠體模流得^ ;或、☆开》成有至少 置區及録線佈設區，而令該晶片與銲線 入該晶片接 覆。 /、、、、马該封裝膠體所包 該攔壩結構之設置係使該晶片接置區 攔壩結構得較平均分布於該基板表面上:Y銲線佈設區及 模流亦得較為平順、流速較為平均而流入f ^ ’封裝樹脂 銲線佈設區，以令該晶片與銲線為該封片接置區及 此，習知多晶片模組基板上，由於多數:=二所包覆。基 致封裝樹脂模流產生亂流或流速不均之:布不均，導 樹脂成型後易殘留有氣洞等缺點，得於 明因而使封裝 使用本發明具有攔壩結構之基板，得避:::屏除，故 殘存而引致之氣爆現象，有效確保產品衣f品因氣洞 率。 口口貝，維持產品良 [發明之詳細說明] 以下即配合所附之第丨至4圖詳細說明 具有攔壩結構之基板之實施例，惟該等各圖;^揭露之 不，僅以示意方式顯示與本發明有關之構件單:間化之圖 構件單元並非以實際數量或尺寸比例每，且此些 衣貝|示之基板結
16336.ptd 第10頁 544894 五、發明說明（6) 構佈局應更加複雜。本發明以適用於球柵陣列（B a 1 1 G r i d Array，BGA)半導體封裝件之基板為例釋之，然不以此為 第一實疼例 第1圖係顯示本發明之具有攔壩結構之基板。如圖所 示，首先，製備一適用於球栅陣列半導體封裝件之基板 5 ;該基板5係以習知材質如環氧樹脂（£ ρ 〇 χ y R e S丨n )、聚 亞醯胺（Poly imide)樹脂、BT樹脂或FR4樹脂等構成。
於該基板5之一表面50上界定有至少一晶片接置區51 及一圍繞該晶片接置區5 1之銲線佈設區5 2。該晶片接置區 5 1係供接置半導體晶片5 3，而該銲線佈設區5 2則供形成多 數銲線5 4如金線，以使接置至該晶片接置區5 1之晶片5 3， 得藉該銲線54而電性連接至該基板5上，其中，該銲線54 係用以將形成於該晶片53上之銲·塾（Bond Pad)530，連接 至該銲線佈設區52上所設置之銲指（Bond Finger ) 52 0，而 完成晶片5 3與基板5間之電性連接。
於该基板5表面50上之晶片接置區51及録線佈設區52 外之區域，形成有一注膠口（Gate) 55及一攔壩結構（Dam Bar )56。模壓（Molding)作業進行時，該注膠口 55係供封 裝樹脂（Molding Compound，如圖中箭頭所示）如環氧樹脂 之模流（Mold Flow)注入基板5上，以使該封裝樹脂流入= 片接置區5 1及録線佈設區5 2，而形成用以包覆該晶片& 3與 銲線54之封裝膠體（Encapsulant，未圖示）。 該掘場結構5 6係以一絕緣性（I n s u 1 a t i n g)材質構成
544894 五、發明說明（7) 並得於基板5製造時或模壓作業進行前完成。攔壩結構5 6 與基板5同時完成者，該攔壩結構5 6得以印刷（P r i n t i ng ) 方式印刷於基板5上，故適合用於大量生產；若攔壩結構 5 6於模壓前製成者，該攔壩結構5 6則得以現有設備形成於 基板5上，亦不會增加製造成本。 該攔壩結構5 6係略呈U字形，設置於基板5上之晶片接 置區5 1及銲線佈設區5 2之外圍，並具有適當數目之開口 (Gat e )，藉之以控制封裝樹脂模流之流向，減缓模流對銲 線5 4之衝擊（I m p a c t)，而有效降低銲線5 4偏移（S w e e ρ )程 度，並防止相鄰銲線54發生短路（Short )現象。該攔壩結 構56之型態（Geometry Shape)及高度皆為影響封裝樹脂模 流之重要因素，容下詳述；其中，以印刷方式製成之攔壩 結構5 6得確保較佳之高度穩定性。 攔壩結構之型態 形成於基板5上之攔壩結構5 6，如第1圖所示，其較佳 型態係具有一朝注膠口 5 5方向開設之第一開口 5 6 0，以及 彼此相對之第二開口 5 6 1與第三開口 5 6 2，該第二開口 5 6 1 與第三開口 5 6 2係分別以與該注膠口 5 5垂直之方向開設， 使該攔壩結構5 6以該第一開口 5 6 0、第二開口 5 6 1與第三開 口 5 6 2而分隔成四個部份。 該第一開口 5 6 0之開設尺寸係小於該第二開口 5 6 1與第 三開口 5 6 2之開設尺寸，其中，第一開口 5 6 0之尺寸需小至 足以降低封裝樹脂模流之流速，以使其流入基板5上之晶 片接置區5 1及銲線佈設區5 2，而不會導致封裝樹脂成型後
16336.ptd 第12頁 544894 五、發明說明（8) 殘存有氣洞（Void)於其中；第二開口 561與第三開口 5 62之 尺寸係分別足以使封裝樹脂模流順利流入該晶片接置區5工 及銲線佈設區5 2，而得包覆設置於晶片接置區5 1與銲線佈 設區52之晶片53及鮮線54。 如此構成之攔壩結構5 6，得確實改變大部份封裝樹脂 之模流方向，使自注膠口 55注入之封裝樹脂模流，受到棚 壩結構5 6之阻擋，而轉向以從該攔壩結構5 6之第二開口 5 6 1與苐二開口 5 6 2流入晶片接置區5 1及鲜線佈設區5 2内 (如圖中箭頭所示）。同時，轉向流入第二開口 5 β 1與第三 開口 5 6 2之封裝樹脂模流方向大致與圖中圈選部份之銲線 5 4佈設方向平行，如此得有效降低模流對該處銲線5 4之衝 擊力，使該處銲線5 4之偏移程度減至最小；基此，習知技 術之缺點，即於基板上未設置有攔壩結構時，與由注膠口 注入之封裝樹脂模流方向垂直佈設之銲線（相當於此述第i 圖中圈選部份之銲線54 )，會受到之模流衝擊力最大而導 致最大之銲線偏移程度，得獲致極大改善。 再者，流入第二開口 5 6 1與第三開口 5 6 2之封裝樹脂模 流’其流速經攔壩結構56之阻擋、轉向後會減慢，如此則 進一步降低模流對銲線5 4造成之衝擊力及銲線5 4偏移程 度，因而減少相鄰銲線54間發生短路之機率；且，締由第 二開口 561與第三開口 5 6 2同時注入晶片接置區“及^線 設區52之封裝樹脂，其模流會較為平順，使封裝樹脂得 平均分布地包覆晶片5 3與銲線5 4。 比較實例
544894 五、發明說明（9) 第3A至3C圖係顯示本發明之攔壩結構型態之比較實 例；而第1圖所示之攔壩結構5 6之較佳型態，即係經本發 明人研九並排除該比較實例型態之缺點而完成。 如第3A圖所示，攔壩結構56a係具有一朝注膠口 55方 向開口 5 6 0 a之簡單屏障構造；然經研究發現，此簡單屏障 構造未能達成明顯阻擋封裝樹脂模流之效果。 第3B圖所示之攔壩結構56b與之第3A圖所示者相似， 其不同之處在於增加攔壩結構56b之長度，並使其開口 5 6 0 b尺寸小於攔壩結構5 6 a之開口 5 6 0 a尺寸。研究發現， 此攔壩結構56b得使流入晶片接置區51及銲線佈設區52之 封裝樹脂模流流速減慢，此則助於降低模流對銲線5 4造成 之衝擊力與銲線5 4偏移程度。 第3C圖所示之攔壩結構56c係改良第3B圖所示之攔壩 結構56b，使該攔壩結構56c開設有較多之開口 5 6 3a — e(共 計5個開口）’以期達成使封裝樹脂模流轉向（如圖中箭頭 所示）之功效。然經研究發現，此具有5個開口之攔壩結構 5 6 c無法如期改變封裝樹脂之流動方向。 因此’復加以改良第3 C圖所示之攔壩結構5 6 c，將該 攔壩結構5 6 c之開口 5 6 3 b、5 6 3 c封合，而使開口 $ β 3 ^ 5 6 3e之尺寸擴大’如此則形成第1圖中較佳型態之搁壤妙 構56 ;藉該攔壩結構56之設置，封裝樹脂得如&期改變大^部 份之模流方向，以經由第二開口 561與第三開口 562=入基 板5上之晶片接置區5 1及銲線佈設區5 2，而if # 士 ^ r 咬风有效降低 銲線54偏移程度、防止相鄰銲線54短路、維持扭 \ $对裝產品良
酬 544894 五、發明說明（1 o) 率等功效。 棚壤結構之南度 如第1圖所示，形成於昊说 Η較佳大於用以填充封裝樹月土旨之模之結構56，其高^ 示）高度之四分之三，例如，若dM=ld caV1ty’未圖 w ☆士斑R R夕古洚Η尨入 、八两度為1厘米’則該攔 拗結構56之同度Η係介於！至〇· 75厘 米；如此之攔壩結構5 6遂得提供足豹 9 乂 …、 L如a u % 足夠之阻擋封裝樹脂模 流、防止、干▲ 54偏移等功效。隨攔壩結構56高度η之減 低，焊線54偏移之降低程度亦隨之減低"列如，當攔壩結 構56之局度Η減為〇· 75厘米時，封裝樹脂模流則會逐漸不 受到攔壩結構56之限制；而當攔壩結構56之高度η進一步 減為0_ 5厘米時，攔壩結構56則無法發揮其功用，使封裝 樹脂模流情形與習知基板上未設置攔壩結構時相同。 第二t施例 第4圖係顯示本發明第二實施例之具有攔壩結構之基 板6。如圖所示，該基板6係應用於多晶片模組（Mu 11 i p 1 e Chip Module，MCM)之半導體封裝件；於該基板6之一表面 6 0上形成有多數晶片接置區6 1及圍繞各該晶片接置區6 1之 銲線佈設區6 2，以使接置至該晶片接置區6 1之多數晶片 6 3，分別藉多數形成於該銲線佈設區6 2之銲線6 4而電性連 接至該基板6上。 於該基板6表面6 0上之晶片接置區6 1及銲線佈設區6 2 外之區域，形成有至少一搁壤結構6 5 ;該攔壤結構6 5之形 狀係不以圖示者為限。該攔壩結構6 5之設置係使該晶片接
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16336.ptd 第15頁 544894 五 、發明說明（11) 板 較 佈 區6 1、銲線佈設區62及攔壩結構⑼… '— 6表面60上，如此’封裝樹脂模流亦：較二均分布於該基 為平均（如圖令曲線所示）而流入該晶片HI順、流速 「設區62,以令該晶片63與銲線64為該封 銲線 基此，習知多晶片模組基板上，由於多二斤=。 導致封裝樹脂模流流速不均或產生亂流之現象，， 線偏移、封裝樹脂成型後易殘留有氣洞等缺點，：：= 明中屏除’故使用本發明具有攔壩結構之基板6，得降低X 銲線偏移程度，避免封裝產品因氣洞殘存而引致之氣爆· (Popcorn)現象，有致確保產品品質，維持產品良率民爆 惟以上所述者，僅係用以說明本發明之具體實施例而 ^者Ϊ Ϊ用以限定本發明之可實施範圍，舉凡熟習該項技 J者在未脫離本發明所指示之精神與原理下所完成之= 專政改變或修飾’仍應皆由後述之專利範圍所涵蓋。
16336.ptd 第16頁 544894 圖式簡單言兒明 [圖式簡單說明] 為讓本發明之上述及其他目的、特徵以及優點能更明 顯易懂，將與較佳實施例，並配合所附圖示，詳細說明本 發明之實施例，所附圖示之内容簡述如下： 第1圖係本發明基板之第一實施例之上視圖； 第2圖係第1圖所示之基板沿2- 2線切開之剖視圖； 第3 A至3C圖係本發明基板之攔壩結構之比較實例之上 視圖， 第4圖係本發明基板之第二實施例之上視圖； 第5A及5B圖係習知基板之上視圖； 第6圖係美國專利案第6，0 3 1，2 8 1號所揭露之晶片與銲 線佈設之上視圖， 第7圖係美國專利案第5，3 3 1，2 0 5號所揭露封裝結構之 剖視圖；以及 第8圖係美國專利案第6，2 1 1，5 7 4號所揭露封裝結構之 剖視圖。 [元件符號說明] 1 基板 10 注膠口 11 銲線 12 晶片 Rl、R2 部位 20 晶片 21 假銲線 22 角落銲線 23 導腳 24 銲線 30 晶片 31 銲線
16336.ptd 第17頁 544894
圖式簡單說明 32 樹脂材料 33 封裝膠體 41 5 銲線 基板 42 固定部 50 表面 51 晶片接置區 52 鲜線佈設區 520 銲指 53 晶片 530 銲墊 54 銲線 55 注膠口 56、5 6a、56b、56c 攔壩結構 560 ' 5 60a、56 0b 第 一開口 561 第二開口 562 第三開口 563a - e 開口 Η 高度 6 基板 60 表面 61 晶片接置區 62 銲線佈設區 63 65 晶片 搁壤結構 64 鲜線 16336.ptd 第18頁

Claims (1)

  1. 544894 六、申請專利範圍 1. 一種具有攔 2· 3 4. 少 -^JfU 5又 於 上 佈 注 元 朝 與 而 如 由 之 如 線 如 脂 晶片接 區， 該導 ，同 設區 膠口 件為 該注 開口 該注 令該 申請 以使 電元 時， 外之 係供 該封 膠口 與第 膠口 封裝 專利 環氧樹脂 組群之一 申請專利 申請專利 化合物。 5. 如申請專利 一絕緣性材 6. 如申請專利 印刷方式印 7. 如申請專利 壩結構之基板，係於其一表面上形成有至 置區及一圍繞該晶片接置區之導電元件佈 接置至該晶片接置區之晶片，藉多數形成 件佈設區之導電元件而電性連接至該基板 於該基板表面上之晶片接置區及導電元件 區域，形成有一注膠口及一攔壩結構，該 封裝膠體之模流注入，以使該晶片與導電 裝膠體所包覆，而該攔壩結構至少具有一 方向開設之第一開口，以及彼此相對之第 三開口 ，該第二開口與第三開口係分別以 垂直之方向開設，以藉該攔壩結構之設置 膠體改變其模流方向。 範圍第1項之基板，其中，該基板係以選自 、聚亞醯胺樹脂、BT樹脂及FR4樹脂所組成 者所構成。 範圍第1項之基板，其中，該導電元件係銲 範圍第1項之基板，其中，該封裝膠體係樹 範圍第1項之基板，其中，該攔壩結構係以 質構成。 範圍第1項之基板，其中，該攔壩結構係以 刷於該基板上而完成。 範圍第1項之基板，其中，該攔壩結構係略 16336.ptd 第19頁 544894 六、申請專利範圍 呈ϋ字形，並以該第一開口 、第二開口與第三開口而分 隔成四個部份。 8. 如申請專利範圍第1項之基板，其中，該攔壩結構之高 度係大於用以填充該封裝膠體之模穴高度之四分之三 〇 9. 如申請專利範圍第1項之基板，其中，該第一開口之開 設尺寸係小於該第二開口與第三開口之開設尺寸。 10. 如申請專利範圍第9項之基板，其中，該第一開口之尺 寸係小至足以降低該封裝膠體模流之流速，以使其流 入該晶片接置區及導電元件佈設區’而不會導致氣洞 形成於該封裝膠體中。 11. 如申請專利範圍第9項之基板，其中，該第二開口與第 三開口之尺寸係分別足以使該封裝膠體模流流入該晶 片接置區及導電元件佈設區。 12. —種具有搁壤結構之基板，係於其一表面上形成有多 數晶片接置區及圍繞各該晶片接置區之導電元件佈設 區，以使接置至該晶片接置區之多數晶片，分別藉多 數形成於該導電元件佈設區之導電元件而電性連接至 該基板上，同時，於該基板表面上之晶片接置區及導 電元件佈設區外之區域，形成有至少一攔壩結構，藉 之以使封裝膠體模流得平順流入該晶片接置區及導電 元件佈設區，而令該晶片與導電元件為該封裝膠體所 包覆。 1 3.如申請專利範圍第1 2項之基板，其中，該導電元件係
    16336.ptd 第20頁 544894 六、申請專利範圍 銲鎳。 14.如申請專利範圍第12項之基板，其中，該攔壩結構係 以一絕緣性材質構成。 1 5.如申請專利範圍第1 2項之基板，其中，該攔壩結構係 以印刷方式印刷於該基板上而完成。 16. 如申請專利範圍第12項之基板，其中，該攔壩結構之 設置係使該晶片接置區、導電元件佈設區及攔壩結構 得平均分布於該基板表面上。 17. 如申請專利範圍第12項之基板，其中，該封裝膠體係 樹脂化合物。
    16336.ptd 第21頁
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI604537B (zh) * 2016-09-30 2017-11-01 南亞科技股份有限公司 半導體封裝體及其製造方法
CN111223823A (zh) * 2018-11-23 2020-06-02 三星电子株式会社 半导体芯片和半导体封装件
TWI736802B (zh) * 2018-10-23 2021-08-21 矽品精密工業股份有限公司 電子封裝件

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100555495B1 (ko) * 2003-02-08 2006-03-03 삼성전자주식회사 칩 어레이 몰딩용 몰드 다이, 그것을 포함하는 몰딩 장치및 칩 어레이 몰딩 방법
US7612444B2 (en) * 2007-01-05 2009-11-03 Stats Chippac, Inc. Semiconductor package with flow controller
US8035205B2 (en) * 2007-01-05 2011-10-11 Stats Chippac, Inc. Molding compound flow controller
JP4438006B2 (ja) * 2007-03-30 2010-03-24 Ｏｋｉセミコンダクタ株式会社 半導体装置及び半導体装置の製造方法
US8450841B2 (en) * 2011-08-01 2013-05-28 Freescale Semiconductor, Inc. Bonded wire semiconductor device
JP2017526977A (ja) * 2014-05-16 2017-09-14 ヘプタゴン・マイクロ・オプティクス・プライベート・リミテッドＨｅｐｔａｇｏｎ Ｍｉｃｒｏ Ｏｐｔｉｃｓ Ｐｔｅ． Ｌｔｄ． 装置の、特に光学装置のウェーハレベル製造

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331205A (en) 1992-02-21 1994-07-19 Motorola, Inc. Molded plastic package with wire protection
US5436203A (en) * 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
JP2590747B2 (ja) * 1994-07-29 1997-03-12 日本電気株式会社 半導体装置の製造方法
JP2844316B2 (ja) * 1994-10-28 1999-01-06 株式会社日立製作所 半導体装置およびその実装構造
JP2663897B2 (ja) * 1995-01-26 1997-10-15 日本電気株式会社 リードフレームおよびその製造方法
US5736792A (en) 1995-08-30 1998-04-07 Texas Instruments Incorporated Method of protecting bond wires during molding and handling
JP3032964B2 (ja) * 1996-12-30 2000-04-17 アナムインダストリアル株式会社 ボールグリッドアレイ半導体のパッケージ及び製造方法
US6117705A (en) * 1997-04-18 2000-09-12 Amkor Technology, Inc. Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate
KR100265461B1 (ko) 1997-11-21 2000-09-15 윤종용 더미본딩와이어를포함하는반도체집적회로소자
JP3819574B2 (ja) * 1997-12-25 2006-09-13 三洋電機株式会社 半導体装置の製造方法
JP4161399B2 (ja) * 1998-03-12 2008-10-08 沖電気工業株式会社 半導体装置用樹脂基板及び半導体装置
JPH11354689A (ja) * 1998-06-04 1999-12-24 Oki Electric Ind Co Ltd フレーム状基板とその製造方法及び半導体装置の製造方法
US6211574B1 (en) 1999-04-16 2001-04-03 Advanced Semiconductor Engineering Inc. Semiconductor package with wire protection and method therefor
US6048656A (en) * 1999-05-11 2000-04-11 Micron Technology, Inc. Void-free underfill of surface mounted chips
KR200309906Y1 (ko) * 1999-06-30 2003-04-14 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조용 리드프레임
US6225685B1 (en) * 2000-04-05 2001-05-01 Advanced Micro Devices, Inc. Lead frame design for reduced wire sweep having a defined gap between tie bars and lead pins
US6303978B1 (en) * 2000-07-27 2001-10-16 Motorola, Inc. Optical semiconductor component and method of manufacture
JP2002093831A (ja) * 2000-09-14 2002-03-29 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI604537B (zh) * 2016-09-30 2017-11-01 南亞科技股份有限公司 半導體封裝體及其製造方法
TWI736802B (zh) * 2018-10-23 2021-08-21 矽品精密工業股份有限公司 電子封裝件
CN111223823A (zh) * 2018-11-23 2020-06-02 三星电子株式会社 半导体芯片和半导体封装件
CN111223823B (zh) * 2018-11-23 2023-11-21 三星电子株式会社 半导体芯片和半导体封装件

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