TW533519B - Semiconductor device and method for producing the same - Google Patents

Semiconductor device and method for producing the same Download PDF

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Publication number
TW533519B
TW533519B TW089103776A TW89103776A TW533519B TW 533519 B TW533519 B TW 533519B TW 089103776 A TW089103776 A TW 089103776A TW 89103776 A TW89103776 A TW 89103776A TW 533519 B TW533519 B TW 533519B
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Taiwan
Prior art keywords
conductive metal
layer
metal layer
electrode
coating layer
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Application number
TW089103776A
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English (en)
Chinese (zh)
Inventor
Eiji Watanabe
Kouichi Murata
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Fujitsu Ltd
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Publication of TW533519B publication Critical patent/TW533519B/zh

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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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TW089103776A 1999-04-13 2000-03-03 Semiconductor device and method for producing the same TW533519B (en)

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JP2003188313A (ja) * 2001-12-20 2003-07-04 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6762503B2 (en) * 2002-08-29 2004-07-13 Micron Technology, Inc. Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same
US6995475B2 (en) * 2003-09-18 2006-02-07 International Business Machines Corporation I/C chip suitable for wire bonding
US20050167837A1 (en) * 2004-01-21 2005-08-04 International Business Machines Corporation Device with area array pads for test probing
US7910471B2 (en) * 2004-02-02 2011-03-22 Texas Instruments Incorporated Bumpless wafer scale device and board assembly
JP3981089B2 (ja) * 2004-02-18 2007-09-26 株式会社東芝 半導体装置とその製造方法
TWI278946B (en) * 2004-07-23 2007-04-11 Advanced Semiconductor Eng Structure and formation method for conductive bump
US20060087039A1 (en) * 2004-10-22 2006-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Ubm structure for improving reliability and performance
US7416980B2 (en) * 2005-03-11 2008-08-26 Intel Corporation Forming a barrier layer in interconnect joints and structures formed thereby
KR100762354B1 (ko) * 2006-09-11 2007-10-12 주식회사 네패스 플립칩 반도체 패키지 및 그 제조방법
JP5101169B2 (ja) 2007-05-30 2012-12-19 新光電気工業株式会社 配線基板とその製造方法
KR101120285B1 (ko) * 2007-07-30 2012-03-07 엔엑스피 비 브이 스트레스 완충 반도체 부품 및 그의 제조 방법
US8349721B2 (en) * 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
JP5350022B2 (ja) * 2009-03-04 2013-11-27 パナソニック株式会社 半導体装置、及び該半導体装置を備えた実装体
US8847387B2 (en) * 2009-10-29 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Robust joint structure for flip-chip bonding
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
KR101187977B1 (ko) * 2009-12-08 2012-10-05 삼성전기주식회사 패키지 기판 및 그의 제조방법
US9159652B2 (en) * 2013-02-25 2015-10-13 Stmicroelectronics S.R.L. Electronic device comprising at least a chip enclosed in a package and a corresponding assembly process
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US6614113B2 (en) 2003-09-02

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