TW501233B - Dual damascene process utilizing a low-k dual dielectric - Google Patents

Dual damascene process utilizing a low-k dual dielectric Download PDF

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Publication number
TW501233B
TW501233B TW090115158A TW90115158A TW501233B TW 501233 B TW501233 B TW 501233B TW 090115158 A TW090115158 A TW 090115158A TW 90115158 A TW90115158 A TW 90115158A TW 501233 B TW501233 B TW 501233B
Authority
TW
Taiwan
Prior art keywords
mask
layer
insulating layer
dielectric
etched
Prior art date
Application number
TW090115158A
Other languages
English (en)
Chinese (zh)
Inventor
Michael Stetter
Erdem Kaltalioglu
Andy Cowley
Original Assignee
Infineon Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Corp filed Critical Infineon Technologies Corp
Application granted granted Critical
Publication of TW501233B publication Critical patent/TW501233B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/0888—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures wherein via-level dielectrics are compositionally different than trench-level dielectrics

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW090115158A 2000-06-21 2001-06-21 Dual damascene process utilizing a low-k dual dielectric TW501233B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US59878000A 2000-06-21 2000-06-21

Publications (1)

Publication Number Publication Date
TW501233B true TW501233B (en) 2002-09-01

Family

ID=24396884

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090115158A TW501233B (en) 2000-06-21 2001-06-21 Dual damascene process utilizing a low-k dual dielectric

Country Status (3)

Country Link
EP (1) EP1292978A2 (de)
TW (1) TW501233B (de)
WO (1) WO2001099184A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030064582A1 (en) * 2001-09-28 2003-04-03 Oladeji Isaiah O. Mask layer and interconnect structure for dual damascene semiconductor manufacturing
GB2394879B (en) 2002-11-04 2005-11-23 Electrolux Outdoor Prod Ltd Trimmer
US9577023B2 (en) 2013-06-04 2017-02-21 Globalfoundries Inc. Metal wires of a stacked inductor
US12334398B2 (en) 2021-08-23 2025-06-17 International Business Machines Corporation Multilayer dielectric stack for damascene top-via integration

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5821169A (en) * 1996-08-05 1998-10-13 Sharp Microelectronics Technology,Inc. Hard mask method for transferring a multi-level photoresist pattern
US6197696B1 (en) * 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
JP2001156170A (ja) * 1999-11-30 2001-06-08 Sony Corp 多層配線の製造方法

Also Published As

Publication number Publication date
WO2001099184A3 (en) 2002-06-27
WO2001099184A2 (en) 2001-12-27
EP1292978A2 (de) 2003-03-19

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