Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
  • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
  • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
  • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
  • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
  • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
  • H10W20/48—Insulating materials thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
  • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
  • H10W20/0888—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures wherein via-level dielectrics are compositionally different than trench-level dielectrics

Definitions

• This invention relates to integrated circuits manufactured using multiple levels of conductive interconnection which make use of dielectric (or insulating) materials fabricated to provide a low value of dielectric constant, and more particularly, to structures fabricated using a dual damascene process to fabricate the multilevel interconnection .
• the first factor the resistivity of the material forming the metal conductors, has been addressed by a change from the predominant use of aluminum to the use of copper for the conductor material .
• the second factor, the dielectric constant of the insulating layers in the structure, has been addressed by the increasing use of insulting materials with a lower dielectric constant (or low-k materials or dielectrics) than the commonly used silicon dioxide or silicon nitride.
• Two general approaches to the use of lower dielectric constant materials are presently in evaluation or limited use in commercially available products.
• One of these is the use of organic materials to replace the inorganic silicon oxide or silicon nitride.
• the second approach is the use of inorganic materials containing voids or bubbles.
• the available methods for etching via openings through the dielectric materials make use of some specific properties of the commonly used silicon oxide dielectric to achieve the required control of the via etching process.
• the by-products resulting from commonly used silicon oxide etching processes deposit on sidewalls of etched portions of vias, and passivate sidewalls thereof and protect them from additional etching.
• these passivating by-products can be removed using a simple ashing process, wherein the passivating material is oxidized to a powdery substance and can then be removed in a cleaning operation.
• the present invention is directed to an integrated circuit structure, and a method for fabricating an integrated circuit structure using a dual damascene metallization process, which allows for the use of conventional silicon dioxide dielectric material in the regions of the structure where the superior mechanical and chemical properties of the silicon dioxide can be used advantageously, and which allows for the use of low-k dielectric materials in the regions of the structure where the lower dielectric constant can be advantageously used to provide circuits which operate at higher speeds, and where the poorer mechanical properties of the low-k dielectric material do not cause a degradation in the mechanical properties or reliability of the integrated circuit .
• conventional silicon oxide dielectric is used in the vicinity of the via structures which interconnect different levels of metallization, and where the structure may be subjected to high mechanical stress such as the regions of the bonding pads.
• the low-k dielectric material is used in the remaining regions of the integrated circuit where the low dielectric constant results in reduced capacitance between conductors and ground and between individual conductors, with a resulting reduction in coupling between conductors.
• a damascene process sequence is a method used to define a level of conductive interconnect wherein the conductive metal lines are defined not by patterning and etching the metal conductor, but rather by defining trenches in an insulating layer, and a metal conductor is then deposited into these trenches.
• the width of the metal conductor is determined by the width of the trenches which have been defined in the dielectric material .
• via holes are patterned in the interior regions of the previously defined trenches . These via holes are then etched through to the underlying interconnect layers or circuit elements. The via holes and trenches are then filled with the interconnect metal .
• the present invention is directed to a method for fabricating an integrated circuit using a dual damascene process to form an interconnect level over a top surface of a semiconductor body in which an insulator underlying a metal conductor of the interconnect level and extending laterally beyond the conductor is of a first dielectric material having a first dielectric constant, and an insulator lying to the sides of the metal conductor is of a second dielectric material having a second dielectric constant which is different than the first dielectric constant.
• the method comprises the steps of: depositing over a semiconductor body, upon which it is desired to form an interconnect level, a first insulating layer of the first dielectric material, and further depositing a second insulating layer of the second dielectric material over the first insulating layer; depositing over the second insulating layer of second dielectric material a first masking layer of a first masking material, and a second masking layer of a second masking material, where the first and second masking materials are chosen so as to be mutually selective to each other in their etching characteristics, such that at least one etchant which etches the first masking material will not etch the second masking material, and at least one etchant which etches the second masking material will not etch the first masking material; defining and etching in the second masking layer an opening which will ultimately define the location and features of a metal conductor, etching said second masking material with an etchant which will not etch said first masking material; defining and etching in the first
• FIG. 1 shows a sectional view of an integrated circuit structure fabricated using the methods of the present invention.
• FIGS. 2-7 show the integrated circuit structure at various points throughout the fabrication process.
• FIG. 1 shows a schematic sectional view of an integrated circuit structure 10 in accordance with an exemplary embodiment of the present invention.
• the structure 10 comprises a semiconductor body 12 having a top surface 13. Transistors and other devices (not shown) fabricated in and/or on semiconductor body 12 would be connected to elements of an interconnect structure using conventional techniques.
• An insulating layer 14 having a top surface 15 is formed on the top surface 13 of semiconductor body 12.
• a conductor 16 having a top surface 17 and an insulating layer 18 having a top surface 19 are formed on the top surface 15 of the insulating layer 14.
• layer 16 selectively can pass through layer 14 and contact portions of body 12 and/or diffusions (not shown) therein. Insulating layer 18 is capped with a hard mask layer 20 having a top surface 21.
• Conductor 16, insulating layer 18, and hard mask 20 could be formed using conventional metal etching processes, a conventional damascene process, a conventional dual damascene process, or by using the novel process of the present invention which is discussed below.
• the conductor 16 and hard mask 20 are covered by cap layer 22 having a top surface 23.
• a conductor 36 comprising portions 36a and 36aa, has portion 36aa in contact with conductor 16 and portion 36a.
• a dashed line 36aaa delineates between the two portions 36a and 36aa of conductor 36.
• Conductor portion 36a serves as an interconnection between various parts of the integrated circuit.
• Conductor portion 36a has a top surface 36t, a bottom surface 36b, and side surfaces 36c.
• Conductor portion 36aa has side surfaces 36s.
• An insulating layer 24 has a top surface 25 and surrounds conductor portion 36aa and lies underneath a bottom surface 36b of conductor portion 36a, extending out to cover a top surface 23 of cap layer 22.
• An insulating layer 26 has a top surface 27 and lies adjacent to side surfaces 36c of conductor portion 36a.
• a cap layer 28 has a top surface 29 and covers the top surface 27 of insulating layer 26.
• FIG. 2 shows a sectional view of the integrated circuit structure 10 at an early stage of fabrication. Fabrication has progressed to the point in the process sequence where a first level of metal conductor 16 having a top surface 17 has been defined on a top surface 15 of an insulating layer 14 which has been fabricated on a top surface 13 of a semiconductor body 12. Transistors which have been fabricated in the semiconductor body 12 are not shown, but would be connected to elements of the interconnect structure using conventional techniques.
• the conductor 16 is surrounded by dielectric material 18 having a top surface 19, which is capped by a hard mask layer 20 having a top surface 21.
• Conductor 16, insulating layer 18, and hard mask 20 could be formed using conventional metal etching processes, a conventional damascene process, a conventional dual damascene process, or by using the novel process of the present invention.
• the metal 16 and hard mask 20 are covered by a cap layer 22 having a top surface 23.
• the insulating layers 14 and 18 might consist of a conventional dielectric such as silicon dioxide, a low-k dielectric material, or a composite dielectric composed of conventional and low-k dielectric material, as are described herein
• FIG. 3 shows the integrated circuit structure 10 after the first steps in the process to fabricate a second conductor layer using a dual damascene process and using a combination of conventional and low-k dielectric materials.
• the steps which have been completed include the deposition of a conventional silicon oxide insulating layer 24 having a top surface 25, the deposition of a low dielectric constant (low- k) insulating layer 26 having a top surface 27, and the deposition of a dual hard mask layer consisting of layers 28 and 30 having top surfaces 29 and 31, respectively.
• Layer 28 forms a cap layer for the low-k dielectric layer 26 and consists of a material, such as silicon nitride, which is compatible with the underlying low-k dielectric material of layer 26.
• Layer 30 forms a hard mask layer on top of layer 28, and typically would be a metallic material such as tungsten.
• the major requirement on the two layers 28 and 30 is that they be mutually selective to each other in their etching characteristics, that is, etchants which etch the material of layer 30 do not etch the material of layer 28 at any significant rate, and etchants which etch the material of layer 28 do not etch the material of layer 30 at any significant rate.
• FIG. 4 shows the integrated circuit structure 10 after an opening 32 has been defined and etched in the hard mask layer 30.
• the opening 32 will subsequently be filled with metal conductor to form the conductor 36a shown in FIG. 1.
• the etchant used to etch the material of layer 30 has not etched any significant amount of the material of layer 28, and the etch process has stopped at or near the top surface 29 of layer 28.
• Conventional photolithographic techniques are used to define an opening in a photoresist material (not shown) , and the photoresist material has subsequently been removed after the completion of the etch process.
• FIG. 5 shows the integrated circuit structure 10 after an opening 34 has been defined and etched, using a suitable etchant material, through the cap layer 28 and down through the low-k insulating layer 26, stopping at the top surface 25 of the conventional insulating layer 24.
• the area below opening 34 is to be a via which will be filled with metal.
• Conventional photolithographic techniques are used to define an opening in a photoresist material (not shown) , the photoresist material is used to define the opening etched in the cap layer 28, and the photoresist material has subsequently been removed after the completion of the etch processes.
• the etchant used to etch the low-k insulating layer 26 is chosen to be selective so as not to etch the material of cap layer 28 nor conventional insulating layer 24.
• FIG. 6 shows the integrated circuit structure 10 after an etch process has been completed to extend the depth of the opening 34 through the conventional insulating layer 24 down to the top surface 23 of the cap layer 22.
• the extended opening 34 is identified as 34a.
• the etchant is chosen so as to selectively etch the material of insulating layer 24 and also to etch the material of cap layer 28 so as to extend the opening 32 down to the top surface 27 of low-k insulating layer 26, while not etching the material of the cap layer 22 or the low-k insulating layer 26, to result in an opening 32a.
• FIG. 7 shows the integrated circuit structure 10 after an etch process has been completed to extend opening 32a through the low-k insulating layer 26 down to the top surface 25 of conventional insulating layer 24 to form opening 32aa. An additional etch is performed to remove the cap layer 22 at the bottom of the opening 34a to result in opening 34aa. The top surface 17 of the metal layer 16 is exposed at the bottom of extended opening 34aa.
• FIG. 1 shows the integrated circuit structure 10 after the structure of FIG. 7 has been subjected to a conventional dual damascene process consisting of a standard metal liner fill, deposition of a seed layer, and metal plating, followed by a chemical mechanical polishing (CMP) to planarize the surface of the integrated circuit structure 10.
• CMP chemical mechanical polishing
• the hard mask layer 30 is removed by the CMP process.
• the structure illustrates the opening 34aa filled with metal to form the conductor 36aa, and the opening 32aa filled with metal to form the conductor 36a.
• the dielectric portion of the region of the integrated circuit structure 10 in the vicinity of via 34aa, filled with metal 36aa and lying between metal conductor 16 and metal conductor 36a, is composed of conventional dielectric material 24.
• the portion of the integrated circuit 10 to either side 36c of metal conductor 36aa is composed of the low-k dielectric material 26.
• various materials and classes of materials may be substituted for the materials specified in the various masking and insulating layers.
• the method may be applied to fabricating similar structures in various devices and circuits fabricated using semiconducting materials other than silicon, and may also be applied to the fabrication of passive interconnection structures such as printed wiring boards, flexible interconnection circuits, and integrated circuit package structures.

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• 2001
  • 2001-06-21 EP EP01946640A patent/EP1292978A2/de not_active Withdrawn
  • 2001-06-21 WO PCT/US2001/019881 patent/WO2001099184A2/en not_active Ceased
  • 2001-06-21 TW TW090115158A patent/TW501233B/zh active

Non-Patent Citations (1)

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