TW499760B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW499760B
TW499760B TW089117271A TW89117271A TW499760B TW 499760 B TW499760 B TW 499760B TW 089117271 A TW089117271 A TW 089117271A TW 89117271 A TW89117271 A TW 89117271A TW 499760 B TW499760 B TW 499760B
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Taiwan
Prior art keywords
external terminal
semiconductor device
patent application
switching element
item
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TW089117271A
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English (en)
Inventor
Takao Emoto
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Toshiba Corp
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Publication of TW499760B publication Critical patent/TW499760B/zh

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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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經濟部智慧財產局員工消費合作社印製 499760 A7 ___B7 _ 五、發明說明(1 ) 【發明所屬之技術領域】 本發明係有關一種半導體裝置之封裝構造,特別是使 用:在MOSFET、1GBT等高輸入的阻抗元件。 〔習知之技術〕 比較小型之電力用半導體裝置(〜1 0 0A、 〜3 0 0 W ),一般而言,具有利用樹脂加以密封半導體 晶片之封裝構造。 例如,功率Μ 0 S F E T的封裝構造,乃如第1 〇圖 及第1 1圖所示。在半導體晶片1 ,形成MOSFET ( 電力用開關元件),其背面爲Μ 0 S F Ε Τ的汲極。半導 體晶片1的背面,是利用焊接或導電性樹脂,固定在框架 散熱部2 - 1。 框架散熱部2 - 1具有得以使半導體晶片1所發生熱 能,釋放到封裝體外部的功能之同時,也具有作爲 Μ〇S F Ε Τ之汲極的外部端子(D )的功能。 半導體晶片1的主表面,形成MO S F Ε Τ之源電極 5及閘電極6。源電極5是利用鍵接線3 a ,被連接在 MOSFET之源極的外部端子(S) 2 — 2。閘電極6 是利用銲接線3 b,被連接在Μ〇S F Ε T之閘極的外部 端子(G ) 2 — 3。銲接線3 a ,3 b例如由鋁、金等金 屬材料構成之。 半導體晶片1及其周邊部,除了 Μ 0 S F Ε T之汲極 、源極、閘極之各外部端子的一部外,均用樹脂4予以覆 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -----------^----------------- (請先閱讀背面之注意事項再填寫本頁) - 4- 第89117271號專利申請案 中文說明書修正頁A?民國91年1月修正
五、發明説明(2) 和〇Ν — 0 F F移 經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 499760 科斗抖一. 蓋之。 再者’關於外部端子(D,S,G )的位置,可做種 種改變。例如,於第1 0圖及第1 1圖中,閘極之外部端 t ( G )的位置與源極之外部端子(s )的位置,可反過 來設計,也可在閫極之外部端子(G )與源極之外部端子 (S )之間,配置汲極之外部端子(d ),以使各端子排 成一列。 現在大電力半導體裝置主要用途是作爲D C 一 D C電 腦、馬達控制電路、電源電路等開關元件,其構造則以高 輸入阻抗的Μ 0 S型作爲主流。此乃基於應用μ 0 S型大 電力半導體裝置的驅動電路,比應用雙極型大電力半導體 裝置的驅動電路小型化等理由。 大亀力半導體裝置(開關元件)的輸出效率,主要是 以〇Ν狀態的損失、和(1 〇 s s 行時(開關動作時)的損失來決定的。因而,習知之目的 在於,縮小〇Ν電阻,或是提高開關速度(使高頻動作特 性提高),進行大電力半導體裝置的開發。 亦即,功率Μ 0 S F Ε Τ的特性與使用條件,在這數 年中大幅的提升。例如關於Ο Ν電阻,乃比數年前的 M〇SFET,更縮小了l/10〜l/15,而有關動 作頻率,則由原來的50kHz,提高到l〇〇kHz。 但是,若動作頻率提高到接近1 〇 〇 kH z或1 0 〇 k Η z以上’反而會重新產生如上述之Μ〇S F Ε T特性 改善的效果達到頂點的問題。此係在於阻抗爲1 / ζ = 1 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公楚) (請先閱讀背面之注意事項再填寫本頁) 一裝· 、1Τ -Φ -5- 經濟部智慧財產局員工消費合作社印製 499760 A7 ___B7 _ 五、發明説明(3) / r + 1 / 2 r f L、z = 2 τ f L的關係,認爲會增加 MOSFET的導通電阻成份。 而隨著電子零件之基板實裝,轉移到要求機器、裝置 小型化與降低成本的所謂面實裝,且進行零件形狀之薄型 化、小型化。例如,半導體I C所應用的封裝之D I P ( Dual Inline Package) 、PGA (Pin Grid Array),正逐 漸改成 SOP (SmallOutline Package) 、BGA (Ball Grid Array)。而連有關個別半導體用封裝,也正逐漸以面 實裝型的封裝作爲主流。 .但是,對應習知面實裝的個別半導體封裝,其主要不 但要切斷既存的針腳插入型的封裝針腳多餘部及外部端子 (針腳),還無法充分滿足機器、裝置之小型化和降低成 本的要求。 〔發明欲解決之課題〕 此種於習知之MOSFET、 IGBT等高輸入阻抗 元件中,若動作頻率接近l〇〇kHz,或爲1〇〇 k Η z以上,就會有元件特性之提升達到頂點的缺點。而 就此種元件的封裝而言,適合面實裝的薄型、小型之封裝 的開發也略感不足。 本發明係爲解決上述缺點之發明,其目的在於,針對 高輸入阻抗元件之封裝體提供一就算其動作頻率接近 1 0 0 k Η ζ ’或爲1 〇 〇 k Η ζ以上,元件之特性(例 如開關速度)的提升也不會達到頂點,也適合面實裝之封 i紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公^ ~ -6- I ; 裝 Ί 訂 . (請先閲讀背面之注意事項再填寫本頁) 499760 A 7 _____ B7 五、發明説明(4) 裝體。 (請先閱讀背面之注意事項再填寫本頁) 〔用以解決課題之手段〕 爲達成上述目的,本發明之半導體裝置係具備有:形 成開關元件之半導體晶片、和覆蓋前述半導體晶片之封裝 體、和被連接在前述開關元件的控制電極之第1外部端子 、和被連接在前述開關元件的第1電極之第2外部端子、 和被連接在前述開關元件的第2電極之第3及第4外部端 子;對前述第1外部端子與前述第3外部端子之間施加輸 入電壓’且對前述第2外部端子與前述第4外部端子之間 流入輸出電流。 前述第1外部端子與前述第3外部端子,乃爲互相?接 .而被配置之。前述第1外部端子與前述第3外部端子,則 被配置在前述封裝體的同一面內。 前述開關元件係爲高輸入阻抗元件。前述開關元件具 有1 0 0 W以上的容許損失,且以1 〇 〇 k Η z以上的動 作頻率,執行動作。 經濟部智慧財產局員工消費合作社印製 前述開關元件爲Μ〇S F Ε Τ,前述第2電極則爲前 述MOS F ΕΤ之源電極。前述第1至第4外部端子,其 表面一部分實際上是與前述封裝體表面一致。 〔發明之實施形態〕 以下,邊參照圖面,邊針對本發明之半導體裝置做一 詳細說明。 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 經濟部智慧財產局員工消費合作社印製 499760 A7 B7__ 五、發明說明(5 ) 第1圖係表示有關本發明之第1實施形態之半導體裝 置。而第2圖係表示第1圖之半導體裝置之斷面圖。 t •本例乃針對大電力面實裝型Μ〇SF E T元件做一說 明。 在半導體晶片1形成縱型之MOSFET (電力用開 關元件),其背面爲MOSFET之汲極。半導體晶片1 之背面,是利用焊接或導電性樹脂,被固定在框架散熱部 2 - 1。框架散熱部2 - 1則具有得以使半導體晶片1所 發生的熱能,釋放到封裝體外部的功能之同時,也是作爲 Μ 0 S F E T之汲極的外部端子(D )之功能。 在半導體晶片1的主表面,形成MO S F Ε Τ之源電 極5及閘電極6。源電極5利用銲接線3 a,被連接在 MOSFET之源極的外部端子(S1) 2 — 2 — 1之同 時,利用銲接線3 c被連接在Μ 0 S F Ε T之源極的外部 端子(S 2 ) 2 - 2 — 2。閘電極6則利用銲接線3 b, 被連接在MOSFET之閘極的外部端子(G) 2 — 3。 M〇S FET之源極的外部端子2 — 2 — 1的功能是 作爲取出輸出電流的輸出端子,外部端子2 - 2 - 2的功 能則是與外部端子2 - 3 —同作爲施加輸入電壓的輸入端 子。 銲接線3 a ,3 b例如是由鋁(A L )、金(A u ) 等金屬材料構成的。半導體晶片1及其周邊部,則除了 Μ 0 S F Ε T之汲極、源極、閘極的各外部端子之一部份 外,均用樹脂4予以覆蓋之。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) - ----I I I I I i^wi i I I I I I I ^-------1 (請先閱讀背面之注意事項再填寫本頁) -8- 499760 A7 , ΒΊ 補充 五、發明説明(6) 上述之半導體裝置的特徴在於,MO S F E T之源極 的外部端子,存有兩個。然後,外部端子(S 1 ) 2 - 2 (請先閲讀背面之注意事項再填寫本頁) - 1的功能是作爲取出輸出電流的輸出端子,外部端子( S 2 ) 2 - 2 - 2的功能則是與外部端子2 — 3 —同作爲 施加輸入電壓的輸入端子。 外部端子2 - 2 - 1是種用來取出輸出電流的端子, 故其大小要儘可能的.大,連繫源電極5與外部端子2 - 2 - 1的銲接線3 a之數量也要很多。 而從Μ〇S F E T的源極至外部端子2 — 2 — 1之間 ,存在著因半導體晶片1之內部配線或銲接線3 a所引起 •的電阻成份和感應係數成份(第5圖之Z i )。 因而,能以縮短半導體晶片1的內部配線,或是增加 銲接線3a的數量,而儘可能的減少從Μ〇S F E T之源極 至外部端子2 - 2 — 1之間的電阻成份和感應係數成份。 另一方面,外部端子2 - 2 - 2是種與外部端子2 - 可小於外 與外部端 經濟部智慧財產局員工消費合作社印製 3 —同作爲施加輸入電壓V G S的端子,其大小 部端子2 - 2 - 1 ,並且也可減少連繋源電極5 子2 — 2 - 2的銲接線3 c之數量。 總之,外部端子2 — 2 - 2,2 — 3,是爲 了施加輸 入電壓V G S的端子,因此特別是從MO S F Ε Τ之源極 到外部端子2 - 2 - 2之間的電阻成份和感應係數成份是 沒問題。 可藉由具備此種的構成,達成提升元件特性(例如開 關速度)。此效果,明顯的產生在具有1 0 0 W以上之容 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐〉 -9- 499760 A7 ___B7_ 五、發明説明(7) (請先閱讀背面之注意事項再填寫本頁) 許損失P D的裝置’或是以接近1 〇 〇 kH z或1 〇 〇 k Η z以上的動作頻率,執行動作的裝置。再者,針對有 關開關速度等之具體效果,於後面做一詳述。 而上述之半導體裝置係採用面實裝型之封裝體。而 Μ〇S F Ε Τ之源極的外部端子(輸入端子)2 — 2 - 2 與閘極的外部端子(輸入端子)2 - 3 ,是互相鄰接而配 置的,因此很容易就完成實裝基板側的配線設計。結果可 達到機器、裝置、系統之小型化和降低成本等。 再者,於第1圖中,可將閘極之外部端子2 - 3的位 置與源#之外部端子2 — 2 - 1 ,2 - 2 - 2的位置反過 來。但源極的外部端子2 - 2 - .2與閘極之外部端子2 -3,卻要成互相鄰接的方式做配置。 第3圖係表示有關本發明之第2實施形態之半導體裝 置。而第4圖係表示第3圖之半導體裝置的斷面圖。 本例亦針對大電力面實裝型Μ 0 S F Ε Τ元件做一說 明。 經濟部智慧財產局員工消費合作社印製 本例之半導體裝置的特徵在於具備設有考慮到對模組 裝置等的實裝利便性之形狀的觀點。總之,閫極之外部端 子2 — 3及源極的兩個外部端子2 — 2 - 1 ,2 — 2 - 2 ,是分別被配置在封裝體其中一面,汲極之外部端子2 — 1則被配置在封裝體的另一面。 以下,針對本例之半導體裝置的構成做一具體說明。 在半導體晶片1形成縱型之Μ〇S F Ε Τ (電力用開 關元件),其背面係爲Μ 0 S F Ε Τ之汲極。半導體晶片 本紙張尺度適用中周國家標準(CNS ) Α4規格(210X297公釐) 499760 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(8 ) 1的背面,是利用焊接和導電性樹脂,被固定在框架散熱 部2 — 1。框架散熱部2 - 1則具有得以使半導體晶片1 所發生的熱能,釋放到封裝體外部的功能之同時,也是作 爲Μ〇S F E T之汲極的外部端子(D )之功能。 •在半導體晶片1的主表面,形成MO S F ΕΤ之源電 極5及閘電極6。源電極5是被連接在MOSFET之源 極的外部端子(S1) 2 - 2 — 1之同時,會被連接在 Μ〇S F Ε Τ之源極的外部端子(S 2 ) 2 — 2 — 2。閘 電極6則被連接在MO S F Ε Τ之閘極的外部端子(G ) 2 - 3。 Μ 0 S F Ε Τ之源極的外部端子2 - 2 - 1的功能是 作爲取出輸出電流的輸出端子,外部端子2 - 2 - 2的功 能則是與外部端子2 - 3 —同作爲施加輸入電壓的輸入端 子。 半導體晶片1及其周邊部,則除了 Μ〇S F Ε 丁之汲 極、源極、閘極的各外部端子之一部份外,均用樹脂4予 以覆蓋之。 就連上述之半導體裝置中,MOSFET之源極的外 部端子,也存有兩個。然後,外部端子(S1) 2 - 2 -1的功能是作爲取出輸出電流的輸出端子,外部端子( S 2 ) 2 — 2 — 2的功能則是與外部端子2 — 3 —同作爲 施加輸入電壓的輸入端子。 外部端子(S 1 ) 2 - 2 - 1是種用來取出輸出電流 的端子,故其大小要儘可能的大,且連繫源電極5與外部 (請先閱讀背面之注意事項再填寫本頁) T裝 ------ 訂-----
n n n I 參 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -11 - 499760 經濟部智慧財產局員工消f合作社印製 a7 户##正 _ B7 I 9LU_ 充—五、發明説明(9) 端子2 — 2 - 1的接點很多。 而從Μ 0 S F. E T的源極至外部端子2 - 2 - 1之間 ,存在著因半導體晶片1之內部配線等所引起的電阻成份 和感應係數成份(第5圖之Z i )。 . 因而,能以縮短半導體晶片1的?部配線等,而儘可能 的減少從Μ〇S F E T之源極至外部端子2 - 2 — 1之間 的電阻成份和感應係數成份。 另一方面,外部端子(S 2 ) 2 - 2 - 2是種與外部 端子2 - 3 —同作爲施加輸入電壓V G S的端子,其大小 可小於外部端子2 - 2 - 1,並且也可減少源電極5與外 部端子2 — 2 — 2的接點。 總之,外部端子2 — 2 — 2,2 - 3,是爲了施加輸 入電壓V G S的端子,因此特別是從Μ〇S F Τ之源極 到外部端子2 - 2 - 2之間的電阻成份和感應係數成份是 沒問題的。 可藉由具備此種的構成,達成提升元件特性(例如開 關速度)。此效果,明顯的產生在具有1 0 0 W以上之容 許損失P D的裝置,或是以接近1 〇 〇 k Η ζ或1 0 0 k Η ζ以上的動作頻率,執行動作的裝置。 而上述之半導體裝置係採用易針對模組裝置等之實裝 的封裝體。而Μ 0 S F Ε Τ之源極的外部端子2 - 2 — 2 與閘極的外部端子2 - 3 ,是在封裝的同一面內,予以互 相鄰接而配置的,因此很容易就完成模組裝置側的配線設 計。結果可達到系統之小型化和降低成本等。 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X297公釐) (請先閱讀背面之注意事項存填寫本頁) 装· 訂 -1#^ -12- 499760 A7 五、發明説明(怊 接著,針對在採用第1圖至弟4圖之半導體裝置的情 形下之效果,做一詳細說明。 (請先閲讀背面之注意事項再填寫本頁) 第5圖係表示第1圖至第4圖之半導體裝置之等値電 路苍。 V G S係爲聞極端子(外部_子)G與源極端子(外 部端子)S 2之間的電壓,V D S係爲汲極端子(外部端 子)D與源極端子(外部端子)s 1之間的電壓,I D爲 汲極電流。 第6圖係表示針對習知品級(3端子品級)測量〇n 波形的結果,第7圖係表示針對本發明品級(4端子品級 )測量Ο N波形的結果。 該些圖係有關汲極電流I D的前沿,並表示本發明品 級比習知品級更高速。總之,按照本發明品級,由〇F F 換向成〇 N的開關速度就變得很高速。 而第8圖係表示針對習知品級(3端子品級)測量 0 F F波形的結果,第9圖係表示針對本發明品級(4端 子品級)測量〇F F波形的結果。 經濟部智慧財產局員工消費合作社印製 該些圖係有關汲極電流I D的後沿,並表示本發明品 級比習知品級更局速。總之,按照本發明品級,由〇N換 向〇F F的開關速度就變得很高速。 如此一來只要按照本發明品級,〇N、〇F F就能同 時完成高速開關動作。而有關開關損失,則於表1 ,表示 比較本發明品級與習知品級的結果。總之,本發明品的開 關ί貝失比習知品級小5 0 %以上。 本紙張尺度適用中國國家標準(CNS〉Α4規格(210Χ297公羡) —--- -13- 499760 Α7 Β7 五、發明說明(11 ) 〔表1〕 開關損失(槪略) Ps w 100kHz 200kHz 3端子品級 37.9 β J 3.79w 7.58w 4端子品級 17.0 β J 1.70 w 3.40w 氺 Psw=Pon + Pof f Ρ ο η : Ο N時的損失 Po f f : OFF時旳的損失 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 而本發明的汲極電流I D,並不會受到V G S的影響 。總之,習知由於源極的外部端子爲一個,故該源極的外 部端子,乃作爲與閘極之外部端子一同施加輸入電壓 V G S的端子,且功能爲取出輸出電流(汲極電流)的端 子。因此,汲極電流I D會大受VG S之影響。另一方面 ,本發明的源極之外部端子爲兩個,其中一方係爲輸入端 子,另一方則爲輸出端子的功能,即可減少汲極電流I D 受V G S的影響,還能減低雜音。 再者,本發明係採用面實裝型的封裝體。例如在如上 述之案例所示的Μ 0 S F E T之情況下,源極端子S 1 , S 2與印刷基板的控制器面積,大幅增加的關係,可減少 大電流發生時的外部端子的發熱。而由於封裝體被薄型化 、小型化,故可達到系統之小型化、低成本化。
· 1 I I I I 1 I 訂· I I I I I 墨 秦 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -14- 499760 A7 __ ___Β7________ 五、發明說明(12 ) 〔發明之效果〕 (請先閱讀背面之注意事項再填寫本頁) 以上,如說明般,若按本發明,有關於高輸入阻抗元 件:的封裝構造,例如Μ Ο S _電晶體的源極之外部電極爲兩 個的關係,就可達成提升元件特性(例如開關速度)。此 效果會明顯的產生在容許損失PD爲1 〇 〇W以上的裝置 (例如縱型MOSFET)、和動作頻率接近1〇〇 kHz或l〇〇kHZ以上的裝置。而若按本發明,就能 藉由採行面實裝型的封裝體,對封裝體提出薄型化、小型 化的貢獻。 〔圖面之簡單說明〕 第1圖係表示有關本發明之第1實施形態之半導體裝 置圖。 第2圖係表示第1圖之半導體裝置之斷面_。 第3圖係表示有關本發明之第2實施形態之半導體裝 置圖。 第4圖係表示第3圖之半導體裝置之斷面圖。 經濟部智慧財產局員工消費合作社印製 第5圖係表示本發明之半導體裝置之等値電路圖。 第6圖係表不習知品級(3端子品級)之〇n波形圖 0 罘7圖係表不本發明品級(4端子品級)之〇n波形 圖。 第8圖係表不習知品級(3端子品級)之〇jr jr波形 圖。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -15- 499760 A7B7 波 F F ο 之 級 品 子 端 4 /V 級 品 明 發 本 ) 示 13表 {係 明圖 說 9 J第 發 圖 形 圖 面 斷 之 。 置 圖裝 置體 裝導 體半 導之 半圖 之 ο 知 1 習第 示示 表表 係係 圖 圖 ο 1一 IX IX 第第 極 源 κί\ 子 端 部 外 } : } 線 極 2 極接 汲 I 閘銲 ( 2 ( : 子 I 子 C 片端 2 端 3 晶部 ,部, 1 體外 i 外 b 明導:一 :3 說半 1 2 3 , 之 : I I I a : · · 號 1222345 符 6 極極 脂電電 樹源閘 (請先閱讀背面之注意事項再填寫本頁) 裳----——訂 —----- BI. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -16-

Claims (1)

  1. 499760 Α8 Β8 C8 D8 々、申請專利範圍 第89 1 1727 1號專利申請案 中文申請專利範圍修正本& i 1 ^ (請先閎讀背面之注意事項再填寫本頁) 民國90年.1月修正 1 · 一種半導體裝置,其特徵爲:具備有,形成開關 元件之半導體晶片、和覆蓋前述半導體晶片之封裝體、和 被連接在前述開關元件的控制電極之第1外部端子、和被 連接在前述開關元件的第1電極之第2外部端子、和被連 接在前述開關元件的第2電極之第3及第4外部端子;對 前述第1外部端子與前述第3外部端子之間施加輸入電壓 ,且對前述第2外部端子與前述第4外部端子之間流入輸 出電流。 2 .如申請專利範圍第1項所述之半導體裝置,其前 述第1外部端子與前述第3外部端子,是互相鄰接而配置· 的。 經濟部智慧財產局員工消費合作社印製 3 .如申請專利範圍第1項所述之半導體裝置,其前 述第1外部端子與前述第3外部端子,是被配置在前述封 裝體的同一面內。 4 .如申請專利範圍第1項所述之半導體裝置,其前 述開關元件爲高輸入阻抗元件。 5 .如申請專利範圍第1項所述之半導體裝置,其前 述開關元件係具有1 0 0 W以上的容許損失。. 6 .如申請專利範圍第1項所述之半導體裝置,其前 述開關元件是以1 0 0 k Η z以上的動作頻率’執行動作 本紙張尺度適用中國國家標準( CNS ) Α4規格(210X297公釐) 一 499760 A8 B8 C8 D8 七、申請專利範圍 〇 7 .如申請專利範圍第1項所述之半導體裝置,其前 述開關元件係爲Μ 0 S F E T,前述第2電極係爲前述 Μ〇S F Ε Τ的源電極。 8 .如申請專利範圍第1項所述之半導體裝置,其前 述第1至第4外部端子,其表面一部分實際上是與前述封 裝體表面一致。 ---Ik 2----裝—I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製
    本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -2-
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JP4115882B2 (ja) * 2003-05-14 2008-07-09 株式会社ルネサステクノロジ 半導体装置
JP4248953B2 (ja) 2003-06-30 2009-04-02 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP5165214B2 (ja) * 2006-06-26 2013-03-21 オンセミコンダクター・トレーディング・リミテッド 半導体装置
JP4769784B2 (ja) * 2007-11-05 2011-09-07 ルネサスエレクトロニクス株式会社 半導体装置
US8253225B2 (en) 2008-02-22 2012-08-28 Infineon Technologies Ag Device including semiconductor chip and leads coupled to the semiconductor chip and manufacturing thereof
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US8853835B2 (en) 2012-10-05 2014-10-07 Infineon Technologies Ag Chip arrangements, a chip package and a method for manufacturing a chip arrangement
US9754854B2 (en) * 2012-10-11 2017-09-05 Infineon Technologies Ag Semiconductor device having sensing functionality
JP2013141035A (ja) * 2013-04-19 2013-07-18 Renesas Electronics Corp 半導体装置
JP2015019115A (ja) * 2014-10-28 2015-01-29 ルネサスエレクトロニクス株式会社 半導体装置
JP2016040839A (ja) * 2015-10-27 2016-03-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6817777B2 (ja) * 2015-12-16 2021-01-20 ローム株式会社 半導体装置
WO2018043039A1 (ja) 2016-08-31 2018-03-08 パナソニックIpマネジメント株式会社 スイッチング回路
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