TW477004B - Method to prevent dopant diffusion in dual-gate - Google Patents

Method to prevent dopant diffusion in dual-gate Download PDF

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Publication number
TW477004B
TW477004B TW087116873A TW87116873A TW477004B TW 477004 B TW477004 B TW 477004B TW 087116873 A TW087116873 A TW 087116873A TW 87116873 A TW87116873 A TW 87116873A TW 477004 B TW477004 B TW 477004B
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TW087116873A
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Dung-Shing Li
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United Microelectronics Corp
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Priority to TW087116873A priority Critical patent/TW477004B/zh
Priority to US09/206,187 priority patent/US6060361A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

477004 3796tvvf.doc/008
)M 經濟部中央標準局員工消費合作社印製 五、發明説响（I ) 本發明是有關於一種半導體元件之製造方法，且特別 是有關於一種防止雙閘極中之摻質擴散之方法。 混合式元件例如將邏輯元件置於dram中已受到相 當之重視’爲了要達到低電壓之操作，需要形成具有雙閘 極之CMOS。在製作雙閘極時，自行對準矽化程序被廣泛 使用’以降低閘極與擴散層之電阻，並連接n+型多晶矽閘 極與p+型多晶矽閘極。但是以金屬矽化物接合之DRAM 難以維持良好的更新（Refresh)特性，因此對於嵌入式 DRAM需要具有多晶砂化金屬（p〇iyCide)之雙閘極。但是， 摻雜在n+型與p+型多晶矽中之摻質（Dopants)會相互擴 散’造成臨限電壓之飄移，因此在多晶矽層與矽化金屬層 之間再形成一層阻障層（Barrier Layer)，以抑制摻質之擴 散。 第1A圖至第1C圖是習知技藝的一種形成雙閘極之 方法剖面流程圖。 首先，請參照第1A圖，提供一基底10，在其中形成 相鄰的井14及隔離結構12。然後，以熱氧化法在基底10 上形成閘氧化層16。接著，再利用化學氣相沈積法（CVD) 於閘氧化層16上形成多晶矽層18。 請參照第1B圖，之後在多晶矽層18上形成阻障層20， 其形成之方法可先以化學氣相沉積法在多晶矽層18上形 成含矽較多之矽化鎢（WSix)層，然後再以濺鍍法在矽化鎢 層上沉積氮化鎢（WNx)層或是氮化鈦（TiNx)所組成之阻障 層20。 請 先 閱 讀- 背' 意 事 項 再 r 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 477004 3 796twf.doc/008 B? 五、發明説明（夂） 請參照第1C圖，接著在阻障層20上形成導電層22， 其形成之方法是使用化學氣相沉積法沉積一層含鎢較多之 石夕化鎢層’或是以濺鍍法或化學氣相沉積法沉積一層金屬 鶴。 後續之製程則包括定義p型閘極與η型閘極，以及在 基底形成源極/汲極區，以完成雙閘極電晶體之製作。 雖然氮化鎢層與氮化鈦層可阻擋硼離子之擴散，但氮 化鎢層與氮化鈦層是以濺鍍法形成，而多晶矽層與矽化鎢 層則是以化學氣相沉積法形成，因此在整個雙閘極製程須 在不同之機台中進行，故會增加晶片更換機台之時間，使 產能無法擴大。 因此本發明的目的就是在提供一種防止雙閘極中之摻 質擴散之方法，經由氮氣或氨氣之電漿處理，使矽化鎢層 轉變成氮矽化鎢，其具有較佳的防止摻質擴散之功能。而 閘極除閘氧化層外，其它各層皆以化學沉積法形成，可在 同一機台完成閘極之製造。 經濟部中央標準局員工消費合作社印製 根據本發明之上述目的，提出一種防止雙閘極中之摻 質擴散之方法，其步驟包括··提供一半導體基底，在其中 先後形成井與隔離結構。之後於井上形成閘極氧化層。然 後於閘極氧化層上形成多晶矽層，接著在多晶矽層形成第 一導電層，進行氮氣或氨氣電紫處理步驟，形成阻障層。 然後在氮矽化金屬層上形成第二導電層。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 4 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） ~ 477004 經濟部中央標準局員工消費合作社印製 3 796t\vf.doc/008 五、發明説明（$ ) 細說明如下： 圖式之簡單說明： 第1A圖至第1C圖是習知技藝的一種防止雙閘極中 之摻質擴散之方法剖面流程圖。 第2A圖至第2D圖是本發明一較佳實施例的一種防 止雙閘極中之摻質擴散之方法剖面流程圖。 圖式之標記說明： 10、60 :基底 12、62 :隔離結構 14 、 64 :井 16、66 :閘氧化層 18、68:多晶砂層 1〇、70 ··第一導電層 20、71 :阻障層 22、72 :第二導電層 實施例 第2A圖至第2E圖是本發明一較佳實施例的一種防止 雙閘極中之摻質擴散之方法剖面流程圖。 請參照第2A圖，首先在基底60形成隔離結構62， 然後在基底60中型成井64。接著在基底60上形成閘氧化 層66,其形成之方法係以熱氧化法，形成約100埃之厚度。 接下來，在閘氧化層66上形成多晶矽層68，其形成之方 法例如是以低壓化學沉積法進行。 請參照第2B圖，在多晶矽層68上形成第一導電層70， (請先閱讀背面之注意事項再填寫本頁)
本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公簸） 477004 3796twf.doc/008 經濟部中央標準局員工消費合作社印製 Λ7 Η 7 五、發明説明（γ) 其材質較佳的是含砂較多的（Silicon-rich)砂化鎢，而其形 成之方式是以例如低壓化學氣相沉積法，使用六氟化鎢與 矽甲烷爲反應氣體，操作溫度約爲300至40(TC，壓力約 爲0.3至1.0 Torr，沉積的厚度約爲100埃。 請參照第2C圖，進行電漿處理步驟，以例如氮氣或 氨氣爲電漿氣體，使第一導電層70之矽化鎢反應轉變成 氮矽化鎢，以作爲阻障層Ή，且此氮矽化鎢之晶相爲非結 晶（Amorphous)。電漿處理所使用的操作壓力約爲2 mTorr，功率約爲300至500W左右。 請參照第2D圖，在阻障層71上形成第二導電層72， 其材質例如是含鎢較多之矽化鎢層，以降低電阻而其形成 之方式是以例如低壓化學氣相沉積法。 後續之製程則包括定義p型閘極與η型閘極，以及在 基底形成源極/汲極區，以完成雙閘極電晶體之製作。 由上述本發明較佳實施例可知，應用本發明具有下列 優點： 1·整個行程閘極的製程都是在同一機台進行，免除晶 片在不同機台轉移之時間，非常適合大量生產。 2·經由電漿處理而形成之氮矽化鎢，其晶相爲非結晶 的結構，以增加在多晶矽層中之不純物例如硼或砷的擴散 路徑，因而可減緩不純物由矽化鎢層擴散至其他元件之機 率。 3·矽化鎢與氮矽化鎢間所產生的應力較矽化鎢與氮化 鎢或氮化鈦爲小，故可避免後續進行熱製程時，發生矽化 6 本紙張尺度適用中國國家榡準（CNS ) a4規格（21〇χ 297公釐） (請先閱讀背面t注意事項存填寫本頁)
477004 3 796twf.doc/008 Η ? 五、發明説明（^ ) 鎢層剝落。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 經濟部中央標準局員工消費合作社印掣 7 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公浼）

Claims (1)

  1. 477004 A8 B8 3 796twf.doc/008 C8 D8 六、申請專利範圍 1. 一種防止雙閘極中之摻質擴散之方法，包括： 在具有一隔離結構與一井之一基底上形成一閘氧化 (請先閱讀背面之注意事項再填寫本頁) 層； 在該閘氧化層上形成一多晶矽層； 在該多晶矽層上形成一第一導電層； 進行一電漿處理步驟，形成一阻障層；以及 在該阻障層上形成一第二導電層。 2. 如申請專利範圍第1項所述之方法，其中該第一導 電層之材質爲含矽較多之矽化鎢金屬。 3. 如申請專利範圍第1項所述之方法，其中形成該第 一導電層係以化學氣相沉積法進行。 4. 如申請專利範圍第1項所述之方法，其中進行該電 漿處理步驟係使用氮氣爲電漿氣體。 5. 如申請專利範圍第1項所述之方法，其中進行該電 漿處理步驟係使用氨氣爲電漿氣體。 6. 如申請專利範圍第1項所述之方法，其中進行該電 漿處理步驟所使用之操作壓力約2 mToir左右，功率爲300 至500 W左右。 經濟部中央標準局員工消費合作社印製 7. 如申請專利範圍第1項所述之方法，其中該阻障層 之材質爲氮矽化鎢金屬。 8. 如申請專利範圍第1項所述之方法，其中該阻障層 之材質爲非結晶之氮矽化鎢金屬。 9. 如申請專利範圍第1項所述之方法，其中形成該第 二導電層係以化學氣相沉積法進行。 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~ 477004 3796tvvf.doc/008 A8 B8 C8 D8 六、申請專利範圍 10. 如申請專利範圍第1項所述之方法 電層之材質爲含鎢較多之矽化鎢金屬。 11. 如申請專利範圍第1項所述之方法 P型閘極與一 η型閘極，以及一源極/汲極 極之製作。 更包括形成一 以完成該雙閘 L-Il·.— I"-10------1T------·1 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐）
TW087116873A 1998-10-12 1998-10-12 Method to prevent dopant diffusion in dual-gate TW477004B (en)

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TW087116873A TW477004B (en) 1998-10-12 1998-10-12 Method to prevent dopant diffusion in dual-gate
US09/206,187 US6060361A (en) 1998-10-12 1998-12-04 Method for preventing dopant diffusion in dual gate device

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US6861356B2 (en) 1997-11-05 2005-03-01 Tokyo Electron Limited Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
US6197672B1 (en) * 1998-12-08 2001-03-06 United Microelectronics Corp. Method for forming polycide dual gate
US6376349B1 (en) * 2000-01-19 2002-04-23 Motorola, Inc. Process for forming a semiconductor device and a conductive structure
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