CN101345260B - 半导体结构 - Google Patents
半导体结构 Download PDFInfo
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- CN101345260B CN101345260B CN2008101378337A CN200810137833A CN101345260B CN 101345260 B CN101345260 B CN 101345260B CN 2008101378337 A CN2008101378337 A CN 2008101378337A CN 200810137833 A CN200810137833 A CN 200810137833A CN 101345260 B CN101345260 B CN 101345260B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000003870 refractory metal Substances 0.000 claims abstract description 68
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 61
- 239000010703 silicon Substances 0.000 claims abstract description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 229910052741 iridium Inorganic materials 0.000 claims description 101
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 101
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 229920005591 polysilicon Polymers 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 24
- 150000003376 silicon Chemical class 0.000 claims description 22
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 10
- 239000011435 rock Substances 0.000 claims description 8
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910003855 HfAlO Inorganic materials 0.000 claims description 4
- 229910004129 HfSiO Inorganic materials 0.000 claims description 4
- 229910052702 rhenium Inorganic materials 0.000 claims description 4
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 abstract description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 11
- 230000008901 benefit Effects 0.000 abstract description 6
- 230000007812 deficiency Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 22
- 230000015572 biosynthetic process Effects 0.000 description 17
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000011819 refractory material Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910004200 TaSiN Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- 206010010144 Completed suicide Diseases 0.000 description 1
- 229910016006 MoSi Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- -1 for example IrSi Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007725 thermal activation Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
- H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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Abstract
一种半导体结构,包括:耐火金属硅化层;富硅耐火金属硅化层,位于该耐火金属硅化物上;以及富金属耐火金属硅化层,位于该富硅耐火金属硅化层上。该耐火金属硅化层、该富硅耐火金属硅化层与富金属耐火金属硅化层包括相同的耐火材料。该半导体结构构成金属氧化物半导体元件的栅极电极的一部分。本发明利用与带缘功函数相关的优势,且同时克服现有技术的不足。
Description
技术领域
本发明涉及半导体元件,尤其涉及MOS结构元件与其制造方法,且尤其涉及p型MOS元件的栅极电极的形成。
背景技术
MOS元件为集成电路中的基础构成元件。常见的MOS元件一般具有栅极电极,其包括使用例如离子掺杂或热扩散方法进行的以p型或n型杂质掺杂的多晶硅。栅极电极的功函数较佳调整为硅的带缘(band-edge);对NMOS元件而言调整功函数接近导电带(conduction band)而对PMOS元件而言,则调整功函数接近价电带(valence band)。可通过选择适合的掺杂来达成调整多晶硅栅极电极的功函数。
具有多晶硅栅极电极的MOS元件存在着载流子耗尽的现象(carrierdepletion effect),也称为多晶硅耗尽效应(poly-depletion effect)。当应用电场从接近栅极介电层的区域清除载流子,而形成耗尽层时会产生多晶硅耗尽效应。在n掺杂多晶硅层中,耗尽层包括离子化非移动性供给位(ionizednon-mobile donor site),而在p掺杂多晶硅层中,耗尽层则包括离子化非移动性接受位(ionized non-mobile acceptor site)。耗尽效应导致有效栅极介电层的厚度增加,造成更难在半导体表面产生反转层(inversion layer)。
而薄栅极介电层使载流子耗尽的现象更严重。对薄栅极介电层而言,在多晶硅栅极中的耗尽层厚度相较于薄栅极介电层的厚度而言变为更加显著,且因此造成元件性能降低。于是,在栅极电极中的载流子耗尽效应限制了栅极介电层有效厚度的下限,因此限制了元件尺寸的缩小化。
使用薄栅氧化层的另一个问题是增加了栅极漏电流。因此,常以高介电常数介电层来减少栅极漏电流。然而高介电常数介电材料由于费米能级钉扎效应(Fermi level pinning)不与多晶硅栅极电极相容。
多晶硅耗尽效应与高介电常数不相容的问题可通过形成金属栅极电极或金属硅化栅极电极来解决,其中在NMOS与PMOS元件中所使用金属栅极较佳也具有带缘功函数。现今已发现形成NMOS元件栅极电极的适合材料。然而对于PMOS元件而言,虽然可获得具有带缘功函数的金属材料,但这些材料的热稳定性差。当暴露于前端工艺(front-end-of-line)步骤的高温时,这些金属材料的功函数偏移,例如朝向中间能带(mid gap)程度,而影响了PMOS元件的功效。此外,在暴露于高温之后,这些功函数金属的电容等价厚度(capacitance-equivalent-thickness,CET)变得高于具有低功函数的金属。
铱与铂为具有高功函数的最有希望的金属。然而铂的工艺处理并不容易,且其很难以常见的反应离子蚀刻(reactive ion etch,RIE)来把铂层图案化作为栅极。另一方面,铱的工艺处理较容易。然而已发现纯铱栅极存在严重的扩散问题,其中在1000℃快速热活化之后,铱会穿透过高介电常数材料。
因此本技术领域需要半导体结构与其形成方法,其利用与带缘功函数相关的优势,且同时克服现有技术的不足。
发明内容
本发明提供一种半导体结构,包括:耐火金属硅化层;富硅耐火金属硅化层,位于该耐火金属硅化层上;以及富金属耐火金属硅化层,位于该富硅耐火金属硅化层上。该耐火金属硅化层、该富硅耐火金属硅化层与富金属耐火金属硅化层包括相同的耐火材料。
本发明提供另一种半导体结构,包括:基底;栅极介电层,位于该基底上;耐火金属硅化层,位于该栅极介电层上;以及富硅耐火金属硅化层,位于该耐火金属硅化层上。该耐火金属硅化层与该富硅耐火金属硅化层包括相同的耐火材料;富金属耐火金属硅化层,位于该富硅耐火金属硅化层上;多晶硅层,位于该富金属耐火金属硅化层上。
在所述的半导体结构中,还包括:盖层,位于该富硅耐火金属硅化层与该多晶硅层之间,且位于该富金属耐火金属硅化层与该多晶硅层之间。
在所述的半导体结构中,该耐火金属包括铱、钼、钨、铼、钽、铂或上述的组合。
在所述的半导体结构中,该耐火金属只包括铱。
在所述的半导体结构中,该富硅耐火金属硅化层的硅原子百分比大于约70%。
在所述的半导体结构中,该栅极介电层包括高介电常数材料,其包括氮化硅、氮氧化硅、HfO2、HfZrOx、HfSiOx、HfTiON、Al2O3、HfAlOx、ZrO2、HfZrO、HfZrON、HfTaO、HfTaTiO或上述的组合。
本发明还提供一种半导体结构,包括:基底;栅极介电层,位于该基底上;以及层叠式硅化铱层。该层叠式硅化铱层包括:硅化铱层,位于该栅极介电层上;富硅硅化铱层,位于该硅化铱层上;以及富铱硅化铱层,位于该富硅硅化铱层上。该半导体结构还包括:多晶硅层,位于该富铱硅化铱层上;栅极间隙壁,位于该层叠式硅化铱层与该多晶硅层的侧壁上;以及p型源/漏极区,位于该半导体基底中且与该栅极介电层相邻。
在所述的半导体结构中,该富硅硅化铱层的硅原子百分比大于约70%,且该富铱硅化铱层的铱原子百分比大于约70%。
本发明还提供一种形成半导体结构的方法,包括:形成耐火金属硅化层;形成富硅耐火金属硅化层,位于该耐火金属硅化层上;以及形成富金属耐火金属硅化层,位于该富硅耐火金属硅化层上。该耐火金属硅化层、该富硅耐火金属硅化层与富金属耐火金属硅化层包括相同的耐火材料。
本发明另提供一种形成半导体结构的方法,包括:提供基底;形成栅极介电层,位于该基底上;形成耐火金属硅化层,位于该栅极介电层上;以及形成富硅耐火金属硅化层,于该耐火金属硅化层上。
本发明又提供一种形成半导体结构的方法,包括:提供基底;形成高介电常数栅极介电层,位于该基底上;以及形成层叠式硅化铱层,其形成方法包括形成硅化铱层,位于该高介电常数栅极介电层上;形成富硅硅化铱层,位于该硅化铱层上;以及形成富铱硅化铱层,位于该富硅硅化铱层上。方法还包括形成多晶硅层,位于该富硅硅化铱层上;形成栅极间隙壁,位于该层叠式硅化铱层与该多晶硅层的侧壁上;以及形成源/漏极区,位于该半导体基底中且与该高介电常数栅极介电层相邻。
本发明利用与带缘功函数相关的优势,且同时克服现有技术的不足。
为了让本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举优选实施例,并配合所附附图,作详细说明如下:
附图说明
图1显示本发明实施例的工艺剖面图,其显示提供基底与形成界面层。
图2显示本发明实施例的工艺剖面图,其显示栅极介电层与层叠式金属硅化层的形成。
图3显示本发明实施例的工艺剖面图,其显示盖层28与多晶硅层30的形成。
图4显示本发明实施例的工艺剖面图,其显示将堆叠层图案化,形成栅极堆叠。
图5显示本发明实施例的工艺剖面图,其显示PMOS元件剩余组成的形成。
图6显示本发明优选实施例的变化例。
其中,附图标记说明如下:
20~基底
22~界面层
23~界面层22的一部分
24~栅极介电层
26、36~层叠式金属硅化层
261~硅化铱层
262~富硅硅化铱层
263~富铱硅化铱层
28、38~盖层
30、40~多晶硅层
32~栅极堆叠
34~栅极介电层
42~轻掺杂源/漏极区
44~栅极间隙壁与
46~源/漏极区
48~硅化区
60~非晶硅层
62~耐火金属层
具体实施方式
本发明提供具有一层叠式栅极结构的MOS元件与形成方法。已绘出本发明制造优选实施例的中间步骤。在本发明的内容与附图中,相同的标号代表相同的元件。
在图1中,提供基底20,其较佳为硅基底。基底20也可包括其他含硅半导体材料,例如硅锗。此外,基底20可为块状半导体、应力半导体、化合物半导体绝缘层上半导体(semiconductor-on-insulator,SOI)等形式。较佳通过在基底20中蚀刻沟槽且以绝缘体(例如,氧化硅)填满沟槽以在基底20中形成浅沟槽隔离(Shallow trench isolation,STI)区。
在基底20之上形成界面层(interfacial layer)22。界面层22的较佳厚度小于约且可包括化学氧化硅,其较佳由化学反应或UV-O3氧化硅形成,而UV-O3氧化硅是通过在含臭氧环境中将基底20暴露于紫外光下来形成。或者,界面层22可包括氮氧化硅、氮化硅等。行业相关技术人员将能了解其个别的形成工艺。
图2显示栅极介电层24与层叠式金属硅化层26的形成。在一个实施例中,栅极介电层包括氧化硅。在另一个实施例中,栅极介电层24包括介电材料具有高介电常数(k值),例如大于约3.9。适当的材料包括氮化硅、氮氧化硅、HfO2、HfZrOx、HfSiOx、HfTiON、Al2O3、HfAlOx、ZrO2、HfZrO、HfZrON、HfTaO、HfSiON、HfAlON、HfTaTiO等、上述的组合或其的多层。较佳厚度为约形成方法包括一般使用的方法,例如原子层沉积(atomic layer deposition,ALD)、化学气相沉积、金属有机化学气相沉积(metalorganic chemical vapor deposition,MOCVD)与物理气相沉积等。若需要,可通过电浆氮化(plasma nitridation)或热氮化(thermal nitridation)将氮加入栅极介电层24中,其中氮的比例较佳小于约30%。
在沉积栅极介电层24之后,执行后沉积退火(post-deposition annealing)。在一个实施例中,在含N2、O2、H2、D2、NH3、钝气或上述的组合的环境中执行后沉积退火。也可包括载体气体,例如氩气。后沉积退火的温度较佳为400-1200℃。
之后沉积层叠式金属硅化层26。在优选实施例中,层叠式金属硅化层包括硅化铱层261、富硅硅化铱层262在硅化铱层261上,以及富铱硅化铱层263在富硅硅化铱层262上。沉积方法包括一般使用的方法,例如物理气相沉积、原子层沉积、金属有机化学气相沉积与溅镀等。在实施例中,沉积方法为物理气相沉积,其以铱靶材与硅靶材来执行,且通过调整实施于铱靶材与实施于硅靶材的能量比率来调整硅化铱层261、262与263。在另一个实施例中,通过从铱硅化靶材溅镀来形成硅化铱层261、262与263,其中通过使用具有不同成分的硅化铱靶材及/或通过调整能量设定来达到硅化铱层261、262与263的不同成分。
261、262与263各层的较佳厚度为约且硅化铱层261、262与263层的结合厚度为约在硅化铱层261中铱原子数与硅原子数的比例为约0.5-1.5。富硅硅化铱层262的硅原子百分比较佳为大于约70%,其中硅原子百分比是以硅的原子数除以硅与铱的原子数来计算。富铱硅化铱层263的铱原子百分比较佳为大于约70%,其中铱原子百分比是以铱的原子数除以硅与铱的原子数来计算。在另一个实施例中,只形成硅化铱层261与富硅硅化铱层262而省略富铱硅化铱层263。
在优选实施例中,金属硅化层26为层叠式硅化铱层。在另一个实施例中,金属硅化层26包括其他耐火材料的层叠式硅化层,例如钼硅化物、钨硅化物、铼硅化物、钽硅化物、铂硅化物与上述的组合。较佳为在层叠式结构中的耐火材料具有相似的原子百分比例如同硅化铱层261、262与263。
在图3中,形成盖层28与多晶硅层30。盖层28可包括Mo、TaN、TiN、TaSiN、TaC或上述的组合,且其具有避免硅化铱层26氧化的功能。盖层28的厚度较佳为约
在图4中,将堆叠层图案化,形成栅极堆叠32,其包括栅极介电层34、层叠式金属硅化层36、盖层38与多晶硅层40。在一个优选实施例中,以反应离子蚀刻来执行图案化,虽然也可使用其他常用的图案化方法。在图案化之后,剩下界面层22的一部分23。之后形成轻掺杂源/漏极(lightly dopedsource/drain,LDD)区42,其较佳通过注入p型杂质(例如硼)于半导体基底20中来形成。
图5显示PMOS元件剩余组成的形成,其包括栅极间隙壁44与源/漏极区46。可通过毯覆式沉积介电层例如氮化硅来形成栅极间隙壁44,并且之后将不需要的部分蚀刻去除。栅极间隙壁44也可具有混合结构,例如氧化物上氮化物(nitride-on-oxide)或氧化物-氮化物-氧化物(oxide-nitride-oxide,ONO)结构。
之后形成源/漏极区46与硅化区48。在优选实施例中,通过注入p型杂质,例如硼及/或铟进入基底20中来形成源/漏极区46,其中在进行注入时,将栅极间隙壁44作为掩模以使源/漏极区46的边缘实质上分别与栅极间隙壁44对齐。源/漏极区46的形成也可包括使基底20产生凹陷且在凹陷处外延成长半导体材料,例如硅锗。为了形成硅化区48,可先形成一个薄金属层(未显示)于元件上,例如钴、镍、铂或上述的组合。之后将元件进行退火以在沉积金属与下层硅区之间形成硅化区48。而之后将未反应的金属层移除。
图6显示优选实施例的变化例。此变化例的起始步骤实质上与图1所显示相同。之后如图6所示,形成非晶硅层60。在优选实施例中,非晶硅层60的厚度为约且更佳为约之后将耐火金属层62沉积于非晶硅层60上。在优选实施例中,耐火金属层62由铱形成。在另一个实施例中,耐火金属层62包括铱、钼、钨、铼、钽、铂与上述的组合。又在另一个实施例中,耐火金属层62可包括金属硅化物,例如IrSi、MoSi2、WSi2、ReSi/ReSi2、TaSi2、PtSi等。耐火金属层62的厚度较佳为约
之后将非晶硅层60与耐火金属层62进行退火以产生硅化反应,形成如图2所示的结构。为了形成层叠式硅化区,需小心调控工艺条件。在一个实施例中,退火为快速热退火(rapid thermal annealing,RTA),其中退火温度较佳为约400-1200℃,更佳为约800-1100℃。退火持续时间较佳为约5-30秒,更佳为约5-15秒。而且非晶硅层60与耐火金属层62的厚度会影响所形成的硅化结构。在一个实施例中,对上述所讨论的退火温度与时间而言,非晶硅层60与耐火金属层62的厚度较佳分别为约与在此工艺下,形成层叠式结构包括硅化铱层261、富硅硅化铱层262与富铱硅化铱层263。
在接下来的工艺步骤中,沉积盖层28与多晶硅层30以形成如图3所示的结构。之后将工艺持续以形成PMOS元件的剩余结构,如图4与图5所示。
本领域相关技术人员应当可以了解,虽然所述附图是对于形成PMOS元件,但本发明的示范也可以实施于形成NMOS元件上。较佳为NMOS元件包括具有低功函数的之带缘金属栅极。较佳的金属包括TaC、TaN、TaSiN、HfN、La或上述的组合,且其可通过物理气相沉积、原子层沉积或金属有机化学气相沉积来进行沉积。金属厚度为约1-30nm。本领域相关技术人员当可了解相对应的形成步骤。
本发明的实施例具有需多优点。已发现的有,层叠式硅化铱层的平能带电位(flat band voltage)为约0.848V,此代表功函数大于约5.0eV。高介电常数材料与层叠式硅化层的组合使电容等价厚度减少,其甚至比得上HfO2上的TaC。硅化铱的扩散较少,且没有发现硅化铱与高介电常数材料间的相互扩散(inter-diffusion)。此外,在所产生的PMOS元件中,由于铱扩散减少,界面层的增加变为微不足道。
虽然本发明已经以优选实施例公开如上,然而其并非用以限定本发明,任何本领域相关技术人员,在不脱离本发明的精神和范围内,当可作出部分改动,因此本发明的保护范围当视后附的权利要求书所界定的范围为准。
Claims (12)
1.一种半导体结构,包括:
基底;
栅极介电层,位于该基底上;
耐火金属硅化层,位于该栅极介电层上;以及
富硅耐火金属硅化层,位于该耐火金属硅化层上,其中该耐火金属硅化层与该富硅耐火金属硅化层包括相同的耐火金属;
富金属耐火金属硅化层,位于该富硅耐火金属硅化层上;
多晶硅层,位于该富金属耐火金属硅化层上。
2.如权利要求1所述的半导体结构,还包括:盖层,位于该富硅耐火金属硅化层与该多晶硅层之间,且位于该富金属耐火金属硅化层与该多晶硅层之间。
3.如权利要求1所述的半导体结构,其中该耐火金属包括铱、钼、钨、铼、钽、铂或上述的组合。
4.如权利要求1所述的半导体结构,其中该耐火金属只包括铱。
5.如权利要求1所述的半导体结构,其中该富硅耐火金属硅化层的硅原子百分比大于70%。
7.如权利要求1所述的半导体结构,其中该栅极介电层包括高介电常数材料,其包括氮化硅、氮氧化硅、HfO2、HfZrOx、HfSiOx、HfTiON、Al2O3、HfAlOx、ZrO2、HfZrON、HfTaO、HfTaTiO或上述的组合。
8.如权利要求1所述的半导体结构,其中该栅极介电层包括高介电常数材料,其包括氮化硅、氮氧化硅、HfO2、HfSiOx、HfTiON、Al2O3、HfAlOx、ZrO2、HfZrO、HfZrON、HfTaO、HfTaTiO或上述的组合。
9.一种半导体结构,包括:
基底;
栅极介电层,位于该基底上;
层叠式硅化铱层,包括:
硅化铱层,位于该栅极介电层上;
富硅硅化铱层,位于该硅化铱层上;以及
富铱硅化铱层,位于该富硅硅化铱层上;
多晶硅层,位于该富铱硅化铱层上;
栅极间隙壁,位于该层叠式硅化铱层与该多晶硅层的侧壁上;以及
源/漏极区,位于该基底中且与该栅极介电层相邻。
10.如权利要求9所述的半导体结构,其中该富硅硅化铱层的硅原子百分比大于70%,且该富铱硅化铱层的铱原子百分比大于70%。
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US94864607P | 2007-07-09 | 2007-07-09 | |
US60/948,646 | 2007-07-09 | ||
US11/840,365 US8159035B2 (en) | 2007-07-09 | 2007-08-17 | Metal gates of PMOS devices having high work functions |
US11/840,365 | 2007-08-17 |
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2007
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US8159035B2 (en) | 2012-04-17 |
TW200908162A (en) | 2009-02-16 |
US20090014813A1 (en) | 2009-01-15 |
TWI397962B (zh) | 2013-06-01 |
CN101345260A (zh) | 2009-01-14 |
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