TW474456U - Semiconductor apparatus - Google Patents

Semiconductor apparatus

Info

Publication number
TW474456U
TW474456U TW088220993U TW88220993U TW474456U TW 474456 U TW474456 U TW 474456U TW 088220993 U TW088220993 U TW 088220993U TW 88220993 U TW88220993 U TW 88220993U TW 474456 U TW474456 U TW 474456U
Authority
TW
Taiwan
Prior art keywords
semiconductor apparatus
semiconductor
Prior art date
Application number
TW088220993U
Other languages
English (en)
Inventor
Yoshikazu Ohno
Hiroki Shinkawata
Takahiro Yokoi
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of TW474456U publication Critical patent/TW474456U/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
TW088220993U 1996-03-29 1996-09-03 Semiconductor apparatus TW474456U (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8076320A JPH09270461A (ja) 1996-03-29 1996-03-29 半導体装置

Publications (1)

Publication Number Publication Date
TW474456U true TW474456U (en) 2002-01-21

Family

ID=13602082

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088220993U TW474456U (en) 1996-03-29 1996-09-03 Semiconductor apparatus

Country Status (5)

Country Link
US (1) US5828096A (zh)
JP (1) JPH09270461A (zh)
KR (1) KR100234835B1 (zh)
DE (1) DE19638684C2 (zh)
TW (1) TW474456U (zh)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996022612A1 (en) 1995-01-19 1996-07-25 Micron Technology, Inc. Method of forming transistors in a peripheral circuit
JP3272979B2 (ja) * 1997-01-08 2002-04-08 株式会社東芝 半導体装置
US6849557B1 (en) 1997-04-30 2005-02-01 Micron Technology, Inc. Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide
JP3577195B2 (ja) 1997-05-15 2004-10-13 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6486023B1 (en) * 1997-10-31 2002-11-26 Texas Instruments Incorporated Memory device with surface-channel peripheral transistor
KR100251228B1 (ko) * 1997-12-31 2000-04-15 윤종용 반도체 메모리 장치의 콘택 형성방법 및 그 구조
JP3114931B2 (ja) * 1998-03-30 2000-12-04 日本電気株式会社 導電体プラグを備えた半導体装置およびその製造方法
US6133599A (en) * 1998-04-01 2000-10-17 Vanguard International Semiconductor Corporation Design and a novel process for formation of DRAM bit line and capacitor node contacts
JP3718058B2 (ja) * 1998-06-17 2005-11-16 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6875371B1 (en) 1998-06-22 2005-04-05 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US6117791A (en) * 1998-06-22 2000-09-12 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US7173339B1 (en) 1998-06-22 2007-02-06 Micron Technology, Inc. Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure
KR100299594B1 (ko) * 1998-07-13 2001-09-22 윤종용 디램 장치의 제조 방법
JP4776747B2 (ja) * 1998-11-12 2011-09-21 株式会社ハイニックスセミコンダクター 半導体素子のコンタクト形成方法
JP2000223569A (ja) * 1999-02-03 2000-08-11 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4807894B2 (ja) 1999-05-31 2011-11-02 ルネサスエレクトロニクス株式会社 半導体装置
KR100470165B1 (ko) 1999-06-28 2005-02-07 주식회사 하이닉스반도체 반도체소자 제조 방법
US6251770B1 (en) * 1999-06-30 2001-06-26 Lam Research Corp. Dual-damascene dielectric structures and methods for making the same
JP2001102550A (ja) * 1999-09-02 2001-04-13 Samsung Electronics Co Ltd 自己整合コンタクトを有する半導体メモリ装置及びその製造方法
KR100474546B1 (ko) * 1999-12-24 2005-03-08 주식회사 하이닉스반도체 반도체소자의 제조방법
JP4068781B2 (ja) * 2000-02-28 2008-03-26 株式会社ルネサステクノロジ 半導体集積回路装置および半導体集積回路装置の製造方法
US6486015B1 (en) * 2000-04-25 2002-11-26 Infineon Technologies Ag Low temperature carbon rich oxy-nitride for improved RIE selectivity
US6479385B1 (en) * 2000-05-31 2002-11-12 Taiwan Semiconductor Manufacturing Company Interlevel dielectric composite layer for insulation of polysilicon and metal structures
KR100338775B1 (ko) * 2000-06-20 2002-05-31 윤종용 Ｄｒａｍ을 포함하는 반도체 소자의 콘택 구조체 및 그형성방법
JP2002217383A (ja) * 2001-01-12 2002-08-02 Hitachi Ltd 半導体集積回路装置の製造方法および半導体集積回路装置
US6989108B2 (en) * 2001-08-30 2006-01-24 Micron Technology, Inc. Etchant gas composition
KR100539276B1 (ko) * 2003-04-02 2005-12-27 삼성전자주식회사 게이트 라인을 포함하는 반도체 장치 및 이의 제조 방법
US7794616B2 (en) 2004-08-09 2010-09-14 Tokyo Electron Limited Etching gas, etching method and etching gas evaluation method
JP2006049771A (ja) * 2004-08-09 2006-02-16 Tokyo Electron Ltd エッチングガス，エッチング方法及びエッチングガスの評価方法
JP5578952B2 (ja) * 2009-08-19 2014-08-27 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
KR20210085421A (ko) * 2019-12-30 2021-07-08 에스케이하이닉스 주식회사 반도체 장치

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61183952A (ja) * 1985-02-09 1986-08-16 Fujitsu Ltd 半導体記憶装置及びその製造方法
JP2615076B2 (ja) * 1987-09-19 1997-05-28 株式会社日立製作所 半導体集積回路装置の製造方法
US5378652A (en) * 1989-04-19 1995-01-03 Kabushiki Kaisha Toshiba Method of making a through hole in multi-layer insulating films
JP2750183B2 (ja) * 1989-12-12 1998-05-13 沖電気工業株式会社 半導体記憶装置の製造方法
NL9100094A (nl) * 1991-01-21 1992-08-17 Koninkl Philips Electronics Nv Halfgeleiderinrichting en werkwijze ter vervaardiging van een dergelijke halfgeleiderinrichting.
KR960000366B1 (ko) * 1992-07-08 1996-01-05 삼성전자주식회사 반도체 장치의 콘택 형성방법
JP3342164B2 (ja) * 1993-04-16 2002-11-05 三菱電機株式会社 半導体装置およびその製造方法
JPH0870105A (ja) * 1994-08-30 1996-03-12 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法

Also Published As

Publication number Publication date
JPH09270461A (ja) 1997-10-14
KR100234835B1 (ko) 1999-12-15
US5828096A (en) 1998-10-27
KR970067775A (ko) 1997-10-13
DE19638684A1 (de) 1997-10-02
DE19638684C2 (de) 2003-12-11

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Legal Events

Date Code Title Description
GD4K Issue of patent certificate for granted utility model filed before june 30, 2004
MK4K Expiration of patent term of a granted utility model