TW472342B - Lateral thin-film silicon-on-insulator (SOI) device having a lateral drift region with a retrograde doping profile, and method of making such a device - Google Patents

Lateral thin-film silicon-on-insulator (SOI) device having a lateral drift region with a retrograde doping profile, and method of making such a device Download PDF

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TW472342B
TW472342B TW089124971A TW89124971A TW472342B TW 472342 B TW472342 B TW 472342B TW 089124971 A TW089124971 A TW 089124971A TW 89124971 A TW89124971 A TW 89124971A TW 472342 B TW472342 B TW 472342B
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lateral
layer
insulating layer
drift region
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Theodore Letavic
Mark Simpson
Richard Egloff
Andrew Mark Warwick
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Koninkl Philips Electronics Nv
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0843—Source or drain regions of field-effect devices
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    • H01L29/402—Field plates
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region

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Description

472342
發明背景 本發明為半導體上絕緣（SOI)穿晋士、甘曰Μ Λ 高電壓應用的側向S(HH，尤其疋關於適用於 在製造高電壓功率裝置時二製土造此種裝置的方法。 尺寸，雷阳二本上對於像是崩潰電壓， 窄六施汗。 1仏的簡易性與可靠性等範圍，皆必 ，即會造成另一個參數：:、Γί:個f數，如崩潰電壓 ，這種裝置將具有在所上:^ 的運作及製造缺點。 的優良㈣’並具有最小 A板二L 薄1裝置的形式包含-半導體 鹿’Λ 入絕緣層，及在埋入絕緣層上一 T層中的-側向電晶體裝置，該敦置像是mosfet，其包 3在該埋入絕緣層上的一半導體表面層，並包含一第一 =的：；極區·’其形成於相對於該第-導電形式的 =第一導電形式的一主體區域中，一絕緣閘極，其位在 该主體區域的-通道區域上’並由—表面絕緣區域來絕緣 ，-淡摻雜側向區4 ’例如該第_導電形式的一側向漂移 區域’該第-導電形式的-沒極區域，其係被該漂移區域 側向地與該通道區域相隔開。 此種形式的一裝置示於圖！，其相同與相關的美國專利 編號5,246,87〇(方法的提出），及5,412,24置的 ，其共同授權給本發明申請案，並在此引用做為參考。圖 1所示的前述發明的裝置為-具有多種特色的侧向s〇i M〇sm裝置，例如-具有-直線側向摻雜區域及—覆蓋場
472342 五、發明說明（2) 板的一變薄的SO I層，以改善運作。如習用方式，該裝置 為一η-通道或NM0S電晶體，其具有n型源極與汲極區域， 使用習用稱為Ν Μ 0 S技術的處理來製造。一更為基本的裝置 示於美國專利編號5, 300, 448中，其也共同授權給本發明 申請案，並在此引用做為參考。 用於改善S 〇 I功率裝置的高電壓及高電流效能參數的更 為先進的技術，係由美國專利申請編號08/998, 048所提出 ’其共同授權給本發明申請案，並在此引用做為參考。 因此’其可瞭解到有不同的技術及方法已被用來改善功 率半導體裝置的功率，並持續努力地達到一更為接近最佳 化的參數组合’例如崩潰電壓，尺寸，電流承載能力，及 製造的簡易性等等。當所有前述的結構提供了裝置效能上 =同程度的改善，並沒有一個裝置或結構能夠最佳化所有 高電壓及高電流運作的設計需求。 ，此’有需要提出一電晶體裝置結構，其能夠在高電麗 ^高電流的環境下提供高效能，其中運作參數，尤其是崩 潰電壓，及/或"開啟"電阻，另可被最佳化。 '、 發明概述 因此本發明的目的即在於提供一電晶體裝置結構，豆能 在—高電壓，高電流環境中提供高效能。本發明的另一 崩：ί要提供一種電晶體裝置結構’其中運作參數，像是 明巧電壓及/或11開啟"電阻能夠被改善。 根據本發明，這4b目的可以與由μ、+、& 裝置任m π 4 A t — 述的—侧向薄膜如1 置^構形式來達成’其中一淡摻雜側向區域（基本上為 472342 提供一反向摻雜截面，所以在相鄰於上 部份的該摻雜截面可大於相鄰於該^;读埂入 域的該側向區域的一部份的摻雜度。 Λ、面絕緣區 在本發明的一較佳具體實施例中，一坤推雜。 該反向摻雜截面’而在相鄰於該埋入絕緣層的$用來違至,！ 區域的該部份的摻雜度大約是高於相鄰於該表面^向漂移 的該側向漂移區域的該部份之摻雜度的5 〇 % ^ 、、邑緣區域 在本發明的另一較佳具體實施例中，根據本 ，其製造方法是該半導體基板係已一需要的摻^ =的裝置 ，該半導體基板被氧化來形成包含有該摻雜劑的=來摻雜 緣層，一SOI層係形成在包含該摻雜劑的該埋入、^埋入絕 ，、而該摻雜劑係由該埋入絕緣層熱擴散到該s〇i芦、，、，層上 成該反向摻雜截面。 s ’而形 合==:側向薄膜s〇I裝置提供了較佳效能特性組 产的^ p ？ Q ，並使該裝置達到適於在—高電壓，高電 Ϊ阻Γ兄下運作，尤其是高崩潰電壓及/或降低的"開啟Μ t ^ ^的延些及其它方面，將可藉由以下的具體實施例 次明而得到進一步瞭解。 圖式簡單說明 所^ =明可參考以下說明而得到更完整的瞭解，並可配合 上二面’其中唯一的圖面所示為根據本發明的一較佳具 ^轭例的一側向薄膜S〇I裝置的一簡化截面圖。 此圖中’具有相同導電形式的半導體區域通常是以該 472342 五、發明說明（4) '~ ' 〜- 截面圖中相同方向的剖面線來表示，其必須瞭解到此 非以等比例繪製。 較佳具體實施例的說明 在圖中該簡化的截面中，一側向薄膜裝置，此處為一 SOI MOS電晶體20，其包含一半導體基板22，一埋入絕緣 層24，及半‘體表面SOI層26，其中用來製造該裝置。 該M0S電晶體包含-導電形式的—源極區域^，一第二相 式=體區域3°，該第-導電形式的-側向漂 34 I』θ第2:一淡接雜沒極區域及-汲極接觸區域 ,、也疋弟一導電形式。該基士 ^ 閘極36來完成，其係由—量 1化的4置、、Ό構係由一 體表面層26所絕緣。在本：明：面：：區域38的底部半導 做為本發明的該啟始點本該廳電晶體係 例如-線性側向摻雜截面：一逐匕同的效能1進特性， 側向漂移區域部份1 了^%板部份36Α，36Β，一變薄的 中’或其它需要效能增進特在丨生前述b對… 或範圍。此外，該M〇s番曰性，白不會背離本發明的精神 40，其與源極28相接觸曰曰、體2〇也可包含一表面接觸區域 主體區域具有相同的導雷在該主體區域3〇中，並與該 構係由一介電層4 2來完成/ 但有更高的摻雜度。該結 處所示為經由該介電屏 在其上有—金屬接觸層44 ,此 本上係由複晶矽製作）。、孔洞來接觸到該閘極3 6 (基 其可瞭解到，圖中所示的該“ 472342 五、發明說明（5) 述了 一特殊的裝置結構，龅 大的不同，但皆食匕夠/ 士在種裳置幾何及架構中有很 昍矸被λ入J: !约在本發明的範圍中使用。此外，本發 m3 不同形式的高電壓薄獅裝置，其具 *。。、氐°、’、“ ’對於那些本技藝的專業人士皆應很熟 ==述說明的結構通f具有良 限於最大可達到的崩 '、主赍兩从 咬IF竹丨王兵仍又 前技藝裝置中的效能：：值及’'開啟M電阻的組合。在先 的接雜度之間的本質： = : :=在=移區域中較高 的該部份形成了淡摻雜没極 二彳=域 ，在此區域中的吁齢& ，、而要低的開啟"電阻 A Η所、f Y°亥較低摻雜度則需要最佳化的崩潰電壓。 〇 "不同的手段，例如改變此區域的厚产，1 % g -側向層級的線性接雜截面 ”或利用 善該"開啟"電阻/崩、、主m V 内上），可以略為改 力太私日Η 士圖但仍需要更多的改善。 ^ 中，此改善可利用一不同的方法來、查.
七 π ^ 飞的先刖技藝裝置在整個該soI層的Μ I 有-固定的摻雜截面(例如在垂直方，曰的厚度中具 少該SO I層的—部ρ . 本叙明即在至 批一始Θ沾 M々中改變垂直方向上的摻雜程户，士楹 ’、"、’及具商義價值的方法來達到。更牲^ 一改善的裝置可出姐 c 灵特疋而言’ 供一反向摻雜截面來製抨 於該埋入絕緣屛沾 a 化·’其中相鄰 豕增的该側向漂移區域的該部份的他 於在該SOI層的s，丨、加八L 切的摻雜，可大 _ 妁至少一部份上的相鄰於該表面砂& f側向漂移區域的該部份的摻II。換言之，=象區域的 區域中的該摻雜係由此區域的頂部增加到該底;;侧向漂移
第10頁 472342 五、發明說明（6) 二種Λ?/的好處是由於該裂置的"開啟"電阻传根攄 整個厚度的實際的電荷分佑外山.主+广而不疋此層中 的垂直方向上的厚度的二㈡電；係根據糊層 層的上表面處的-較高接雜度特：！表= 。因：二而降低該裝置的該崩潰電壓特性 另可由降A二開啟"電阻/崩潰電壓的數值，发 另了藉由降低该側向漂移區域 八 的悬祛仆，t尨你FB r 丁 I〜Ο雜木做進一步 度中-相當高的整體；積=雜持j此區域的厚 面可改善裝置中的飽合電流，直 ^ ^反向摻雜截 ’因為在該SQI層的下表面^ 源極跟隨者模式 ,lL a ^ 曲處的该相當重的摻雜度，將诰 成此層在該基板上的較少損耗 力。 貝耗因此而增加了飽合電流能 的ΪΪ1!面：該反向換雜截面係用於該側向漂移區域32 ，使得此區域的摻雜度由該氧化表面 Τ賴至“亥埋入絕緣層24的方向上增加…瞭解到 2明並不限於特定的摻雜度，截面，或摻雜劑 =範：中該摻雜劑為坤，而在該S0I層中的該 =面^由提供-濃度範圍來達到，該 絕緣層的約Κ2χ1〜，下降到相鄰於該表面鄰絕 、·彖&域的約8x1 〇15 cm·3的濃度。 :用習用的處理技術，如果不可能如前述地在s〇i層中 形成一反向摻雜截面’其通常為卜2微米厚度，例如那些
472342 五、發明說明（7) 用於高電壓裝置者， ^ ' ' 上可由離子植入來提供時：=需=的摻雜截面理論 約為丨Mev ’目前該層級無法到而 的能量，其大小 在任何狀況下皆报難利用光罩。° 〃運用的程度，因此 根據本發明，其在該SOI層提供一反向换 利=埋入絕緣層做為一極底;雜:面，其係 困難。 身在利用離子植入法達到-截面時的 此可藉由提供一習用的矽晶圓及所需要 ，例如以砷來摻雜該晶圓，而到達砷的固能二劑來達成 摻雜劑係在該氧化物成長期間，本ΐ自二f來形成，該 的氧化物。在形成該S0i層於 加入到該埋入 ，用來在該8〇1層令形成一巧電：：：絕緣層上之後 動地造成該推雜劑，例成如丨電由气 4=擴散猶賴 夕雜截面。δ月注意，如果使用在今亥 、° 雜截面，在該s〇I層的更高換雜區^上的一^•生推 過兮；5 6换蚀井 作匕Μ Y的该側向電荷將蓋 δ〇ΓΛ却 所以—反向摻雜截面將僅存在於該 田声°基本上’在該熱擴散處理期間所使用的 咖ΐ超過1 2 0 0 °c來達到所需要的反向摻雜截面。 今所2Γ可以瞭解到’所描述的方法的潛在好處是， 的話，即會很難以一有效率及經濟性的方法二中： 第12頁 472342 五、發明說明（8) 裝置製造中 反向摻雜截 以前述的 在一高電壓 參數，尤其 了一簡單並 當本發明 後，對本技 發明的精神 請案中，其 該元件的使 提出的其它 必要的一些處理步驟， 面來提供雙倍的負載量 方法，本發明提供一種 ’面電流的環境中達到 是崩潰電壓及”開啟"電 經濟的方法來製造這樣 已藉由幾種較佳具體實 藝的那些專業人士可以 或範圍之下進行型式及 必須瞭解到在一元件前 用’而該字眼"包含"並 元件或步驟的存在。 也可藉由形“需要的 〇 電晶體裝置ά士士毯 取I、、°構，能夠 高效能，而可增進運作 阻。此外，本發明提供 的一種裝置結構。 施例加以圖示及說明之 瞭解到，可在不背離本 細節上的改變。在此申 的"一"並不排除複數個 不排除那些已說明或已
第13頁 472342 圖式簡單說明 第14頁

Claims (1)

  1. 472342 六、申請專利範圍 1. 一種側向薄膜絕緣體上積矽（s ο I)裝置（2 〇 )，其包含 一半導體基板（2 2 )’ 一埋入在該基板上的絕緣層（2 4 )，及 在該埋入絕緣層上一 S Ο I層（2 6 )中的一側向電晶體裝置， 該電晶體裝置具有第一導電形式（2 8 )的一源極區域，其係 开> 成在相對於s亥弟一導電形式的一第二導電形式（3〇)的主 體區域内’該第一導電形式的側向漂移區域（32)係位在相 鄰於該主體區域，並形成淡摻雜汲極區域，一第一導電形 式（3 4 )的汲極接觸區域係被該側向漂移區域由該主體區域 側向地隔開，以及一閘極（36)，其係位在該主體區域的一 部伤之上，其中一通道區域在運作期間形成，並延伸到相 鄰於該主體區域的該側向漂移區域的一部份之上，而該閘 極係由一表面絕緣區域（38)而與該主體區域及漂移區域絕 緣，而該側向漂移區域（32)中至少一部份為反向摻雜截面 ，所以在相鄰於該埋入絕緣層（24)的該側向漂移區域的一 部份處的摻雜度，將會大於相鄰於該表面絕緣區域（38， 38A，38B)的該側向漂移區域的—部份處的摻雜度。 2. 如申明專利範圍第】項之側向薄膜絕緣體上積矽（) 及置’其中該反向摻雜截面包含一砷摻雜Μ。 /署如Γ!!利範圍第2項之㈣向薄膜絕“上積石夕⑽η 卢二：ί相鄰於該埋入絕緣層的該側向漂移區域的該 :二度會大於約50%的在相鄰於該表面絕緣區 或的遠側向漂移區域的該部份處的該摻雜产。 公.m側向薄膜絕緣體上積石夕⑽)又裝置（2〇)的方 去’包含一半導體基板（22)，一埋入在 工八在5亥基板上的絕緣層
    472342 六、申請專利範圍 (2 4 )’及在該埋入絕緣層上一 S ΟI層（2 6 )中的一侧向電晶 體裝置，該電晶體裝置具有第一導電形式（28)的一源極區 域’其係形成在相對於第一導電形式的一第二導電形式 (3 0 )的主體區域内’該第一導電形式的側向漂移區域（3 2 ) „--------------- 係位在相鄰於該主體區域’並形成淡摻雜沒極區域，一第 —導電形式（3 4 )的没極接觸區域係被該側向漂移區域由該 主體區域側向地隔開，以及一閘極（3 6 )，其係位在該主體 區域的一部份之上，其中一通道區域在運作期間形成，並 延伸到相鄰於該主體區域的該側向漂移區域的一部份之上 ，而該閘極係由一表面絕緣區域（38，38A，38B)而與該主 體區域及漂移區域絕緣，而該側向漂移區域（3 2)中至少一 部份為反向摻雜截面，所以在相鄰於該埋入絕緣層（24)的 =側向漂移區域的一部份處的摻雜度，將會大於相鄰於該 =絕緣區域（38，38A，38B)的該侧向漂移區域的一部份 處的摻雜度，該方法包含： 以 故π β Ϊ的摻雜劑來摻雜該半導體基板； 層包：該：雜Ϊ體基板來形成該埋入絕緣層，胃埋入絕緣 及 形成該SOI層在包含有 s亥摻雜劑的該埋入絕緣層上 劑到該S 0 I層，來形成 由該埋入絕 該反向摻雜截面 緣層熱擴散該摻雜 圍第4項之製造側向薄膜絕緣體上積矽 其中該半導體基板係以砷來摻雜。
    第16頁 5.如申請專利範 (s〇i)裝置的方法， 472342 六、申請專利範圍 (s^如申請專利範圍第5項之製造側向薄膜絕緣體上積矽 裝置的方法，其中該半導體基板係摻雜到砷的該固 態洛解限制。 ^如申請專利範圍第6項之製造侧向薄膜絕緣體上積矽 、、® 1 2 3 \裝置的方法’其中在相鄰於該埋入絕緣層的該側向 :移區域的忒部份處的該摻雜度會大於約5 0 %的在相鄰於 忒表面絕緣區域的該侧向漂移區域的該部份處的該摻雜度 8. 如申請專利範圍第4項之製造側向薄膜絕緣體上積矽 (SO I)裝置的方法’其中該摻雜劑係被用來製造該训I裝置 的至少一熱擴散循環來進行熱擴散。 9. 一種側向薄膜絕緣體上積矽（so I)裝置（2 〇 )，包含一 半導體基板（2 2 )，一埋入在該基板上的絕緣層（2 4 )，及在 汶埋入絕緣層上一 S 〇 I層（2 6 )中的一側向電晶體裝置，並 包含一淡摻雜側向區域（32 )，及在該側向區域上的一表面 絕緣區域（38，38A，38B)，該側向區域包含至少一部份的 反向摻雜截面’所以在相鄰於該埋入絕緣層（2 4)的該側向 區域（3 2 )的一部份處的摻雜度，將會大於相鄰於該表面絕 緣區域（38，38A，38B)的該侧向區域的一部份處的摻雜度
    第17頁 1 0. —種製造側向薄膜絕緣體上積矽（SO I)裝置（2 〇 )的方 2 法’包含一半導體基板（22)，一埋入在該基板上的絕緣層 3 (24) ’及在該埋入絕緣層上一SOI層（26)中的—側向裝置0 4 ’並包含一淡摻雜側向區域（3 2 )，及在該側向區域上的_ 472342 六、申請專利範圍 表面絕緣區域（38 ’38A，9βΐ3、 Α ΛΑ C；丄A A 38B) ’該側向區域包含至少一部 伤的反向摻雜載面，所w — ,0, , ^ M在相鄰於該埋入絕緣層（24 )的該 而怨缺广 處的摻雜度，將會大於相鄰於該表 雜南 ^β)的該側向區域的一部份處的摻 #度’該方法包含： Γ —所需t的摻雜劑來摻雜該半導體基板（22)，· 入绝緣\化5亥半、體基板來形成該埋入絕緣層(2 4 )，該埋 名緣層包含該摻雜劑； π s V y 形成該SOI層（26)在包合_ (24) L 牡已3有该摻雜劑的該埋入絕緣層 工，及 ，來开，:“里二邑换彖層(24)熱擴散該摻雜劑到該S01層(26) ^成該反向換雜截面。
    第18頁
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US6313489B1 (en) 2001-11-06
WO2001037346A1 (en) 2001-05-25
EP1147561A1 (en) 2001-10-24
KR100752799B1 (ko) 2007-08-29
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