TW456031B - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

Info

Publication number
TW456031B
TW456031B TW089116100A TW89116100A TW456031B TW 456031 B TW456031 B TW 456031B TW 089116100 A TW089116100 A TW 089116100A TW 89116100 A TW89116100 A TW 89116100A TW 456031 B TW456031 B TW 456031B
Authority
TW
Taiwan
Prior art keywords
signal
data
parallel
semiconductor integrated
integrated circuit
Prior art date
Application number
TW089116100A
Other languages
English (en)
Chinese (zh)
Inventor
Kazuyuki Kanezashi
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of TW456031B publication Critical patent/TW456031B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
TW089116100A 1999-12-09 2000-08-10 Semiconductor integrated circuit TW456031B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35054199A JP4071910B2 (ja) 1999-12-09 1999-12-09 半導体集積回路

Publications (1)

Publication Number Publication Date
TW456031B true TW456031B (en) 2001-09-21

Family

ID=18411196

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089116100A TW456031B (en) 1999-12-09 2000-08-10 Semiconductor integrated circuit

Country Status (3)

Country Link
US (2) US6343041B1 (enExample)
JP (1) JP4071910B2 (enExample)
TW (1) TW456031B (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6825698B2 (en) * 2001-08-29 2004-11-30 Altera Corporation Programmable high speed I/O interface
KR100477494B1 (ko) * 1995-01-31 2005-03-23 가부시끼가이샤 히다치 세이사꾸쇼 반도체 메모리 장치
JP4071910B2 (ja) * 1999-12-09 2008-04-02 富士通株式会社 半導体集積回路
JP3848038B2 (ja) * 2000-01-12 2006-11-22 株式会社日立製作所 半導体集積回路
JP4612139B2 (ja) * 2000-02-08 2011-01-12 富士通セミコンダクター株式会社 入力回路及びその入力回路を利用する半導体装置
US7120761B2 (en) * 2000-12-20 2006-10-10 Fujitsu Limited Multi-port memory based on DRAM core
US6549444B2 (en) * 2001-04-12 2003-04-15 Samsung Electronics Co., Ltd. Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data
JP3717912B2 (ja) * 2003-11-06 2005-11-16 沖電気工業株式会社 インタリーブ装置
DE102004014973B3 (de) * 2004-03-26 2005-11-03 Infineon Technologies Ag Parallel-Seriell-Umsetzer
JP2005326203A (ja) * 2004-05-13 2005-11-24 Matsushita Electric Ind Co Ltd 半導体集積回路の実速度検査方法
JP2006277872A (ja) * 2005-03-30 2006-10-12 Elpida Memory Inc 半導体記憶装置及びそのテスト方法
US20080288684A1 (en) * 2006-01-03 2008-11-20 Ellison Brandon J Design structure for an address translation device
US7444453B2 (en) * 2006-01-03 2008-10-28 International Business Machines Corporation Address translation device
JP5410075B2 (ja) * 2008-11-11 2014-02-05 ルネサスエレクトロニクス株式会社 半導体集積回路装置および遅延路の制御方法
JP2011108300A (ja) * 2009-11-13 2011-06-02 Elpida Memory Inc 半導体装置及びその制御方法並びに半導体装置を備えたデータ処理システム
KR101326628B1 (ko) * 2010-12-02 2013-11-07 주식회사 엘지화학 신규한 노칭 장치 및 이를 사용하여 생산되는 이차전지
JP6170596B1 (ja) * 2016-06-15 2017-07-26 ウィンボンド エレクトロニクス コーポレーション 半導体装置
US10170166B1 (en) * 2017-09-08 2019-01-01 Winbond Electronics Corp. Data transmission apparatus for memory and data transmission method thereof
US10366742B1 (en) * 2018-02-07 2019-07-30 Micron Technology, Inc. Memory device parallelizer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2376572A1 (fr) * 1976-12-30 1978-07-28 Roche Alain Circuits de conversion serie-parallele et de multiplexage ou de conversion parallele-serie et de demultiplexage pour des multiplex numeriques
JPS59221741A (ja) 1983-05-31 1984-12-13 Sanyo Electric Co Ltd 記憶用半導体装置
JPS6282417A (ja) 1985-10-07 1987-04-15 Casio Comput Co Ltd スイツチ検出回路
JP2000067577A (ja) * 1998-06-10 2000-03-03 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2000163965A (ja) * 1998-11-27 2000-06-16 Mitsubishi Electric Corp 同期型半導体記憶装置
JP4071910B2 (ja) * 1999-12-09 2008-04-02 富士通株式会社 半導体集積回路

Also Published As

Publication number Publication date
US20020057614A1 (en) 2002-05-16
US6438054B1 (en) 2002-08-20
US6343041B1 (en) 2002-01-29
JP4071910B2 (ja) 2008-04-02
JP2001167575A (ja) 2001-06-22

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