TW436969B - Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product - Google Patents

Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product Download PDF

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TW436969B
TW436969B TW088118743A TW88118743A TW436969B TW 436969 B TW436969 B TW 436969B TW 088118743 A TW088118743 A TW 088118743A TW 88118743 A TW88118743 A TW 88118743A TW 436969 B TW436969 B TW 436969B
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Atul Ajmera
Devendra K Sadana
Dominic J Schepis
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
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    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283Lateral isolation by refilling of trenches with dielectric material

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Description

經濟部智慧財產局員工消費合作社印製 4369 6 9 A7 _______B7__ 五、發明說明(1 ) 技術領域 本發明係關於一種製造半導體裝置之方法,特別係關於 一種形成具有自我對準溝槽之圖案化SOI層之方法。 發明背景 絕緣體外延矽(SOI)結構包含一層嵌置絕緣層其係由矽基 材電隔離矽層。SOI結構並未經常佔據矽基材整個表面: 反而SOI結構偶爾僅占有矽基材之一部分。對準SOI結構區 俗稱SOI區,SOI結構外側區俗稱突塊區。
具有一突塊區及一SOI區的半導體裝置具有突塊區絕佳 結晶化及SOI區絕佳元件隔離優點。例如邏輯記憶電路較 佳形成於突塊元件區,而高性能邏輯電路較佳形成於S〇I 區。因此希望半導體裝置具有B比鄰同一晶圓的SOI區及突 塊碎區。 曾經開發多種技術來形成SOI區及突塊區。一種最佳製 造技術爲離子植入’包括將高能離子植入實心面而形成嵌 置層。由於植入攙雜劑通常非位於適當晶格位置且大半爲 鈍性,故常使用高溫退火製程來修復晶體損害及電激勵攙 雜劑。氧植入矽通常爲建立S0I基材的較佳方法。藉植入 氧(SIMOX)方法分開例如可用於極大型積體(VLSI)裝置。 不幸經罩蓋或圖案化的離子植入於半導體基材產生一部 分植入區稱作過渡區。過渡區形成於接受完整離子植體劑 量該區與屏蔽不受植入區稱作罩蓋區之該區間。由於部分 劑量結果,過渡區有高度缺陷,含有晶體瑕疵,其可能傳 播至半導體梦層其他區。 本紙張尺度適用中國國家標準(CNS)A4規格(210 297公釐) (請先閱讀背面之注意事項再填寫本頁) - I I ! I I 訂·--—I!:. 卡迥 1 COJSrs)A^^,茶(210 X 297 嫜掩汾择® PSOI蚵 渰寐痒s -ftl噼獬羚科澉 Λ裨象。免(喻鉍忽) 硝轉Η龄采Λ择琴咏辦 >'斯。KL a w a i ^一 钿.:^ fer X,νϋίίε.漆裨Λσ參岑 TMh ί 淥知 r β ^ ^ ρ Λ^ f u,^ Lr o & wsf ^ ^ l· "萍寐KLawai $迤碑聲φ ,碟
Icawpi^. Jt 酒如令J 铖-4,sws>, 82^0隸弊 s ——
3——A LP。wt. S蚪i 3潑旃雜 vwr Μ ο Η ^r β, L^r ^ ^30--p金.J嶠舟聲滿餐通务3 J ο χ n e r J4 画如斗α 被 5,3<54-,soo ^ 5,5 4-00, 1 私9 ν^ u^ar ο U^Y 辦 ^wr ® S ^f u J。:y n e f S 厨S 01 顾 顾。jHs J o y η o r ^一^ ^· S ΟI 顾 择® s _其。縣课Joxnel-海s 3泖At,南錄 S QI顾p 择®。贷JOYner-爺ί ΐ采条W蘇雖雜诈击汾择顾S忠s β Mr ΰ ^ β ^ΜΗ3Λ hr '^ kr ^ s 淋薄努漆 4 $ ΰ 憐w
Hanigpwa^:_ 批迥♦斗.J 铖 5,7 仁 Ο,090 备®忽耻画丨_珠卜 ^ ί ft ^ ΗΡΡ^^Ρ»>Ρ44 f ^β, 3 1 ^ f ^Γ ^ SOI ® ρ汾择® S雜m。民論斗>,% ΜΓ 。T a n i g a -W a 〇tt* 雜 N ^ p 4 ^ ^ Λ^- £f νί ® ^ ^s- W ο 耻週如斗_J铖私6雜择s I雜 4-¾^ WH^OX Mown# s 0 4 揉蘇忽 ΑΎ J^n
薄珠斗麻揉SOI ®知 挪义 3险神费麥命W 3 1驷8l·濟膝喻 P含涉令秦p酒^Λσ降 β ^ ^ J^S-AWS S
ο fi. 辨 u®^ ί, m- 0 ^β, f OH 卜·------------ 4369 6 9 A7 B7 五、發明說明(3 ) 多晶矽而形成單晶。然後SOI裝置建構於此層上。最終結 構爲非平面,如Ahn敎示的結構帶有此種結構特有的問 題。此外,Kawai所述方法不合實際,原因在於對多晶矽 之再結晶控制不良故。
Moslehi之美國專利第5,143,862號敎示經由選擇性晶膜外 延生長製造SOI晶圓。Moslehi敎示寬溝槽,藉CVD沉積嵌 置氧化物,由溝槽側壁去除氧化物,然後使用選擇性晶膜 外延生長而生長矽於氧化物區上。然後Moslehi藉由形成側 壁於晶膜外延罩蓋上隔開各區,持續生長妙至表面,及最 終移開側壁’及蝕刻以電介質填補的溝槽來隔離裝置。該 方法未去除於過渡相的受損區。實際上溝槽並未延伸超過 嵌置氧化物層。 日立公司之日本專利第06334147號敎示將基材劃分爲 SOI區及突塊區’以及將不同型電路置於各區來獲得各區 的特殊優點。由於堆疊電容器升高高於突塊矽面,形成 SOI區,其升高而使最終晶片相對於各區爲平坦。顯然頂 矽及嵌置氧化物由SOI結構去除留下突塊基材區作爲記憶 單元。如此該結構爲混合基材具有記憶體於突塊及S◦;[作 爲邏輯電路,及具有約略平坦面。
Sun之美國專利第5,399,507號也説明一種於單一基材上 形成突瑰區及SOI區之方法及結構。該方法係始於全面性 SOI(藉SIMOX形成)及然後蝕刻去除矽及嵌置基材層向下 至碎基材。於此方法步驟,結構類似Ahn揭示之結構,结 構具有暴露突塊矽區於與SOI區頂部不同高度。但Sun更進 -6 - 本紙張尺度適用t國困家標準(CNS)A4規格(210 X 297公釐) ί請先閱讀背面之注意事項再填寫本頁)
i I 11 11 訂------11 I 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 ^ 436969 A7 --- —_B7_____ 五、發明說明(4 ) —步將侧壁置於蝕刻開口,然後使用矽選擇性晶膜外延生 長’其爲單晶矽的延續。晶膜外延生長持續至S0I區表面 使該區變成平面。Sun也使用平面化步驟來確保二區係在 同一平面上。Sun無法改良圖案化植體或去除任何存在的 瑕戒區。替代具趙例中,由Sun敎示的圖案化SOI植體不具 有任何隔離’ Sun也未曾指示需要任何隔離。此外無法自 我對準隔離與罩蓋結構β 建構SOI基材之離子植入方法之缺陷顯示仍然需要去除 高度瑕疵過渡區,該區接受離子植體部分劑量。爲了克服 離子植入方法的缺點提供新穎方法。本發明之目的係提供 形成圖案化SOI層之方法而未形成高度瑕疵過渡區。 發明概述 爲了達成此等及其他目的以及鑑於其用途,本發明提供 —種形成平面SOI基材之方法,該基材包含一圖案化S0i區 及一突塊區,其中該基材不含過渡瑕疵。該方法包含藉由 於SOI區與突塊區間形成毗鄰SOI區的自我對準溝槽而去除 過渡瑕病1。 溝槽的自我對準方式係經由形成嵌置氧化矽區於矽基材 獲知,該基材具有一氧化硬表層及—包含氮化碎或多晶石夕 於氧化矽表層之表面保護層,該方法係經由: (a) 於表面保護層上形成一罩蓋區,該區有一罩蓋區頂面 及侧壁來罩蓋基材之嵌置氧化矽區以外部分; (b) 沉積一側壁蓋層選自主要由氮化矽及氧化矽-氮化砂 複合體於罩蓋區側壁之側壁蓋層,側壁蓋層也延伸於表面 本纸張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) f n n t n n* 一-nJ_ I t— I (請先閱讀背面之注意事項再填寫本頁) 43696 9 A7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 Μ 五、發明說明( 保護層部分上; ⑷去除非位在$蓋層及㈣蓋層τ方的表面保護層來暴 露氧化矽表層部分; (d) 將氧離子植入矽基材區於氧化矽表層暴露部分下方來 形成具有—頂面的嵌置氧化物層; (e) 退火氧化矽表層暴露部分而形成厚的表面氧化矽區及 退火嵌置氧化物層; ⑴移開側壁蓋層及㈣蓋層下方的表面保護層來暴露基 材; (g)形成一溝槽於基材之延伸介於罩蓋側壁與一厚表面氧 化矽層間之暴露部分,以及於基材延伸至至少嵌置氧化物 層的頂面: 00移開罩蓋層;以及 (i)以填補材料塡補溝槽。 需瞭解前文概略説明及後文細節説明僅供舉例説明本發 明之用而絕非限制性β 圖式之簡單説明 由後文詳細説明連同附圖一起研讀將最爲明瞭本發明。 根據一般實務強調附圖之各種結構特徵非照比例繪製。相 反地,各種結構特徵的尺寸可任意放大縮小以求清晰。附 圖含括下列各圖: 圓ί以不意代表圖顯示一元件,包含矽基材、表面氧化 矽層及表面保護層,基材有一罩蓋層 '一保護層及一側壁 蓋層沉積於基材上; ----I 1 I I I I ! I I--—ί — 訂· — A {請先閱讀背面之注意事項再填窝本頁) 8- 5 436969 缦濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(6 ) 囷2以示意代表圖顯示保護層被去除後之圖1元件,表面 保護層被部分去除且形成嵌置氧化物層; 圖3以示意代表圖顯示圖2元件,其中部分表面氧化矽層 及嵌置乳化物層已經被退火; 圖4以示意代表圖顯示圖3元件,其中側壁蓋層及部分表 面氧化矽層及部分表面保護層已經被去除; 圖5以示意代表圖顯示形成溝槽後之圖4元件;以及 圖6以示意代表圖顯示圖5元件,其中罩蓋層已經被去 除’溝槽已經被填補,及元件已經被平面化。 發明之詳細説明 其次將參照附圖舉例説明本發明,其中類似的编號表示 附圖中的相同元件。此等附圖僅供舉例説明之用而非限制 性’俾便輔助解説本發明之方法。 始於囷1,實施本發明方法之第一步驟涉及獲得矽基材 10具有表面氧化矽層12由表面保護層14遮蓋。表面保護 層14通常爲氮化矽或多晶矽層。此等層形成於矽基材上表 示眾所周知的技術而對本發明而言並無特殊限制。 如圖1所示,首先於表面保護層14上沉積罩蓋16。罩蓋 1 6典型係沉積爲表面保護層1 4上的連績層,然後經圖案 化及姓刻形成個別罩蓋於完成後元件最終突塊區的輪廓。 較佳具體例中’罩蓋16包含四乙氧矽烷(TE〇S)。氮化矽 層可選擇性沉積於罩蓋16之暴露頂面上,形成罩蓋保護氮 化矽層1 9。 罩蓋1 6具有暴露側壁1 7,其次以侧壁蓋層1 8覆蓋。側 -9 * 本紙張尺度適财關家標準(CNS)A4規g (21Q χ 297公爱〉 — ί ^ ---- I I I 1 訂---------^ (請先閱讀背面之注意事項再填寫本頁) 4369 6 9 A7
五、發明說明(7 ) 經濟部智懸財^局貝工消費合作社印製 壁蓋層18較佳包含氮化砍或氧化矽與氮化矽的複合物。較 佳側壁蓋層1 8及罩蓋保護層1 9爲相同材料製成。侧壁蓋 層1 8之形成方式係經由沉積氮化矽或氧化矽_氮化矽層來 填補HT比鄰罩蓋1 6間足空間’然後圖案化及蝕刻沉積層而形 成侧壁蓋層1 8於罩蓋1 6之側壁1 7上。 較佳具體例中,表面氧化矽層12厚約5〇埃至約2〇〇埃’ 表面保護層14厚度爲約500埃至約1500埃,及罩蓋16厚度 爲約500埃至約5000埃。罩蓋側壁蓋層is爲具有變化厚^ 的推拔形狀,如圖2所示。沿罩蓋側壁蓋層18毗鄰表面= 護層14底部量測厚度,罩蓋側壁蓋層丨8厚度於由氮化矽 組成時較佳爲约1200埃至約2500埃,由氧化矽.氮化碎複 合物組成時爲約1000埃至約2500埃。 本發明方法之次一步驟涉及去除暴露面保護層14之非位 在罩蓋1 6及罩蓋侧壁蓋層1 8下方部分,遵照此步報存在 的結構説明於圖2。如本圖所示,去除表面保護層14b比鄰 侧壁蓋層1 8之暴露部分暴露出下方表面氧化矽層1 2部分 遵照此步驟,氧離子植入表面氧化矽層1 2之暴露部 分13。罩蓋16及罩蓋側壁蓋層18屏蔽離子植入表面氧 化矽層12及矽基材10之於罩蓋16及罩蓋側壁蓋層18下 方區。離子植入爲一種方法,其中被激勵的帶電荷原子或 分子直接被引進基材如矽基材》較佳約1 X 1〇18/平方厘米 氧離子係於約200 keV植入。 離子植入步驟產生介於接受全離子劑量22之區與不接受 -10- 本紙張尺度適用中國國家標準(CNS)A4規格(21D x 297公笼) ------------^·------ - 訂-------^ (請先閱讀背面之注意事項再填寫本頁) 4369 6 9 A7 五、發明說明(_ 任何離子劑量24之區間之過渡區2〇(表面氧化矽層12及矽 基材10之由罩蓋層16及罩蓋側壁蓋層18遮蔽部分)。嵌置 氧化物層26具有頂面25及底面27,係形成於接受完整離 子劑量22之該區内部。 較佳具體例中,嵌置氧化物層26及表面氧化矽層12於 離子植入步驟後被退火。另外,退火嵌置氧化物層26及表 面氧化矽層1 2之步驟係出現於隨後各步驟之後,容後詳 述,隨後步驟包括去除側壁蓋層18及罩蓋層16,以及去 除表面保護層14之暴露部分13,而係出現於填補溝槽步 驟之前。較佳具體例中,嵌置氧化物層26之厚度至少爲約 50埃。 其次退火嵌置氧化物層26。亦於離子植入後,表面氧化 矽區12被退火而形成厚表面氧化矽層12a,如圖3所示。厚 表面氧化矽層12a之預定厚度爲約1〇〇〇埃至約3〇〇〇埃。於 退火步驟形成厚表面氧化矽區12a後,若未達厚表面氧化 矽區12a之預定厚度,.則厚表面氧化矽區12a可選擇性於約 1000 C溫度使用乾氧氣加熱氧化來增加厚度。 退火及選擇性氧化步驟後接著去除側壁蓋層18,下方表 面保護層14,及介於罩蓋16與厚表面氧化矽層12a間之表 面氧化矽層1 2,如圖4所示。側壁蓋層丨8及下方表面保護 層1 4之去除較佳係藉乾触刻進行。本發明之溝槽係形成於 此一介於罩蓋側壁1 7與厚表面氧化矽層1 8間的空間。 圖5顯示其中形成自我對準溝槽2 8之元件侧视圖。溝槽 28自我對準於介於厚表面氧化矽區i2a與罩蓋側壁間之 -11 - 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公爱) (請先閱讀背面之注意事項再填寫本頁) 裝 if---- - 訂---ί I I--*"· 經濟部智慧財產局員工消費合作社印製 4369 6 9 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(9 ) 過渡區2 0。溝槽2 8係使用蝕刻技術形成,並延伸於♦基 材至至少嵌置氧化物層26頂面25。較佳具體例中,溝槽 2 8延伸至約嵌置氧化物層2 6底面2 7,如圖5舉例說明。如 此蚀刻溝槽28去除過渡區20,其未接納全離子植體。較 佳具體例中,溝槽28係使用乾蝕刻技術蝕刻,例如反應性 離子姓刻(RIE)或電衆改良型姑刻。 一旦溝槽28已經形成,其次使用填補材料3〇塡補至至 少表面保護層14的暴露部34,元件於去除罩蓋16後被平 面化,如圖6所示。較佳具體例中,填補材料3 〇爲氧化物 如四乙氧矽烷(TEOS)。於溝槽填補後,填補溝槽表面 32,表面氧化矽層12暴露部分13,及表面保護層M暴露 部分34被平面化,使用表面保護層14作爲擋止層。較佳 具體例中,平面化係藉化學-機械拋光(CMP)處理進行。 於平面化後,應用業界已知步驟來完成規則STI(淺溝槽 隔離)處理。此外,本發明方法各步驟係用於突塊STI處 理。 含括下列實例來更清晰驗證本發明之整體性質。本實例 爲舉例説明而非限制本發明。 實例1 表面氧化矽層12沉積於<100>矽基材1〇上。然後氮化矽 層(表面保護層14)沉積於表面氡化矽層12上。5〇〇〇埃 TEOS層係沉積於表面保護層i 4上。丁£〇§層使用習知微影 術圖案化並蝕刻形成TEOS革蓋1 6。氮化矽層丨9係沉積於 TEOS罩蓋1 6之侧壁1 7上,且經蝕刻形成側壁蓋層丨8。表 -12- 本紙張疋度適用中國國家標準(CNS)l4規格(21〇 x797公餐: (請先閱讀背面之注意事項再填寫本頁) -11--- f 訂--------- 4369 6 9 A7 B7 五、發明說明(10) 面保護層1 4之未位於罩蓋1 6及側壁蓋層1 8下方部分係使 用微影術及蝕刻暴露出表面氧化矽層12部分13而被去 除。 進行SIMOX氧植入,將氧離子植入未由TEOS罩蓋16及 側壁蓋層18保護區且形成喪置氧化物層26。然後退火嵌 置氧化物層26及表面氧化矽層12之暴露部分13 ;退火表 面氧化矽層12形成厚表面氧化矽區12a之暴露部分13。其 次加熱氧化厚表面氧化矽區12a,增厚厚表面氧化矽區i2a 至約2000埃厚度。然後去除側壁蓋層1 8,去除方式係藉熱 磷酸蝕刻接著藉短緩衝氫氟酸(BHF)浸潰而由TEOS侧壁區 去除墊氧化物,留下未經保護區介於罩蓋16與厚表面氧化 矽區12a間。 其次於過渡區2 0蝕刻溝槽2 8至毗鄰嵌置氧化矽層2 6底 面27之深度,對準於厚表面氧化硬區i2a與TEOS罩蓋1 6 間。其次去除罩蓋1 6,使用BHF長條來由溝槽28去除罩蓋 氧化物,然後進行溝槽的再度氧化。溝槽2 8藉化學蒸氣沉 積(CVD)方法以TEOS填補。然後化學-機械拋光(CMp)方法 用來平面化最終結構且使用剩餘氮化物作爲蝕刻擋止層。 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁w 雖然前文參照某些特定具體例舉例説明,但雖言如此本 發明絕非意圖限於所示細節。反而可於申請專利範園之相 當範圍内且未悖離本發明之精髓就細節上做多種修改。 -13- 本紙張尺度適用中國國家標準(CNS>A4規格(210 * 297公釐〉

Claims (1)

  1. A8B8C8D8 d369 6 9 六、申請專利範圍 1_ 一種形成平面絕緣體外延矽(SC)I)基材之方法,該基材包 含一具有氧化物層及一突塊區之圖案化S〇I區,其中該 基材不含過渡瑕疵,該方法包含經由形成毗鄰於S〇I區 與突塊區之間之S0I區的自我對準溝槽而去除過渡瑕 戚。 2 _如申請專利範圍第1項之方法,其中該突塊區包含—具 有側壁之軍蓋》 3. 如申請專利範圍第2項之方法,其中該罩蓋具有之厚度 爲約500埃至約5〇〇〇埃。 4. 如申請專利範圍第3項之方法,其中該溝槽係形成爲毗 鄰於SOI區之氧化物層且她鄰突塊區之罩蓋。 5. 如申請專利範圍第4項之方法,其進一步包含於形成溝 槽前沉積側壁蓋層於罩蓋侧壁上之步驟。 6. 如申請專利範圍第5項之方法’其進一步包含將氧離子 植入SOI區之步騍,形成一嵌置氧化物層,其中該罩蓋 及側壁蓋層屏蔽離子植入突塊區。 7·如申請專利範圍第6項之方法,其進一步包含於植入氧 離子後而於形成溝槽前移開側壁蓋層之步騍。 8·如申請專利範圍第7項之方法’其中該嵌置氧化物層具 有之厚度至少爲約5 0埃。 9. 一種於矽基材形成嵌置矽氧化物區之方法,該基材具有 一氧化矽表層及一表面保護層,該保護層包含氮化矽或 多晶矽且位於氧化矽表層上,該方法包含下列步膝: (a)於表面保護層上形成一罩蓋區,該區有一罩蓋區頂 •14- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公楚) {請先M讀背面之注意事項再填寫本頁) b li If Ϊ 一S°J* n i I 經濟部智慧財產局員工消費合作社印製 4369 6 9 六、申請專利範圍 面及側壁以罩蓋基材之嵌置氧化梦區以外部分; <請先閱讀背面之注意事項再填寫本頁) 一⑻沉積選自主要由氮化矽及氧化矽-氮化;複合物之 一侧壁蓋層於罩蓋區側壁之側壁蓋 於表面保護層部分上;側壁i層也延伸 ⑷去除非位在罩蓋層及側壁蓋層下方的表面保護層來 暴露氧化梦表層部分; ⑷將氧離子植人$基材區於氧切表層暴露部分下方 來形成具有一頂面的嵌置氧化物層; (e)退火氧化矽表層暴露部分而形成厚的表面氧化矽區 及退火嵌置氧化物層; (0移開側壁蓋層及側壁蓋層下方的表面保護層來暴露 基材; (g) 形成一溝槽於延伸於罩蓋側壁與—厚表面氧化矽層 之間基材之暴露部分,且於基材延伸至至少嵌置氧化物 層的頂面; (h) 移開罩蓋層;以及 (i) 以填補材料塡補溝槽。 10.如申請專利範圍第9項之方法,其中該退火嵌置氧化物 層之步驟係於形成溝槽後進行。 經濟部智慧財產局員工消貲合作社印製 Π·如申請專利範園第9項之方法,其中該罩蓋爲四乙氧矽 烷。 12. 如申請專利範圍第丨丨項之方法,其中該軍蓋之厚度爲约 500埃至約1〇〇〇埃。 13. 如申請專利範圍第9項之方法,其中氮化矽層係於步騍 -15- 本紙張尺度適用中國國家標準(CNS)A4規格(210 * 297公釐) 4 3 6 9 6 9 as B8 C8 ——______D8 六、申請專利範圍 (b)之前沉積於罩蓋頂面上。 如申請專利範圍第9項之方法,其中該表面氧化矽層之 厚度爲約50埃至約200埃。 15. 如申請專利範圍第9項之方法,其中該表面保護層之厚 度係爲約500埃至約1500埃。 16. 如申請專利範圍第9項之方法,其中該側壁蓋層之厚度 係爲約1200埃至約2500埃。 17. 如申請專利範圍第9項之方法,其中該植入步驟包含於 約200 keV下植入約1 X 1〇18/平方厘米氧離子。 18. 如申請專利範圍第9項之方法,其中該厚表面氧化矽區 之厚度係爲約500埃至約3000埃。 19. 如申請專利範圍第9項之方法’其進一步包含於步驟(e) 之後加熱氧化表面氧化碎層暴露部分之步驟。 20. 如申請專利範圍第9項之方法,其中該於步驟(g)形成的 溝槽係延伸至約略嵌置氧化物層底面。 21. —種平面絕緣體外延矽基材,包含一圖案化SOI區及一 不含過渡瑕疵之突塊區,其中該等過渡瑕疵係藉形成一 毗鄰於SOI區與突塊區之間的SOI區之自我對準溝槽而去 除。 ------ ----I--裝----i — 訂----I--— Ά (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -16 - 本紙張尺度適用令國國家標準(CNS)A4規格(210 X 297公釐〉
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