TW412787B - Single step process for blanket-selective CVD aluminum deposition - Google Patents

Single step process for blanket-selective CVD aluminum deposition Download PDF

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TW412787B
TW412787B TW085112815A TW85112815A TW412787B TW 412787 B TW412787 B TW 412787B TW 085112815 A TW085112815 A TW 085112815A TW 85112815 A TW85112815 A TW 85112815A TW 412787 B TW412787 B TW 412787B
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layer
nucleation layer
cvd
nucleation
metal
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Roderick C Mosely
Ted Tie Guo
Liang-Yuh Chen
Mehul Naik
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Applied Materials Inc
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

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Description

412787 B7 五、發明說明（1 ) 本案為1995年11月21日提出申請之名稱“低溫積體金 屬化方法及裝置”之審查中之美國申請案第〇8/561，6〇5號 之繼績部分申請案。 發明領域 本發明係關於半導體裝置製造用之金屬化方法及裝 置》特別本發明係關於於絕緣層選擇性金屬化孔眼，而介 於導電層間形成不含空隙之互連，包含於高縱橫比次半微 米用途之孔眼，例如接觸孔或貫穿孔，同時較佳也於絕緣 層上形成一層範覆層。 相關技術背景 訂 次半微米多階金屬化為下一代極大型積體化（VLSI)之 關鍵技術之一。處於此種技術核心的多階互連，須要於高 縱橫此孔眼形成互連紋路的平面化，孔眼包含接觸孔、貫 穿孔、線路、或其它紋路。可靠的形成此等互連紋路對VLSI 之成功而言極為要緊’且對工業基片及小晶片之線路密度 及品質増高之未來，努力上也極為重要。 兩種藉化學蒸氣沈積（CVD)沈積鋁（A1)之習知方法包 含氈覆法及選擇法。CVD方法典型起包括於化學蒸氣成 份接觸基片上的“成核位置，，時發生薄膜層沈積。組分附 接於成核位置’形成沈積物表面，於該上方繼續進行沈積。 氈覆CVD方法典型地將薄膜沈積於基片之全體暴露面上， 包含孔眼之側壁及底面，以及沈積於場上，原因為全體表 面皆作為成核層之故。選擇法典型地僅將薄膜沈積於提供 於基片表面上的選擇性成核表面上β -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 五、 發明說明（ 氈覆CVD金屬沈積，例如cVD A1，此處金屬膜係沈 積於基片之整體暴露面上，通常要求存在有導電成核層。 於氈覆CVD過程中，沈積的薄金屬膜通常服貼且提供絕 佳階梯覆蓋，亦即任何孔眼側邊及底面上，各層厚度均勻 延伸入基片的整體表面’即使孔眼幾何極小亦如此。因此 鋁之CVD為常用來填補孔眼之方法，但使用氈覆CVD方 法填補高縱橫比（高度對寬度比大於2: 孔眼而形成貫穿 孔或接觸孔有兩大困難。第一，CVD薄膜於孔眼各侧上 生長且於構成貫穿孔及接觸孔的填補孔眼内形成空隙或餘 匙孔，結果導致裝置受損。孔眼内部形成空隙俗稱頂冠， 原因為沈積層向上向外與孔眼的上角隅生長，並於孔眼完 全填補之前於此位置架橋。第二項困難，成核層必須沈積 於孔眼壁上俾確保CVD層沈積其上，進一步縮小孔眼密 度’因而增加不含空隙之孔眼填補的困難。 晚近穿透型電子顯微術（TEM)資料顯示’即使標準 電子試驗互連資料未證實存在有空隙，但空隙確實存在於 許多藉CVD A1方法形成的互連。參照第i圖，TEM相片 顯示以CVDA1填補的〇.45微米貫穿孔之剖面影像。影像 明白指出，沈積於貫穿孔結構的金屬層内存在有空隙。須 了解此種空隙極難以藉一般剖面標準電子顯微術之sem 技術檢測，原因為於切片製品的機械拋光過程中，軟性鋁 内發生若干變形。此外，導電試驗進行多：欠，也無法檢測 結構異常例如空隙’原因為金屬至少通過孔眼的一部分形 成架橋層U雖然-般導電試驗層呈陽性，但其中含有 •5· 本纸張尺度中國國家標準（CNS)A4規^(210 x 297公髮· ^--------^---------^ (請先閲讀背面之注意事項再填寫本頁) 412787 Α7 Β7 五、發明說明（3 ) 空隙的接觸孔之傳導隨著時間之經過，可能損害積體電路 裝置的完整性。 於基片上形成多種C VD A1層之TEM研究指出，空隙 典型地以鑰匙孔形式存在’其中貫穿孔頂部於完全填滿前 密封’亦即頂冠。雖然於低溫’於高縱橫比孔眼，典型地 沈積薄而服貼的CVD A1層，而形成接觸孔及貫穿孔；但 完全填補孔眼之連續CVD沈積典型地導致生成空隙。徹底 進行研究，專注於藉修改CVD製程步驟及參數來去除金屬 層之空隙。 選擇性CVD A1沈積係基於：CVD A1前驅氣體分解而 提供沈積膜通常需要來自導電成核膜的電子來源。根據習 知選擇性C VD A1沈積法’ A1將於孔眼底部生長，此處， 來自下方導電層的金屬膜或掺雜矽皆暴露出，但不可於場 上介電材料生長而形成孔眼壁。不似介電孔眼壁，下方金 屬膜及摻雜矽皆具有導電性’可供應Α1前驅氣體分解所需 電子’結果導致Α1沈積。經由選擇性沈積所得結果為孔内 CVD Α1「上下顛倒」生長’可填補極小直徑（小於〇 25 Am)高縱橫比（大於5 : 〇貫穿孔或接觸孔開口。
參考第2圖’積體電路結構1〇之示意圖顯示於貫穿孔 14形成的金屬互連選擇性被導電件18成核，並朝向介電層 16表面20均勻向上生長。然而，於選擇性沈積法之真正實 務中於介電層表面及孔眼側壁上幾乎經常有瑕疲，提供自 由電子’如此也作為CVD A1生長的成核位置，引起表面2〇 及孔眼壁上形成不期望的結節。注意，於習知選擇性CVD (請先閱讀背面之注意事項再填寫本頁) 1 I 棚^· ί ! I —-^---1.- I . -6· A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 方法填補貫穿孔或接觸孔14之過程中，結節12係藉選擇性 喪失而於介電層上形成。曾經使用多種方法來減少可能導 致結節生成的選擇性損失’特別為選擇性豸（w)技術。 此等方法包含例如預先調理晶圓表面及化學機械拋光 (CMP)表面，來去除於選擇性沈積過程中已經於晶圓表 面20上形成的結_ i2。然而’此等方法使形成所須電路結 構的製程步料複雜，且顯著提高積體電路製造方法成 本》類似地，某些步驟例如CMp無法到達孔眼侧壁。此 外，整體方法之步驟增加，可能增加於形成結構出現瑕疵 的可能性。 因此，仍須要有一種不含空隙地填補孔眼，特別高縱 橫比次四分之一微米寬孔眼，供形成接觸孔及貫穿孔之金 屬化方法。特別希望有一種簡單方法，所須製程步驟較少 即可完成選擇性CVD A1沈積，而形成貫穿孔及接觸孔， 不會因場之選擇性喪失引發結節生成。也希望有一種可供 於貫穿孔或接觸孔之選擇性CVD A1沈積及場之覆蓋cVD A1沈積二者之單一步驟方法。 發明概沭 本發明提供一種於具有一層介電層覆蓋至少第一導電 件之基片上形成互連之方法及裝置，包括下列步驟：於介 電表面上形成一層成核層，蝕刻孔眼通過成核層及介電層 而形成一個底面暴露出導電件的一部分，及藉化學蒸氣沈 積選擇性沈積金屬於互連底面及成核層上。 本發明之另一態樣，係提供一種於選擇性化學蒸 -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁)
412787
積金屬於第二表面之過程中，防止於第一表面上形成結節 之方:¾:及裝置’該方法包括於第—表面上形成—層成核層 而提供沈積膜大體均勻生長之步驟。 本發明之又另-態樣，係提供—種於基片之選擇部分 t尤積金屬膜之方法及裝置，該方法包括於基片之特選部 77上提供導電成核層，及藉化學蒸氣沈積於成核層上選擇 性沈積金屬膜之步驟。 1_A.之簡單說明 、因此可了解達成本發明之前述特點、優點及目的之方 式細郎，前文摘述之本發明經由參照附圖舉例說明之具體 例將作更特定描述。 但須注意附圖僅舉例說明本發明之典型具體例，因此 不得視為限制其範圍，本發明亦許可其它同等有效的具體 例0 第1圖為穿透型電子顯微術相片，顯示其中含有空隙 之半導趙基片貫穿孔之剖面圊； 第2圖為示意圖顯示於習知選擇性化學蒸氣沈積方法 中經由選擇性喪失而形成結節； 第3圖為成層結構之剖面圊，該結構包含一層介電層 32及一層成核層依次於導電件或導電層上形成； 第4圊為蝕刻入第3囷之結構之成核層及介電層之貫 穿孔或接觸孔之剖面圖； 第5圖為於第4圊之結構上形成的不含空隙的金屬互 連及氈覆金屬層之剖面圖； -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）
— — — — — — — — 裝· — — I ————訂- — — — ·^· <請先閱讀背面之注意事項再填寫本頁) 〜.•潼二上五、發明說明（6 ) A7 B7
Vs*, jA..， 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 第6圖為適合根據本發明依序金屬化之積體處理系 統；及 第7圖為供應氣體至第6圖之系統之cvd氣箱輸送系 統之示意流程圖。 較佳具體例之詳細說明 本發明提供一種於小幾何尺寸中，例如將形成貫穿孔 或接觸孔之小孔眼内部，選擇性沈積材料之簡單方法及裝 置’其可消除場之選擇性損失。此種方法包括下列步鄉： ⑴於場上沈積一層薄導電層較佳氮化鈦（TiN)層作為成 核層，⑵加圖樣及蝕刻成核層及介電層而形成具有小幾何 之孔眼；及⑶沈積CVD金屬於結構上而提供金屬與小幾何 内部選擇性成長，較佳於場上同時均勻地生長。如此，本 發明提供一種以較少處理步驟、以無空隙方式填補小幾何 並可防止場上形成結節之方法及裝置。 參照第3圖顯示層狀結構30之剖面圖，層狀結構包含 —層介電層32及一層成核層34，依序於導電件或層36上形 成。導電件36可呈摻雜矽基片形式或可為於基片上形成的 第一導電層或隨後導電層。導電件36典型地為金屬或摻雜 石夕層’其事先加圖樣而構成電子裝置之一部分。根據業界 已知程序，於導電件36上形成一層介電層32而構成整體積 體電路的一部分。 根據目前使用之選擇性沈積技術，製程中之次一步驟 典型地包含蝕刻介電層而形成互連貫穿孔或接觸孔。然而 根據本發明，薄成核層34沈積於介電層32上形成大體連續
(請先閲讀背面之注意事項再填寫本頁) 裝 -線. 412787 經 濟 部 智 慧 財 產 局 消 費 合 社 印 製 A7 B7 五、發明說明（7 ) 膜。此種成核層有助於沈積的CVD金屬開始形成包括原 子、離子或分子於基片上之界定排列之固體結晶狀態的過 程。 較佳成核層34包含由PVD TiN形成的TiN層或導電膜 或其它耐火膜（Nb、Al、Ti、Ta、鋁矽酸鹽、氧化石夕、 高氧化鋁等），藉CVD或PVD形成的TiN ( CVD TiN或PVD TiN)或此等層之組合。氮化鈦為較佳成核材料，原因為 氮化鈦可提供鋁之良好成核，具有良好良遷移阻力，且於 其下方安置介電層之用途中容易蝕刻。也較佳成核層厚度 為約10至約900埃，最佳厚度為約100至約200埃。 成核層34形成後，成核層34及介電層32 (揭示於第3 圖）加圖樣及蝕刻而打開孔眼，供形成貫穿孔或接觸孔向 下直達導電層36。 現在參考第4圊’顯示第3圖之貫穿孔或接觸孔38蝕 刻至成核層34及介電層32之剖面圖。貫穿孔或接觸孔38加 圖樣及蝕刻’可使用業界人士之已知任一種習知方式完 成。貫穿孔38具有壁40成形於介電層32，俾向下延伸足夠 距離而暴露出導電件或導電層3 6之表面或底面42。 蝕刻後仍殘留的成核層34部分可描述為自行排齊層， 該層覆蓋介電層32而形成場，於該場可出現均勻氈覆沈 積。藉此方式存在有成核層34，可防止非期望的結節12與 介電表面上形成’並免除需要藉化學機械拋光介電面來去 除其上形成的任何結節的需求。 現在參考第5圖’顯示不含空隙式金屬互連44及氈覆 -10- (請先閱讀背面之注意事項再填寫本頁} • — — — — — — — I — — — — — — — — Λ， - - 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（8) 金屬層46之剖面圖。化學蒸氣沈積金屬於加圖樣的基片 上，可提供同時選擇性沈積於貫穿孔或接觸孔38内部，及 覆蓋沈積於成核層34，而提供貫穿孔或接觸孔結構的服貼 覆蓋，而未於互連形成空隙（參見第1圖）或於場形成結 節。由於CVD A1均勻沈積於成核層34故，CVD A1之頂面
I 48大體平面化。 ^ 雖然CVD A1可於多種條件下沈積，但典型方法包括 晶圓溫度為約150°C至約300°C及沈積速率為約20 A / sec 至約13〇A/sec。CVD A1沈積可於小室壓力約1托耳至約 80托耳’較佳小室壓力為約25托耳進行^ CVD A1之較佳 沈積反應包括氫化二甲基鋁（DMAH)與氩氣（H2)根據 如下反應式反應： 6(CH3)2A1 - Η + 3H2....6A1(CH4)2 沈積於貫穿孔或接觸孔3 8(參見第4圖）而形成金屬互 連44具有選擇性，原因為下方導電層36之表面42已經於貫 穿孔或接觸孔38底面暴露於CVD A1。因此CVD A1由底面 42向上方沈積，填補貫穿孔或接觸孔38，而大體並無cvd A1沈積於貫穿孔或接觸孔壁4〇上（參見第4圖）。 此外，由於成核層34係於貫穿孔或接觸孔％蝕刻之前 沈積於介電層32上，故貫穿孔或接觸孔％之壁及底面分別 為介電層32及暴露的下方成核層36之暴露面。如前述大 體非導電性介電材料（包含们並非良好電子給予者，因此 不會對CVD金屬前驅㈣沈積_提供良好成核作用。反 而由於貫穿孔或接觸孔38下方暴露的導電件36對沈 ^----------------- <請先閲讀背面之注意事項再填寫本頁)
41278T7 ____B7_____ 五、發明說明（9 ) 4 成核，故金屬膜開始於貫穿孔或接觸孔底形成。於最初金 屬層已經沈積於貫穿孔或接觸孔底面42後，隨後更容易沈 積’因此金屬由貫穿孔或接觸孔底面42向上生長而填補孔 38 - 雖然貫穿孔或接觸孔38之介電壁40上的瑕疵，引起結 節於貫穿孔或接觸孔散在形成，但此等結節通常不會阻斷 貫穿孔或接觸孔而造成空隙。由於導電貫穿孔或接觸孔底 面暴露出大面積成核材料，故於結節有機會橫跨貫穿孔或 接觸孔生長而於其中形成空隙之前，貫穿孔或接觸孔已經 由底面向上填補金屬。 本發明之另一態樣中，於選擇性CVD過程之後，基片 可移動至PVDA1小室，而於低於CVDA1及PVDA1熔點之 溫度沈積一層PVD A1層50於先前形成的CVD層上。雖然 CVD金屬層46為鋁’但較佳PVD A1層50係於晶圓溫度低 於約660°C，較佳低於約40CTC沈積。鋁層46於約400。(：進 行PVD沈積過程中開始流動，而TiN成核層3 4仍牢固定位 原處呈固體金屬層。 較佳PVD A1層包含至少微量銅（Cu)。可使用AlCu乾 形成PVD AlCu層而達成。當於同一個簇工具上具有pVD 小室及CVD小室的整合製程中，於CVD A1之後接著為PVD AlCu時，介於其間無法形成氧化物層，PVE) A1Cu層5〇於 CVD A1層46上等角生長而無晶粒邊界，亦即，兩層的結 晶結構皆均勻。此外，依序CVD Al/PVD AICu方法可使交 混層（元件46與50結合）於約300°C退火約15分鐘而達成
A7 V ： ； V V· r ^ * . ·? >· ·； > ' · Β7 ...... 經濟部智慧財產局員工消費合作社印製 五、發明說明（10) Cu於CVD/PVD層内大體均勻分布。也較佳交混CVD/PVD A1層頂面52接受PVD TiN抗反射被覆（ARC)(未顯示出）俾 降低表面的反射係數並改善該層之光學製版性能。最後， 本發明之將基片孔眼金屬化之最佳方法包含下列依序步 驟：以介電層32遮蓋導電件36，藉PVD TiN方法沈積氮化 鈦之成核層34，蝕刻貫穿孔或接觸孔38而暴露出部分導電 件36，沈積選擇性/氈覆CVD A1層44，46，沈積PVD AlCu ) 層50，及沈積TiN ARC (未顯示出）。 現在參考第6圖，顯示組合設備工具60之示意圖。 典型地基片係經由卡式負載鎖62引進組合設備工具60及由 其中抽出。具有輪葉67之機械人64會在組合設備工具60内 部來移動基片通過組合設備工具60。一個機械人64典型地 安置於缓衝小室68來介於卡式負載鎖62，除氣晶圓取向小 室70，前潔淨小室72，PVD TiN小室74，及冷卻小室76間 轉運基片。第二個機械人78安置於轉運小室80内來介於冷 ') 卻小室76、積聚Ti小室82、CVD TiN小室84、CVD八1小 室86、及PVD AlCu處理小室88間來來去去轉運基片。整 合系統内的轉運小室80較佳維持於低/高壓真空於10-3至 - 10-8托耳之範圍。第6圖小室之特定構型包括可於單一組 合設備工具進行CVD及PVD過程二者之整合處理系統。小 室構型單純供示例說明之用而不得視為限制本發明之用 途。 典型地於組合設備工具60處理之基片由卡式負載鎖 62送至緩衝小室68，於此處，機械人64先將基片移動入除 -13- -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS)A4規格（2〗0 X 297公釐） 、麵 r,... -'r*, ^ 412787 A7 B7 五、發明說明（11) 氣小室70。然後，基片可轉運入前潔淨室72，PVD TiN小 室74，然後轉運至冷卻室76。機械人78典型地將基片由冷 卻小室76移動至1或多個處理小室32，3丨内部或其間隨 後將基片送回冷卻小室76。預期基片可以任一種次序，以 任一種次數於1或多個小室内處理或冷卻而完成基片上所 須結構的製造。處理後，基片由組合設備工具6〇移出，通 過緩衝小室68 ’然後送回負載鎖62。設有微處理器控制器 80來控制所須薄膜層於基片上方之順序與形成。 根據本發明，組合設備工具60將基片通過負載鎖62 通入除氣小室70,其中基片進行污染物之除氣。然後，基 片移動入前潔淨小室72，於此處清潔基片表面而去除任何 污染物。然後，機械人64將基片移入準備處理的冷卻小室 76。機械人78將基片移送至CVDTiN小室84或具有準直儀 之Ti小室82 ’亦即，多個小室大體平行基片延伸位在基片 與靶間’而將成核層沈積於基片上。若基片首先接受準直 化Ti層的沈積，則基片一般係接著在CVD TiN小室84内處 理。沈積CVD TiN層後，基片移送入蝕刻小室供對其上方 形成的各層加圖樣及電漿蚀刻而形成所須孔眼，隨後將形 成貫穿孔或接觸孔。 然後’基片具有孔眼延伸通過TiN成核層及介電層向 下延伸至界定貫穿孔或接觸孔底面的暴露出的導電件表 面，基片於CVD A1小室86内接受CVD金屬層例如CVD A卜 然後，基片於PVD AlCu小室88處理，及選擇性於位在整 合系統的PVD TiN小室74内處理。 -14- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁)
I I I ! I 訂·！ I--1;A 經濟部智慧財產局員工消費合作社印製 一 A7 B7 五、發明說明（Π) 經濟部智慧財產局員工消費合作社印製
Cu分散遍布CVD A1層，係由於整合系統可使基片於 具有CVD A1小室及PVD A1小室的單一處理工具内連續加 工處理故完成銅之分散。如此防止處理後的基片暴露於外 部環境可能導致於暴露面（亦即CVD A1層）上形成氧化物 層。若使氧化物層於C VD A1層上形成，則將妨礙p vd A1 層提供的Cu均勻分布遍布CVD A1層。 一種階梯式真空晶圊處理系統揭示於1993年2月16日 獲頒之Tepman等之美國專利第5，186,718號，名稱“階梯 式真空晶圓處理系統方法”（併述於此以供參考）。 現在參考第7圖舉例說明供應氣體至第6圖之系統 之C VD小室的氣箱系統。TiN氣箱供應N2、Ar、He、02、 Η?及NFS。反應產物肆二甲胺基鈦（TdmAT)以及惰性氣體 Ar及N2通入CVD TiN小室供處理。類似地，CVD A1氣箱 供應N2、Ar及He。反應產物氫化二曱基紹DMAH , 及 隋性氣體Ar通入C VD Α1小室供沈積紹。兩個小室皆配備 有渦輪泵於小室提供真空及配備有鼓風機/乾式泵。 雖然前文係針對本發明之較佳具體例說明，但本發 明之其它進一步具體例示未悖離其基本構想。本發明之範 圍係由隨附之申請專利範圍所限。 -15- 氏k尺度適用中國國豕標準（CNS)A4規格（210 X 297公釐） —裝--- (請先閲讀背面之泫意事項再填寫本頁) 訂. --線- A7 經濟部智慧財產局員工消費合作社印製 412787 B7 五、發明說明（13) 元件標號對照 10·. ..積體電路結構 50....PVD AlCu層 12.· 結節 52____頂面 14,38....貫穿孔，接觸孔 6 0…·組合設備工具 16·. ..介電層 62.…卡式負載鎖 18.., ..導電件 64,78..··機械人 20.. ..晶圓表面 68....緩衝小室 30.. ..層狀結構 7 0....除氣小室 31,32....處理小室 72....前潔淨小室 32.. ..介電層 74....PVD TiN小室 34.. ..成核層 76....冷卻小室 36·. ..導電件，導電層 80....轉運小室 40.. .•壁 80....微處理器控制器 42.· ..表面，底面 82.…積聚Ti小室 44·· ..互連 84....CVD TiN小室 46·. ..氈覆金屬層，CVD A1層 86....CVD AI小室 48.. ..頂面 88....PVD AlCu處理 4 -16- (請先閱讀背面之注意事項再填寫本頁) ^--------訂---------線 i I »1 · 本纸張尺度適用中國國家標準（CNS)A4規格（210x 297公釐）

Claims (1)

  1. 412787 A8 B8 C8 D8 申請專利範圍 1. 2. 3. 4. 5. 經濟部智慧財產局員工消費合作钍印製 6. 7. 8· 一種於具有一層非導電層覆蓋一個導電件之基片上形 成互連之方法，包括下列步驟： (a) 於非導電層表面上形成成核層； (b) 蚀刻互連通過成核層及非導電層而形成底面 暴露出導電件的一部分；及 (c) 化學蒸氣沈積金屬層，選擇性沈積於互連底 面及成核層上。 如申切專利範圍第1項之方法，其又包括步驟： (d) 於低於約660=c之溫度物理蒸氣沈積一層金屬 層於化學蒸氣沈積金屬層上，而使物理蒸氣沈積金屬 層及化學蒸氣沈積金屬層流入貫穿孔内，而未於其中 生成空隙。 如申請專利範圍第1項之方法 TiN組成。 如申請專利範圍第3項之方法 10至約9〇〇埃之厚度。 如申請專利範圍第丄項之方法 的金屬為鋁。 如申請專利範圍第丄項之方法 的金屬包括鋁及其中該鋁之物理蒸氣沈積係於低於約 400 C之溫度進行。 如申請專利範圍第1項之方法，其中步驟⑷至（C)係 於整合處理小室内進行。 如申明專利範圍第6項之方法，丨中該物理蒸氣沈積 其中該成核層係由 其中該成核層具有約 其中該化學蒸氣沈積 其中該物理蒸氣沈積
    (請先閎讀背面之注意事項再填寫本頁) 訂- AS B8 C8 _________ D8 六、申請專利範圍 的紹包括一種摻雜劑，該方法又包括步雜·· (d)於約250°C至約350°C之溫度退火。 9. 如申請專利範圍第工項之方法，其中該非導電層為電 介質。 10. —種形成及填補互連通過非導電層之選擇性化學蒸氣 沈積方法，其中該等互連具有一個導電底面，其改良 部分包括步驟： i (a)於導電層上形成一層成核層；及 (b)蝕刻互連通過成核層及非導電層。 11. 如申請專利範圍第1〇項之方法，其中該非導電層為介 電層。 12·如申請專利範圍第1〇項之方法，其中該成核層係由 TiN組成。 13.如申請專利範圍第12項之方法，其中該成核層具有約 10至約900埃之厚度。 }丨4· 一種於選擇性化學蒸氣沈積金屬於第二表面期間防止 非均勻沈積物於第一表面上形成之方法，該方法包括 步驟： (a)於第一表面上形成一層成核層’因此沈積於 第一表面上之金屬化學蒸氣大體平面化。 15.如申請專利範圍第14項之方法，其中該第—表面包括 電介質。 16·如請專利範圍第14項之方法，其中該成核層係由TiN 組成。 _____ -18- I紙張尺度適用中ΐ國家標準_( CNS ) Μ規格（2丨0X297公董） ' :~ (請先聞讀背面之注意事項再填寫本頁) 裝. *1Τ 線 經濟部智慧財4局員工消費合作社印^- A8 B8 C8 D8
    17. 如申請專利範圍第16項 乃忐其中該成核層具有約 10至900埃之厚度。 18. —種沈積金屬膜於基片之特 竹进。P分上之方法，該方法 包括步驟： ⑷提供導電成核層於基片之特選部分上；及 ⑻選擇性化學蒸氣沈積金屬膜於成核層上。 19. 如申請專利範圍第18項之方法，其中該選擇性化學蒸 乳沈積金屬膜之步驟包括下列步驟. (c)提供氫化二甲基鋁及氫氣； ⑷氫化一甲基鋁及氫氣於成核層面上反應而沈 積鋁於成核層上。 2〇·如申請專利範圍第19項之方法，其中該成核層係由 TiN組成。 (請先閱讀背面之注意事項再填寫本育) '11 經濟部智慧財產局員工消費合作社印製 -19- 本紙張尺度適用t國國家梯準（CNS ) A4規格（210X 297公釐）
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