TW365689B - Semiconductor device having an insulation film of low permittivity and a fabrication process thereof - Google Patents
Semiconductor device having an insulation film of low permittivity and a fabrication process thereofInfo
- Publication number
- TW365689B TW365689B TW086109088A TW86109088A TW365689B TW 365689 B TW365689 B TW 365689B TW 086109088 A TW086109088 A TW 086109088A TW 86109088 A TW86109088 A TW 86109088A TW 365689 B TW365689 B TW 365689B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- insulation film
- fabrication process
- low permittivity
- depositing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26339696 | 1996-10-03 | ||
JP9097672A JPH10163192A (ja) | 1996-10-03 | 1997-04-15 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW365689B true TW365689B (en) | 1999-08-01 |
Family
ID=26438835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086109088A TW365689B (en) | 1996-10-03 | 1997-06-28 | Semiconductor device having an insulation film of low permittivity and a fabrication process thereof |
Country Status (4)
Country | Link |
---|---|
US (1) | US5905298A (zh) |
JP (1) | JPH10163192A (zh) |
KR (1) | KR100292393B1 (zh) |
TW (1) | TW365689B (zh) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3801730B2 (ja) | 1997-05-09 | 2006-07-26 | 株式会社半導体エネルギー研究所 | プラズマcvd装置及びそれを用いた薄膜形成方法 |
JP3178375B2 (ja) * | 1997-06-03 | 2001-06-18 | 日本電気株式会社 | 絶縁膜の形成方法 |
US6166428A (en) * | 1997-08-25 | 2000-12-26 | Advanced Micro Devices, Inc. | Formation of a barrier layer for tungsten damascene interconnects by nitrogen implantation of amorphous silicon or polysilicon |
JP3141827B2 (ja) | 1997-11-20 | 2001-03-07 | 日本電気株式会社 | 半導体装置の製造方法 |
US6177286B1 (en) * | 1998-09-24 | 2001-01-23 | International Business Machines Corporation | Reducing metal voids during BEOL metallization |
JP2000094310A (ja) * | 1998-09-24 | 2000-04-04 | Matsushita Electric Ind Co Ltd | 被研磨基板の保持装置、基板の研磨方法及び半導体装置の製造方法 |
JP3601988B2 (ja) * | 1999-01-04 | 2004-12-15 | 株式会社東芝 | 絶縁膜の形成方法 |
KR100545710B1 (ko) * | 1999-05-25 | 2006-01-24 | 주식회사 하이닉스반도체 | 고밀도 플라즈마 산화막의 다단계 증착을 이용한 반도체 소자의층간절연막 형성방법 |
US6927160B1 (en) | 1999-06-09 | 2005-08-09 | National Semiconductor Corporation | Fabrication of copper-containing region such as electrical interconnect |
US6136688A (en) * | 1999-10-20 | 2000-10-24 | Vanguard International Semiconductor Corporation | High stress oxide to eliminate BPSG/SiN cracking |
KR100661220B1 (ko) * | 2004-12-29 | 2006-12-22 | 동부일렉트로닉스 주식회사 | 듀얼 절연막을 이용한 금속 배선 형성 방법 |
JP2006278219A (ja) * | 2005-03-30 | 2006-10-12 | Utec:Kk | Icp回路、プラズマ処理装置及びプラズマ処理方法 |
KR100675895B1 (ko) * | 2005-06-29 | 2007-02-02 | 주식회사 하이닉스반도체 | 반도체소자의 금속배선구조 및 그 제조방법 |
JP4939176B2 (ja) * | 2005-12-22 | 2012-05-23 | キヤノン株式会社 | 有機el素子 |
JP5543116B2 (ja) * | 2009-01-29 | 2014-07-09 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US9184041B2 (en) * | 2013-06-25 | 2015-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with backside structures to reduce substrate warp |
KR102334181B1 (ko) * | 2016-03-25 | 2021-12-03 | 쇼와덴코머티리얼즈가부시끼가이샤 | 유기 인터포저 및 유기 인터포저의 제조 방법 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5972745A (ja) * | 1982-10-19 | 1984-04-24 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JPH01287930A (ja) * | 1988-05-13 | 1989-11-20 | Seiko Epson Corp | 半導体装置 |
JPH0289346A (ja) * | 1988-09-27 | 1990-03-29 | Toshiba Corp | 半導体装置及びその製造方法 |
CA2026605C (en) * | 1990-10-01 | 2001-07-17 | Luc Ouellet | Multi-level interconnection cmos devices including sog |
US5719416A (en) * | 1991-12-13 | 1998-02-17 | Symetrix Corporation | Integrated circuit with layered superlattice material compound |
JPH07321199A (ja) * | 1994-05-27 | 1995-12-08 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US5607773A (en) * | 1994-12-20 | 1997-03-04 | Texas Instruments Incorporated | Method of forming a multilevel dielectric |
-
1997
- 1997-04-15 JP JP9097672A patent/JPH10163192A/ja not_active Withdrawn
- 1997-05-29 US US08/865,165 patent/US5905298A/en not_active Expired - Lifetime
- 1997-06-26 KR KR1019970027538A patent/KR100292393B1/ko not_active IP Right Cessation
- 1997-06-28 TW TW086109088A patent/TW365689B/zh active
Also Published As
Publication number | Publication date |
---|---|
US5905298A (en) | 1999-05-18 |
KR19980079282A (ko) | 1998-11-25 |
JPH10163192A (ja) | 1998-06-19 |
KR100292393B1 (ko) | 2001-07-12 |
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