TW360792B - Merged memory and logic (MML) integrated circuits including data path width reducing circuits and methods - Google Patents

Merged memory and logic (MML) integrated circuits including data path width reducing circuits and methods

Info

Publication number
TW360792B
TW360792B TW087101863A TW87101863A TW360792B TW 360792 B TW360792 B TW 360792B TW 087101863 A TW087101863 A TW 087101863A TW 87101863 A TW87101863 A TW 87101863A TW 360792 B TW360792 B TW 360792B
Authority
TW
Taiwan
Prior art keywords
mml
logic
path width
data path
width reducing
Prior art date
Application number
TW087101863A
Other languages
English (en)
Inventor
Gyu-Hong Kim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW360792B publication Critical patent/TW360792B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
TW087101863A 1997-07-14 1998-02-11 Merged memory and logic (MML) integrated circuits including data path width reducing circuits and methods TW360792B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970032669A KR100269299B1 (ko) 1997-07-14 1997-07-14 데이터패쓰(dq)수감소회로및감소방법과이를이용한반도체장치

Publications (1)

Publication Number Publication Date
TW360792B true TW360792B (en) 1999-06-11

Family

ID=19514408

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087101863A TW360792B (en) 1997-07-14 1998-02-11 Merged memory and logic (MML) integrated circuits including data path width reducing circuits and methods

Country Status (6)

Country Link
US (1) US5926420A (zh)
JP (1) JP4097165B2 (zh)
KR (1) KR100269299B1 (zh)
DE (1) DE19807739B4 (zh)
GB (1) GB2327272B (zh)
TW (1) TW360792B (zh)

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KR100474985B1 (ko) * 1997-06-23 2005-07-01 삼성전자주식회사 메모리로직복합반도체장치
US6216240B1 (en) * 1997-06-26 2001-04-10 Samsung Electronics Co., Ltd. Merged memory and logic (MML) integrated circuits including memory test controlling circuits and methods
US6195593B1 (en) * 1997-09-03 2001-02-27 Seiko Epson Corporation Reusable modules for complex integrated circuit devices
JP4026945B2 (ja) * 1998-08-11 2007-12-26 株式会社アドバンテスト 混在ｉｃ試験装置及びこのｉｃ試験装置の制御方法
KR100307626B1 (ko) 1998-08-31 2001-11-30 윤종용 디램과버퍼메모리를갖는메모리로직복합집적회로장치
KR100331551B1 (ko) * 1999-09-08 2002-04-06 윤종용 비스트 회로를 갖는 메모리 로직 복합 반도체장치
KR100800133B1 (ko) * 2001-09-13 2008-02-01 주식회사 하이닉스반도체 디큐 압축 테스트 모드를 위한 디큐 압축 방법 및 그 회로
KR100706226B1 (ko) * 2003-06-19 2007-04-11 삼성전자주식회사 어드레스 제어를 이용한 8배속/16배속 동작이 가능한비휘발성 반도체 메모리 장치
JP2006120250A (ja) 2004-10-21 2006-05-11 Fujitsu Ltd 半導体装置およびその試験方法
KR100634439B1 (ko) * 2004-10-26 2006-10-16 삼성전자주식회사 퓨즈프리 회로, 퓨즈프리 반도체 집적회로 및 퓨즈프리불휘발성 메모리 장치, 그리고 퓨즈프리 방법
KR100732241B1 (ko) 2006-01-24 2007-06-27 삼성전자주식회사 테스트 효율이 높은 반도체 메모리 장치, 반도체 메모리장치의 테스트 방법, 및 이를 구비한 테스트 시스템
KR100907927B1 (ko) * 2007-06-13 2009-07-16 주식회사 하이닉스반도체 반도체메모리소자 및 그의 구동방법
JP4820795B2 (ja) * 2007-10-04 2011-11-24 パナソニック株式会社 半導体記憶装置
KR100927409B1 (ko) * 2008-04-30 2009-11-19 주식회사 하이닉스반도체 반도체 소자와 그의 구동 방법
KR100977730B1 (ko) 2008-10-02 2010-08-24 주식회사 하이닉스반도체 반도체 메모리 및 그 테스터 방법

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KR100274478B1 (ko) * 1990-05-10 2001-01-15 칼 하인쯔 호르닝어 병렬 테스트 장치를 갖는 집적 반도체 메모리 및 그 리던던시 방법
US5315553A (en) * 1991-06-10 1994-05-24 Texas Instruments Incorporated Memory circuit test system using separate ROM having test values stored therein
US5465257A (en) * 1992-03-03 1995-11-07 Nec Corporation Test signal output circuit in LSI
US5377144A (en) * 1993-07-27 1994-12-27 Texas Instruments Inc. Memory array reconfiguration for testing
DE69415600T2 (de) * 1993-07-28 1999-07-15 Koninklijke Philips Electronics N.V., Eindhoven Mikrokontroller mit hardwaremässiger Fehlerbeseitigungsunterstützung nach dem Boundary-Scanverfahren
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KR0146544B1 (ko) * 1995-05-25 1998-11-02 김광호 다수개의 스위칭 수단을 가지는 다용도 패드를 구비한 반도체 메모리장치
US5574692A (en) * 1995-06-07 1996-11-12 Lsi Logic Corporation Memory testing apparatus for microelectronic integrated circuit
US5535165A (en) * 1995-06-30 1996-07-09 Cirrus Logic, Inc. Circuits, systems and methods for testing integrated circuit devices including logic and memory circuitry
KR100197554B1 (ko) * 1995-09-30 1999-06-15 윤종용 반도체 메모리장치의 고속테스트 방법
GB9622687D0 (en) * 1996-10-31 1997-01-08 Sgs Thomson Microelectronics An integrated circuit with tap controller
KR100265758B1 (ko) * 1997-08-05 2000-09-15 윤종용 반도체장치의 병합된 데이터 입출력 회로 및 방법

Also Published As

Publication number Publication date
GB2327272A (en) 1999-01-20
GB2327272B (en) 2002-07-17
JPH1152028A (ja) 1999-02-26
GB9802819D0 (en) 1998-04-08
DE19807739B4 (de) 2007-03-08
DE19807739A1 (de) 1999-01-21
US5926420A (en) 1999-07-20
KR19990010047A (ko) 1999-02-05
JP4097165B2 (ja) 2008-06-11
KR100269299B1 (ko) 2000-10-16

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