TW348293B - Method and apparatus for aligning the position of die on a wafer table a method for determining the position of a die on a wafer table after a wafer has been cut includes stepping the wafer table a series of one die lengths diagonally. - Google Patents

Method and apparatus for aligning the position of die on a wafer table a method for determining the position of a die on a wafer table after a wafer has been cut includes stepping the wafer table a series of one die lengths diagonally.

Info

Publication number
TW348293B
TW348293B TW086106927A TW86106927A TW348293B TW 348293 B TW348293 B TW 348293B TW 086106927 A TW086106927 A TW 086106927A TW 86106927 A TW86106927 A TW 86106927A TW 348293 B TW348293 B TW 348293B
Authority
TW
Taiwan
Prior art keywords
die
wafer table
wafer
diagonally
series
Prior art date
Application number
TW086106927A
Other languages
English (en)
Inventor
Balamurugan Subramanian
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW348293B publication Critical patent/TW348293B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/70—Determining position or orientation of objects or cameras
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/54466—Located in a dummy or reference die

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Automatic Control Of Machine Tools (AREA)
TW086106927A 1996-01-31 1997-05-23 Method and apparatus for aligning the position of die on a wafer table a method for determining the position of a die on a wafer table after a wafer has been cut includes stepping the wafer table a series of one die lengths diagonally. TW348293B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG1996000739A SG54995A1 (en) 1996-01-31 1996-01-31 Method and apparatus for aligning the position of die on a wafer table
US08/667,246 US5851848A (en) 1996-01-31 1996-06-20 Method and apparatus for aligning the position of die on a wafer table

Publications (1)

Publication Number Publication Date
TW348293B true TW348293B (en) 1998-12-21

Family

ID=20429201

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086106927A TW348293B (en) 1996-01-31 1997-05-23 Method and apparatus for aligning the position of die on a wafer table a method for determining the position of a die on a wafer table after a wafer has been cut includes stepping the wafer table a series of one die lengths diagonally.

Country Status (3)

Country Link
US (2) US5851848A (zh)
SG (1) SG54995A1 (zh)
TW (1) TW348293B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI498993B (zh) * 2011-11-09 2015-09-01 I Hsing Tsai 首顆晶粒之自動定位方法
TWI732576B (zh) * 2020-06-02 2021-07-01 梭特科技股份有限公司 微型機器人裝置及微晶粒排列系統

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JPH10164443A (ja) * 1996-11-29 1998-06-19 Nikon Corp 固体撮像素子カメラ
US6216055B1 (en) * 1997-12-16 2001-04-10 Texas Instruments Incorporated Partial semiconductor wafer processing
KR19990053079A (ko) * 1997-12-23 1999-07-15 윤종용 인식 마크가 형성된 반도체 웨이퍼 및 그 인식 마크를 이용한 웨이퍼 절삭 방법
JP2000068296A (ja) * 1998-08-19 2000-03-03 Nichiden Mach Ltd ダイボンダ
US6608920B1 (en) * 1998-10-29 2003-08-19 Applied Materials, Inc. Target acquisition technique for CD measurement machine
WO2000037884A1 (fr) * 1998-12-22 2000-06-29 Mitsubishi Denki Kabushiki Kaisha Procede et appareil permettant de mesurer des erreurs de positionnement au moyen d'un repere, et appareil d'usinage susceptible de corriger des erreurs en fonction de resultats de mesure
CH694745A5 (de) * 1999-01-21 2005-06-30 Esec Trading Sa Verfahren für die Montage von Halbleiterchips.
US6238939B1 (en) * 1999-04-30 2001-05-29 Tower Semiconductor Ltd. Method of quality control in semiconductor device fabrication
JP2001144148A (ja) * 2001-05-12 2001-05-25 Advantest Corp 半導体試験装置のウエハマップ表示装置
US6744913B1 (en) * 2000-04-18 2004-06-01 Semiconductor Technology & Instruments, Inc. System and method for locating image features
JP3538602B2 (ja) * 2000-06-28 2004-06-14 シャープ株式会社 半導体レーザー装置の製造方法および半導体レーザー装置の製造装置
US6498863B1 (en) 2000-09-20 2002-12-24 Media Cybernetics Inc. Method, system, and product for analyzing a digitized image of an array to create an image of a grid overlay
US6648730B1 (en) * 2000-10-30 2003-11-18 Applied Materials, Inc. Calibration tool
JP4514322B2 (ja) * 2000-12-08 2010-07-28 パナソニック株式会社 部品実装方法、及び部品実装装置
JP3784671B2 (ja) * 2001-07-23 2006-06-14 シャープ株式会社 半導体装置の製造方法
US7233841B2 (en) * 2002-04-19 2007-06-19 Applied Materials, Inc. Vision system
US7085622B2 (en) * 2002-04-19 2006-08-01 Applied Material, Inc. Vision system
US6773543B2 (en) * 2002-05-07 2004-08-10 Delaware Capital Formation, Inc. Method and apparatus for the multiplexed acquisition of a bare die from a wafer
US6831736B2 (en) * 2002-10-07 2004-12-14 Applied Materials Israel, Ltd. Method of and apparatus for line alignment to compensate for static and dynamic inaccuracies in scanning
KR100519789B1 (ko) * 2003-03-20 2005-10-10 삼성전자주식회사 반도체 기판의 얼라인 방법
JP4128513B2 (ja) * 2003-10-07 2008-07-30 株式会社新川 ボンディング用パターン識別方法、ボンディング用パターン識別装置及びボンディング用パターン識別プログラム
JP4088232B2 (ja) * 2003-10-07 2008-05-21 株式会社新川 ボンディング方法、ボンディング装置及びボンディングプログラム
US7271609B2 (en) * 2005-05-16 2007-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of automatically creating a semiconductor processing prober device file
KR100652435B1 (ko) * 2005-10-07 2006-12-01 삼성전자주식회사 첫 번째 다이의 위치를 구분할 수 있는 표시수단을구비하는 웨이퍼 및 웨이퍼의 다이 부착 방법
US7534655B2 (en) * 2006-10-10 2009-05-19 Texas Instruments Incorporated Method of arranging dies in a wafer for easy inkless partial wafer process
US20080188016A1 (en) * 2007-02-02 2008-08-07 Texas Instruments, Inc. Die detection and reference die wafermap alignment
US8538576B2 (en) * 2011-04-05 2013-09-17 Asm Technology Singapore Pte. Ltd. Method of configuring a dicing device, and a dicing apparatus for dicing a workpiece
JP5936847B2 (ja) 2011-11-18 2016-06-22 富士機械製造株式会社 ウエハ関連データ管理方法及びウエハ関連データ作成装置
CN104205317B (zh) * 2012-03-27 2017-02-22 富士机械制造株式会社 裸片供给装置
JP2014060249A (ja) * 2012-09-18 2014-04-03 Hitachi High-Tech Instruments Co Ltd ダイボンダ、および、ダイの位置認識方法
US10446728B2 (en) * 2014-10-31 2019-10-15 eLux, Inc. Pick-and remove system and method for emissive display repair
DE112017003551T5 (de) 2016-07-13 2019-03-28 Universal Instruments Corporation Modulares Die-Handhabungssystem
KR20210009843A (ko) * 2019-07-18 2021-01-27 세메스 주식회사 다이 픽업 방법

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US4929893A (en) * 1987-10-06 1990-05-29 Canon Kabushiki Kaisha Wafer prober
JP3659981B2 (ja) * 1992-07-09 2005-06-15 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド ダイ特定情報に特徴付けられるダイ上の集積回路を含む装置
CA2100324C (en) * 1992-08-06 2004-09-28 Christoph Eisenbarth Method and apparatus for determining mis-registration
JP3265504B2 (ja) * 1993-10-12 2002-03-11 株式会社ニコン 露光方法及び装置、並びに半導体素子の製造方法
US5694482A (en) * 1994-11-08 1997-12-02 Universal Instruments Corporation System and method for locating solder bumps on semiconductor chips or chip carriers
US5699260A (en) * 1995-03-14 1997-12-16 Analog Devices, Incorporated Technique for optimizing the number of IC chips obtainable from a wafer
US5665609A (en) * 1995-04-21 1997-09-09 Sony Corporation Prioritizing efforts to improve semiconductor production yield

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI498993B (zh) * 2011-11-09 2015-09-01 I Hsing Tsai 首顆晶粒之自動定位方法
TWI732576B (zh) * 2020-06-02 2021-07-01 梭特科技股份有限公司 微型機器人裝置及微晶粒排列系統

Also Published As

Publication number Publication date
SG54995A1 (en) 1998-12-21
US6016358A (en) 2000-01-18
US5851848A (en) 1998-12-22

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees