TW345636B - Time information synchronous delay control circuit - Google Patents

Time information synchronous delay control circuit

Info

Publication number
TW345636B
TW345636B TW086105150A TW86105150A TW345636B TW 345636 B TW345636 B TW 345636B TW 086105150 A TW086105150 A TW 086105150A TW 86105150 A TW86105150 A TW 86105150A TW 345636 B TW345636 B TW 345636B
Authority
TW
Taiwan
Prior art keywords
pulse
delay
rearward
delay unit
control circuit
Prior art date
Application number
TW086105150A
Other languages
English (en)
Inventor
Hatuki Toda
Original Assignee
Toshiba Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Co Ltd filed Critical Toshiba Co Ltd
Application granted granted Critical
Publication of TW345636B publication Critical patent/TW345636B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

Landscapes

  • Dram (AREA)
  • Pulse Circuits (AREA)
TW086105150A 1996-04-23 1997-04-21 Time information synchronous delay control circuit TW345636B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10097696 1996-04-23

Publications (1)

Publication Number Publication Date
TW345636B true TW345636B (en) 1998-11-21

Family

ID=14288388

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086105150A TW345636B (en) 1996-04-23 1997-04-21 Time information synchronous delay control circuit

Country Status (3)

Country Link
KR (1) KR100292127B1 (zh)
CN (2) CN1132104C (zh)
TW (1) TW345636B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468709B1 (ko) * 1998-03-30 2005-03-16 삼성전자주식회사 차동클럭신호를이용한클럭동기지연회로
US6668331B1 (en) * 2000-03-24 2003-12-23 Advantest Corp. Apparatus and method for successively generating an event to establish a total delay time that is greater than can be expressed by specified data bits in an event memory
US7183825B2 (en) * 2004-04-06 2007-02-27 Freescale Semiconductor, Inc. State retention within a data processing system
WO2006018943A1 (ja) * 2004-08-19 2006-02-23 Renesas Technology Corp. 位相同期回路
TWI273367B (en) * 2004-10-01 2007-02-11 Fortune Semiconductor Corp Method and device for calibrating monitor clocks
JP4808414B2 (ja) * 2005-01-31 2011-11-02 富士通株式会社 コンピュータシステム及びメモリシステム
US7685393B2 (en) * 2006-06-30 2010-03-23 Mosaid Technologies Incorporated Synchronous memory read data capture
CN103257309B (zh) * 2012-02-17 2015-10-07 安凯(广州)微电子技术有限公司 ddr系列pcb板时序补偿方法、系统及终端
TWI522809B (zh) * 2013-01-22 2016-02-21 威盛電子股份有限公司 補償同步資料匯流排之誤差的裝置與方法
CN104820654B (zh) * 2015-04-29 2018-02-02 桂林电子科技大学 一种延时调整器

Also Published As

Publication number Publication date
KR100292127B1 (ko) 2001-06-01
CN1132104C (zh) 2003-12-24
KR970072700A (ko) 1997-11-07
CN1229729C (zh) 2005-11-30
CN1169000A (zh) 1997-12-31
CN1389797A (zh) 2003-01-08

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