TW332319B - The semiconductor apparatus with planarization surface and its producing method - Google Patents

The semiconductor apparatus with planarization surface and its producing method

Info

Publication number
TW332319B
TW332319B TW083102442A TW83102442A TW332319B TW 332319 B TW332319 B TW 332319B TW 083102442 A TW083102442 A TW 083102442A TW 83102442 A TW83102442 A TW 83102442A TW 332319 B TW332319 B TW 332319B
Authority
TW
Taiwan
Prior art keywords
fitting portion
silicon
density wire
oxide
interlayer insulating
Prior art date
Application number
TW083102442A
Other languages
English (en)
Inventor
Yoshio Hayashide
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW332319B publication Critical patent/TW332319B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)
  • Wire Bonding (AREA)
TW083102442A 1994-02-23 1994-03-21 The semiconductor apparatus with planarization surface and its producing method TW332319B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6025220A JPH07235537A (ja) 1994-02-23 1994-02-23 表面が平坦化された半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
TW332319B true TW332319B (en) 1998-05-21

Family

ID=12159887

Family Applications (1)

Application Number Title Priority Date Filing Date
TW083102442A TW332319B (en) 1994-02-23 1994-03-21 The semiconductor apparatus with planarization surface and its producing method

Country Status (6)

Country Link
US (2) US5500558A (zh)
EP (1) EP0669645B1 (zh)
JP (1) JPH07235537A (zh)
KR (1) KR0159351B1 (zh)
DE (1) DE69418302T2 (zh)
TW (1) TW332319B (zh)

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* Cited by examiner, † Cited by third party
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JPH06333944A (ja) * 1993-05-25 1994-12-02 Nippondenso Co Ltd 半導体装置
JP3438446B2 (ja) * 1995-05-15 2003-08-18 ソニー株式会社 半導体装置の製造方法
JPH0955425A (ja) * 1995-08-10 1997-02-25 Mitsubishi Electric Corp 多層Ａｌ配線構造を有する半導体装置およびその製造方法
US6478977B1 (en) 1995-09-13 2002-11-12 Hitachi, Ltd. Polishing method and apparatus
JP2785768B2 (ja) * 1995-09-14 1998-08-13 日本電気株式会社 半導体装置の製造方法
JPH09172072A (ja) * 1995-12-18 1997-06-30 Nec Corp 半導体装置及びその製造方法
US6136728A (en) * 1996-01-05 2000-10-24 Yale University Water vapor annealing process
US6653733B1 (en) * 1996-02-23 2003-11-25 Micron Technology, Inc. Conductors in semiconductor devices
US5663108A (en) * 1996-06-13 1997-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Optimized metal pillar via process
JP3941133B2 (ja) * 1996-07-18 2007-07-04 富士通株式会社 半導体装置およびその製造方法
JPH1065118A (ja) * 1996-08-19 1998-03-06 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5861647A (en) * 1996-10-02 1999-01-19 National Semiconductor Corporation VLSI capacitors and high Q VLSI inductors using metal-filled via plugs
US6040628A (en) 1996-12-19 2000-03-21 Intel Corporation Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics
JP3340333B2 (ja) * 1996-12-26 2002-11-05 株式会社東芝 半導体装置及びその製造方法
JPH10270555A (ja) * 1997-03-27 1998-10-09 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5981374A (en) * 1997-04-29 1999-11-09 International Business Machines Corporation Sub-half-micron multi-level interconnection structure and process thereof
US6212671B1 (en) * 1997-10-20 2001-04-03 Mitsubishi Electric System Lsi Design Corporation Mask pattern data producing apparatus, mask pattern data producing method and semiconductor integrated circuit device
EP1042793A1 (de) * 1997-12-16 2000-10-11 Infineon Technologies AG Barriereschicht für kupfermetallisierung
TW498440B (en) 1998-03-30 2002-08-11 Hitachi Ltd Manufacture method of semiconductor device
KR100281897B1 (ko) * 1998-07-21 2001-03-02 윤종용 도전층을 갖는 반도체 장치의 제조방법
JP2000156480A (ja) * 1998-09-03 2000-06-06 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6143644A (en) * 1998-09-17 2000-11-07 Taiwan Semiconductor Manufacturing Company Method to prevent passivation from keyhole damage and resist extrusion
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6429132B1 (en) * 1998-12-23 2002-08-06 Aurora Systems, Inc. Combination CMP-etch method for forming a thin planar layer over the surface of a device
JP3345880B2 (ja) 1999-06-29 2002-11-18 日本電気株式会社 不揮発性メモリセルと電界効果トランジスタとを備えた半導体装置およびその製造方法
US6303043B1 (en) * 1999-07-07 2001-10-16 United Microelectronics Corp. Method of fabricating preserve layer
JP2001024056A (ja) * 1999-07-12 2001-01-26 Mitsubishi Electric Corp 半導体装置の多層配線装置及びその製造方法
US6521977B1 (en) * 2000-01-21 2003-02-18 International Business Machines Corporation Deuterium reservoirs and ingress paths
KR100363093B1 (ko) * 2000-07-28 2002-12-05 삼성전자 주식회사 반도체 소자의 층간 절연막 평탄화 방법
US20030141597A1 (en) * 2002-01-31 2003-07-31 Houston Theodore W. Semiconductor apparatus having contacts of multiple heights and method of making same
US20030177639A1 (en) * 2002-03-19 2003-09-25 Berg N. Edward Process and apparatus for manufacturing printed circuit boards
KR100673883B1 (ko) * 2002-06-29 2007-01-25 주식회사 하이닉스반도체 반도체소자의 콘택 플러그 형성방법
US20040219759A1 (en) * 2002-12-19 2004-11-04 Houston Theodore W Semiconductor apparatus having contacts of multiple heights and method of making same
US7743698B2 (en) * 2003-10-31 2010-06-29 Sephra L.P. Fountain that flows with fluidic material
KR100705937B1 (ko) * 2003-12-19 2007-04-11 에스티마이크로일렉트로닉스 엔.브이. 실리콘 질화막의 스트레스를 방지 및 완충하는 패드구조를 구비한 반도체 장치
JP5704811B2 (ja) * 2009-12-11 2015-04-22 キヤノン株式会社 固体撮像装置の製造方法
JP5329001B2 (ja) * 2011-02-09 2013-10-30 キヤノン株式会社 半導体装置の製造方法
JP5241902B2 (ja) * 2011-02-09 2013-07-17 キヤノン株式会社 半導体装置の製造方法

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Publication number Priority date Publication date Assignee Title
JPS4835778A (zh) * 1971-09-09 1973-05-26
JPS5958838A (ja) * 1982-09-29 1984-04-04 Hitachi Ltd 半導体装置
JPS59136934A (ja) * 1983-01-27 1984-08-06 Nec Corp 半導体装置の製造方法
IL82113A (en) * 1987-04-05 1992-08-18 Zvi Orbach Fabrication of customized integrated circuits
US4954459A (en) * 1988-05-12 1990-09-04 Advanced Micro Devices, Inc. Method of planarization of topologies in integrated circuit structures
US5077238A (en) * 1988-05-18 1991-12-31 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device with a planar interlayer insulating film
JPH01303742A (ja) * 1988-05-31 1989-12-07 Nec Corp 半導体装置
JPH02219264A (ja) * 1989-02-20 1990-08-31 Matsushita Electric Ind Co Ltd Ｄｒａｍセルおよびその製造方法
US5139608A (en) * 1991-04-01 1992-08-18 Motorola, Inc. Method of planarizing a semiconductor device surface
JP2870610B2 (ja) * 1991-07-25 1999-03-17 三菱電機株式会社 路側通信放送方式
KR960003864B1 (ko) * 1992-01-06 1996-03-23 삼성전자주식회사 반도체 메모리장치 및 그 제조방법
US5317192A (en) * 1992-05-06 1994-05-31 Sgs-Thomson Microelectronics, Inc. Semiconductor contact via structure having amorphous silicon side walls
US5302551A (en) * 1992-05-11 1994-04-12 National Semiconductor Corporation Method for planarizing the surface of an integrated circuit over a metal interconnect layer
JPH0621244A (ja) * 1992-06-30 1994-01-28 Fujitsu Ltd 半導体装置の製造方法
US5494857A (en) * 1993-07-28 1996-02-27 Digital Equipment Corporation Chemical mechanical planarization of shallow trenches in semiconductor substrates
JPH0745616A (ja) * 1993-07-29 1995-02-14 Nec Corp 半導体装置の製造方法
US5567661A (en) * 1993-08-26 1996-10-22 Fujitsu Limited Formation of planarized insulating film by plasma-enhanced CVD of organic silicon compound
US5665202A (en) * 1995-11-24 1997-09-09 Motorola, Inc. Multi-step planarization process using polishing at two different pad pressures

Also Published As

Publication number Publication date
KR0159351B1 (ko) 1999-02-01
KR950025894A (ko) 1995-09-18
EP0669645A1 (en) 1995-08-30
DE69418302D1 (de) 1999-06-10
US5500558A (en) 1996-03-19
EP0669645B1 (en) 1999-05-06
DE69418302T2 (de) 1999-09-30
JPH07235537A (ja) 1995-09-05
US5840619A (en) 1998-11-24

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