TW321616B - - Google Patents
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- Publication number
- TW321616B TW321616B TW086101262A TW86101262A TW321616B TW 321616 B TW321616 B TW 321616B TW 086101262 A TW086101262 A TW 086101262A TW 86101262 A TW86101262 A TW 86101262A TW 321616 B TW321616 B TW 321616B
- Authority
- TW
- Taiwan
- Prior art keywords
- flux
- welding
- item
- solder
- scope
- Prior art date
Links
- 229910000679 solder Inorganic materials 0.000 claims description 75
- 230000004907 flux Effects 0.000 claims description 58
- 238000003466 welding Methods 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 239000012752 auxiliary agent Substances 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 1
- 230000002079 cooperative effect Effects 0.000 claims 1
- 239000010977 jade Substances 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 description 11
- 239000000956 alloy Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 8
- 239000000758 substrate Substances 0.000 description 4
- 238000001994 activation Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910001369 Brass Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 206010011469 Crying Diseases 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/111—Preheating, e.g. before soldering
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1178—Means for venting or for letting gases escape
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
發明範圍 本發明一般地係關於焊接連接,以及,更特別地係關於 —種焊塊裝置、一種電子元件與一種用以形成一焊塊的方法。 發明背景 焊塊經常時附著在電子元件如積體電路或電路板之導電 區或焊接墊片,以供電子元件之表面固定使用。 預形成的焊塊可自動地定位於使用各式各樣已知技術的 預塗助焊劑的焊接墊片上,包括自動拾起與放置方法與網 板印刷方法。焊塊放置後經常是一個软熔操作,其使焊塊 牢牢固定於焊接墊片。 焊塊也可由一種焊劑形成,其包括一種焊接合金與—種 在軟熔操作之前施加在焊接墊片上的助焊劑。當焊劑渡過 軟熔過程後,焊接合金"成球狀”及形成焊塊。 在軟溶過程期間,助焊劑活化與分散,除去焊塊與焊接 整片之表面污染物及確保焊塊堅固地附著在焊接墊片。然 而,在助焊劑活化與分散過程期間,焊塊可能隨著助焊劑 移動而與焊接墊片分離。另外,助焊劑可能被困在焊塊與 焊接墊片之間,結果產生弱的焊塊·至-焊接墊片附著β 經濟部中央標準局貝工消費合作社印製 因此對於焊塊方法與裝置有一個需要,其可加強焊塊在 焊接墊片上的正確定位及增加焊塊與焊接墊片之間的連接 信賴性。 發明摘述 根據本發明之一個觀點,前述的需要係由一個焊塊裝置 所提出,該裝置包括—個充分導電區與一個從充分導電區
321616 Α7 Β7 五、發明説明( 經濟部中央標準局貝工消費合作社印製 突出的隙鏠。烊接保護區至少部份環繞充分導電區之周園 及隙縫之周固。焊塊係形成於導電區及至少一部份焊接保 護區上。 才據本發月之另一個觀點,一種電子元件包括一個介電 區、—個配置於介電區的充分導電區、-個緊鄰充分導電 區的焊接保護區、一個藉由除去充分導電區與介電區之材 料而形成的隙縫與—個連結導電區的焊塊,其覆蓋至少一 部份焊接保護區與隙縫。 根據本發明之另外—個觀點,—種用以形成—焊塊的方 法包括:提供一個具有一個充分導電區、一個從充分導電區 哭出的隙縫與一個烊接保護區的裝置,烊接保護區至少部 6 %繞導電區與隙縫;放置許多焊劑於裝置上,焊劑包含 一種焊料與一種助焊劑,焊劑充分覆蓋導電區與至少一部 汾焊接保護區;以及加熱焊劑以形成焊塊於導電區與至少 一部份焊接保護區。 從隨後作爲説明所顯示與插述的本發明之較佳具體實施 例之描述,熟諳此技藝者將容易地明白本發明之優點。如 同將被了解的,本發明能夠有其它與不同的具體實施例, 且其知節能夠有各方面的改善。於是,圖案與描述本質上 是當作説明用的,及不當作限制用的。 圏案簡述 -圈1是根據本發明之一個較佳具體實施例的一個電子元件 接合區之平面圖。 屬2是沿著圖^中描寫的接合區之2·2線的橫截面圖。 讀 先 閲 讀 背 之 注
I 養
經 t 央 標 準 Μ 貝 工 消 費 合 作 社 印 五、發明説明(3 :3是圈i與圖2中描寫的電子元件之接合區平面圈,其 描出软熔過程期間形成的焊塊。 圈4是沿著圖3中描寫的接合區之線44的橫截面圈。 圈5是根據本發明之較佳具趙實施例之用以形成一焊 方法之流程圖》 較佳具體實施例詳述 現在轉向圖案,其中相同的數字指示相同的元件,圏!是 一個根據本發明之較佳具體實施例的電子元件之接合區平 面圖《接合區10可附著至電子元件(未顯示出),例如尤其 是積體電路晶片或印刷電路板,或可爲電予元件之主要部 份。許多接合區10可存在於單一電子元件是令人期待的。 .在個實例中’ 31個接合區係配置於一個電子元件上。 如同圖1顯示的,接合區10包括一個焊接保護區12,焊 接保護材料是爲人熟知的及廣泛可取得的:—個導電區14 ,其可爲如由金屬材料如銅所製成的焊接墊片;一個隙縫 1 6與一個包含許多焊劑的焊劑區18 β 隙縫16係從焊接墊片突出,且實質地垂直焊接墊片 隙縫16可爲任何須要的形狀,例如圓形、長方形或橢圓形 ,以及可用任何適合的方法形成,例如使用雷射。烊接保 護區1 2較佳地係環繞焊接墊片! 4輿隙縫〗6 β烊劑i 8覆蓋 焊接墊片14,部份延仲至焊接保護區12及部份覆蓋隙縫16。 _接合區10可用各式各樣的方式建構。一個適合於接合區 1 0的構造實例係顯示於圈2。如同説明的,焊接整片j 4係 配置於介電區20的較大導電層15之外露區域,其可爲一種 請 先 閲 讀 背 之 注
I 訂 飞 6- 本紙張尺度適用中國國家標準(CNS ) Α4«<格(210X297公釐) B7 五、發明説明(4 ) 基材如陶瓷或其它材料。焊接保護區12可配置於導電層15 上面及可選擇性地除去而形成焊接墊片14。隙縫Η延伸經 過焊接保護區12與導電層15,以便外露基材2〇。經過基材 20的通路孔23可利用接合區1〇反側(未顯示出)上的元件( 未顯示出)電連接焊接墊片14,典型地是連接至積體電路元 件。 焊劑1 8較佳地係使用普遍熟知的技術網版印刷至接合區 10,例如使用型版(未顯示出)與橡皮刮刀(未顯示出)。可 爲金屬的型版之適合金屬包括不錄鋼 '黃銅或銅,但不限 於此,其具有藉由如鑿孔、蹐孔或蝕刻所形成的小孔。較 佳地,型版上的一個小孔係對應於接合區i 〇上的一個焊接 墊片14位置》令人期待的是多接合區1〇存在時,型版可具 有多對應小孔。更令人期待的是焊劑18可經由型版同時施 加至許多接合區1 0組合,例如許多電子元件形成於單一基 材2 0時。在某個實例中,焊劑i 8係施加至丨4個電子元件, 每個電子元件具有31個接合區1〇。 經濟部中央榡隼局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 爲了將焊劑18配置於接合區1〇上,型版係放置在焊接整 片14上,以及橡皮刮刀迫使焊劑18經過型版到達焊接墊片 1 4。焊劑1 8可印刷成任何須要的形狀,例如長方形或圓柱 狀或其它形狀。如同圈1與2顯示的,焊劑18的形狀是長方 形。 -通常,焊劑18包括至少三種工作成份:一種焊接合金、一 種助焊劑與一種典型地爲適合溶解助焊劑的溶劑的載體。 通常,助焊劑是在低於焊接合金之熔點的溫度下活化。焊 本紙浪尺度適用中國國家標準(CNS > A4規格(210X297公釐)
經濟部中央標準局負工消費合作社印1iL Α7 Β7 五、發明説明(5 ) 劑18之組成必須以可軟焊性與連結完整性需求爲基礎來選 擇》 在適用於本文所描述的接合區10的焊接連接範固中有各 式各樣爲人熟知的適合的烊劑材料。一種適合的焊劑是商 業上可得自位於美國组澤西州(New Jersey) 07304澤西市 (Jersey City)第440號公路600號的阿爾法金屬公司 (Alphametals)之件號RMA390DH4,其包含約90%焊接合金 與約5%助焊劑,其餘爲載體,焊接合金依序包含大約62% 錫、大約3 6 %鉛與大約2 %銀》 如同圖1與2顯示的,焊劑18的體積爲大約〇·78立方毫米 焊劑區1 8之尺寸應以須要的最後焊塊尺寸(在下面更進一 步討論)爲基礎來選擇。較佳的焊劑-對-焊塊體積比是7 : 1 。高焊劑-對-焊塊體積比可降低焊劑1 8之位置對於最後焊 塊位置的小變化的靈敏度,也可幫助確定小的焊劑體積變 動對最後焊塊尺寸有減小的衝擊。 囷3與4是囷1與2描寫的電子元件之接合區圖,其説明軟 熔操作期間由焊劑18所形成的焊塊22。焊塊可在軟熔期間 由焊劑1 8以許多步驟所形成。首先,焊剤1 8係在低於焊劑 18之焊接合金成份之熔點的溫度下加熱一段時間。加熱溫 度與時段係選擇以便充分活化焊劑18之助焊劑成份及提供 足量的時間使助焊劑完成其作用及分散。 .雖然有許多溫度與焊接合金之熔點有關聯,但是約179 至183 C的溫度範固是適合的β同樣地有各種適合的時段 輿助焊劑之活化有關聯。一個較佳的軟熔過程可加以提供 本纸張尺度適用中國國家揉準(CMS ) Α4規格(210X297公釐) (請先閱讀背面之注意事項再填寫本頁)
經濟部中央標準局員工消費合作社印製 A 7 ______ B7 _五、發明説明(6 ) ,以使尤其是包含約9 Ο %焊接合金與约5 %助烊劑的烊劑i 8 在大約150至172aC的溫度範囷内加熱大約2分鐘。 在助焊劑活化過程期間,焊劑i 8之可能殘留困在坪塊2 2 與焊接墊片14之間的助焊劑成份流進隙縫16,部份由於助 焊劑對介電基材20的吸引力,所以增加焊塊22與焊接整片 14之間連接信賴性。另外,隙縫16捕捉流自烊接保護區12 的過剩助焊劑,抑制了焊劑! 8或焊塊22位移的傾向及輔助 正確的焊塊22對焊接墊片14的位置。 爲了完成軟熔過程,焊劑18可加熱在焊接合金之熔點附 近,例如在大約178至183Ό的溫度範圍内,其使得焊接合 金·’成球狀",以及在焊接墊片14上形成焊塊22,因此坪接 合金被吸引到導電焊接墊片14 β加熱至一洄較高的溫度也 是須要的。例如達到2 1 8。(:左右,以改善焊接連結的品質 。如同圖4顯示的,焊塊2 2延伸覆蓋至少一部份焊接保護 區1 2及至少一部份隙縫! 6。 雖然企圈將本文描述的技術應用到大範圍的焊塊尺寸及 間距,但是在一個較佳具體實施例中,焊塊2 2量到〇丨8毫 米直徑’且可在鄰近焊塊(未顯示出)之大約14毫米之内形 成。 因此’可了解到如同圖5所説明的,從方塊開始,用 以形成一焊塊的方法包括一個第一步驟32,其提供一種具 有一個充分導電區、一個實質地垂直充分導電區的隙缝與 —個焊接保護區的裝置’該焊接保護區至少部份環繞導電 區與昧縫》下一個步驟34包括放置許多包含焊接合金與助
ϋ· m I (請先閲讀背面之注意事項再填寫本頁) ^i·.* ^^1· In ·
、?T -9- 本紙狀度適用中國國家橾率(CNS } 321616 A7 經濟部中央標準局負工消費合作社印裝 B7 五、發明説明(7 ) 焊劑的焊劑於装置上,充分覆蓋導電區與—部份焊接保護 區。最後步樣3 6牵涉到加熱焊劑以在導電區與焊接保護區 上形成焊塊。 使用本文描述的裝置與方法,過程缺陷與加工成本降低 。正確的焊塊對焊接墊片的定位是藉由使用介電障縫而得 到’該隙縫在軟炫過程期間吸收過剩的助焊劑與幫助校正 錯棑及強化焊塊與焊接墊片之間的焊接連結完整性而不用 筇貴的工具如自動裝置。 、 顯而易見的’本發明之其它與更進—步的丨 ,叼2氕可加以設 計而不税離附屬申請專利範固及其同等物之精神與範 以及頃了解到不應以任何方法限制本發明, ^ 於上延的特定具 體實施例,而只由下列的申請專利範圍殳其 欠丹 j争物所支配。 -10- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) (請先閲讀背面之注意事項再填寫本頁)
Claims (1)
- 包含如下的步 A8 B8 C8 D8 中請專利範圍 l —種用以形成一焊塊的方法,步银如下 提供一種具有—個充分導電區、-缺充分導電區突 出的陳縫與-個焊接保護㈣裝置,料接保護區至少 部份環繞導電區與隙縫; 放置許多焊劑於裝置上,焊劑包含_種焊材與一種助 淳劑,㈣大致覆蓋導電區與至少_部份焊接 以及 加熱焊劑以在導電區與至少—部份焊接保護區上形成 浮塊。 根據申請專利範圍第1項的方法,其另外 驟: 在加熱焊劑以形成焊塊之前’加❸旱劑至攸於焊材之 塔點的溫度,至少-部份助焊劑從焊接保護區流入隙縫。 3.根據申請專利範圍第2項的方法,其中溫度是大約15〇_ 17 2。(:。 《根據中請㈣範園第2項的方法,|中在該溫度下維持 焊劑的時間大於1分鐘。 5·根據申請專利範圍第玉項的方法,其另外包含如下的步 驟: 在加熱焊劑以形成焊塊之前,加熱焊劑至低於焊材之 溶點的溫度,至少-部份助焊劑從充分導電區流入陈缝。 6.根據申請專利範圚第1項的方法,其另外包含如下的步 驟: 附著焊塊於電路板。 -11 本紙張用t S目家鱗(。叫八械格(21^297公釐) -----’---I』裝------訂------ (請先鬩讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印«. ABCD 321616 六、申請專利範圍 7. 根據申請專利範圍第1項的方法,其中焊劑體積比焊塊 體積大超過5倍。 8. 根據申請專利範圍第1項的方法,其中焊劑體積形狀係 選自長方形與圓柱形: 9·根據申請專利範圍第丨項的方法,其中焊劑係配置於至 少一部份隙缝。 10.恨據申請專利範圍第}項的方法,其中焊接保護區具 小於1 0毫米的厚度。 ' (請先聞讀背面之注意Ϋ項再填寫本頁) 袈· 訂 經濟部中央揉準局貝工消費合作社印褽 娜 Μ *«/ Ns 6 /(\ 準 標 家 國 國 中 用 一適 釐 -公 7 29
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US08/635,111 US5738269A (en) | 1996-04-19 | 1996-04-19 | Method for forming a solder bump |
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TW321616B true TW321616B (zh) | 1997-12-01 |
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KR (1) | KR100278959B1 (zh) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US6222136B1 (en) * | 1997-11-12 | 2001-04-24 | International Business Machines Corporation | Printed circuit board with continuous connective bumps |
US5962151A (en) * | 1997-12-05 | 1999-10-05 | Delco Electronics Corp. | Method for controlling solderability of a conductor and conductor formed thereby |
US6316736B1 (en) * | 1998-06-08 | 2001-11-13 | Visteon Global Technologies, Inc. | Anti-bridging solder ball collection zones |
JP2000040867A (ja) * | 1998-07-24 | 2000-02-08 | Shinko Electric Ind Co Ltd | 半導体チップ実装用回路基板 |
SG90709A1 (en) * | 1998-09-04 | 2002-08-20 | Advanced Systems Automation | Method of producing solder bumps on substrate |
US6394819B1 (en) | 1998-10-29 | 2002-05-28 | The Whitaker Corporation | Dielectric member for absorbing thermal expansion and contraction at electrical interfaces |
US6085968A (en) * | 1999-01-22 | 2000-07-11 | Hewlett-Packard Company | Solder retention ring for improved solder bump formation |
US6047637A (en) * | 1999-06-17 | 2000-04-11 | Fujitsu Limited | Method of paste printing using stencil and masking layer |
US7572343B2 (en) * | 2003-08-06 | 2009-08-11 | Board Of Trustees Of Michigan State University | Composite metal matrix castings and solder compositions, and methods |
US6380060B1 (en) * | 2000-03-08 | 2002-04-30 | Tessera, Inc. | Off-center solder ball attach and methods therefor |
US6403399B1 (en) * | 2000-08-11 | 2002-06-11 | Lsi Logic Corporation | Method of rapid wafer bumping |
US6419148B1 (en) | 2001-01-23 | 2002-07-16 | Orbotech Ltd. | System for forming bumps on wafers |
JP4094982B2 (ja) * | 2003-04-15 | 2008-06-04 | ハリマ化成株式会社 | はんだ析出方法およびはんだバンプ形成方法 |
TWI243462B (en) * | 2004-05-14 | 2005-11-11 | Advanced Semiconductor Eng | Semiconductor package including passive component |
JP2011023509A (ja) * | 2009-07-15 | 2011-02-03 | Renesas Electronics Corp | 半導体装置の製造方法、および、これに用いる半導体製造装置 |
AT516750B1 (de) * | 2014-12-18 | 2016-08-15 | Zizala Lichtsysteme Gmbh | Verfahren zur Voidreduktion in Lötstellen |
KR102326505B1 (ko) | 2015-08-19 | 2021-11-16 | 엘지이노텍 주식회사 | 인쇄회로기판 및 그의 제조 방법 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4339768A (en) * | 1980-01-18 | 1982-07-13 | Amp Incorporated | Transistors and manufacture thereof |
JPS5724775U (zh) * | 1980-07-17 | 1982-02-08 | ||
US5024372A (en) * | 1989-01-03 | 1991-06-18 | Motorola, Inc. | Method of making high density solder bumps and a substrate socket for high density solder bumps |
US5043796A (en) * | 1990-02-06 | 1991-08-27 | Motorola, Inc. | Isolating multiple device mount with stress relief |
JPH04148587A (ja) * | 1990-10-11 | 1992-05-21 | Matsushita Electric Ind Co Ltd | 表面実装用部品の実装方法 |
US5133495A (en) * | 1991-08-12 | 1992-07-28 | International Business Machines Corporation | Method of bonding flexible circuit to circuitized substrate to provide electrical connection therebetween |
US5403671A (en) * | 1992-05-12 | 1995-04-04 | Mask Technology, Inc. | Product for surface mount solder joints |
US5261593A (en) * | 1992-08-19 | 1993-11-16 | Sheldahl, Inc. | Direct application of unpackaged integrated circuit to flexible printed circuit |
DE4310930A1 (de) * | 1993-04-02 | 1994-10-06 | Siemens Ag | Leiterplattenanordnung und Verfahren zur Herstellung einer bestückten Leiterplatte |
US5477086A (en) * | 1993-04-30 | 1995-12-19 | Lsi Logic Corporation | Shaped, self-aligning micro-bump structures |
US5400950A (en) * | 1994-02-22 | 1995-03-28 | Delco Electronics Corporation | Method for controlling solder bump height for flip chip integrated circuit devices |
JP2673098B2 (ja) * | 1994-08-03 | 1997-11-05 | インターナショナル・ビジネス・マシーンズ・コーポレイション | プリント配線基板及び実装構造体 |
US5493075A (en) * | 1994-09-30 | 1996-02-20 | International Business Machines Corporation | Fine pitch solder formation on printed circuit board process and product |
US5598967A (en) * | 1995-04-04 | 1997-02-04 | Motorola, Inc. | Method and structure for attaching a circuit module to a circuit board |
-
1996
- 1996-04-19 US US08/635,111 patent/US5738269A/en not_active Expired - Fee Related
-
1997
- 1997-01-24 WO PCT/US1997/001145 patent/WO1997040530A1/en not_active Application Discontinuation
- 1997-01-24 JP JP9538031A patent/JP2000509203A/ja active Pending
- 1997-01-24 EP EP97903096A patent/EP0907963A4/en not_active Withdrawn
- 1997-01-24 KR KR1019980708341A patent/KR100278959B1/ko not_active IP Right Cessation
- 1997-02-04 TW TW086101262A patent/TW321616B/zh active
Also Published As
Publication number | Publication date |
---|---|
WO1997040530A1 (en) | 1997-10-30 |
EP0907963A4 (en) | 2000-07-12 |
US5738269A (en) | 1998-04-14 |
EP0907963A1 (en) | 1999-04-14 |
KR100278959B1 (ko) | 2001-04-02 |
KR20000005541A (ko) | 2000-01-25 |
JP2000509203A (ja) | 2000-07-18 |
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