TW315518B - High density electrical connectors - Google Patents
High density electrical connectors Download PDFInfo
- Publication number
- TW315518B TW315518B TW086100959A TW86100959A TW315518B TW 315518 B TW315518 B TW 315518B TW 086100959 A TW086100959 A TW 086100959A TW 86100959 A TW86100959 A TW 86100959A TW 315518 B TW315518 B TW 315518B
- Authority
- TW
- Taiwan
- Prior art keywords
- path
- groove
- signal path
- ground plane
- signal
- Prior art date
Links
- 239000002184 metal Substances 0.000 claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 238000004377 microelectronic Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 33
- 239000000758 substrate Substances 0.000 description 22
- 238000005452 bending Methods 0.000 description 20
- 238000005530 etching Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000000151 deposition Methods 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 229920000052 poly(p-xylylene) Polymers 0.000 description 3
- 230000008439 repair process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000013013 elastic material Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 238000012777 commercial manufacturing Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 239000006082 mold release agent Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 230000001225 therapeutic effect Effects 0.000 description 1
- 238000007736 thin film deposition technique Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81141—Guiding structures both on and outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8136—Bonding interfaces of the semiconductor or solid state body
- H01L2224/81365—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01077—Iridium [Ir]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
- H05K3/326—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor the printed circuit having integral resilient or deformable parts, e.g. tabs or parts of flexible circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Details Of Connecting Devices For Male And Female Coupling (AREA)
Description
3J55J8 A7 B7 五、發明説明(彳) 發明領域 本發明係有關於—種電性裝ϊ之連接,尤指-種自動對 準,軟性高密度和可調式阻抗電性連接器。 發明背景 :在積體電路領域技術中,要求更快和更密集的系統,在 許多應用中’ &需結合輕重量和密集結構,技術發展趨向 於更複雜的系統’包括愈來愈多的構件並且需要彼此連 接爲了配合新系統在不同構件之間通道迅速會合之需 要’則其系統的不同構件之間路徑長度必需維持在一定的 限度内。 當系統複雜度增加,則在構件之間路徑長度亦增加,爲 了不超過每個構件之間可用的最大距離,該構件必需愈來 愈小並且壓縮得愈來愈密集,因此,發展出多—晶片模 子,即儘可能的壓縮包裝未簡化的IC。 事實上,假如整個系統積體在相同平面上,則不同活性 構件之間距離不大’其最大距離,视執行所需來決定,假 如祇用-個平面連接晶片/構件’則在複雜系統内,需彼 此連接的構件之間不需要太大,因爲僅有在相 同平面内的 經濟部中央棵準局員工消費合作社印装 構件得到最大距離。 三維結構能克服該問題’即’由—構件延中的連接線, 不僅可連接同平㈣構作,亦能直接連通在該平面上或下 、構件w肖些不同的方式:第―,系統具有模予連接 到背平面;第系統包括黏在-起的晶片;第三系統垂 直連接在—維晶片之焉聳的—端上。該三維結構並未解決 ?ί55ΐ8
、發明説明( 2 Α7 Β7 經濟部中央揉準局貝工消費合作社印裝 連接^件=間短路㈣题’域件封閉在空間内並由長線 之^錄 則無法解決,很明顯的,當兩構件依上述 種方法連接在一起,即 F在兩個不同相鄰的多一晶 々视于上,經由一侧面通 一^ ^ ^ ^ ^ 您 ^ 在晶片面上的短垂直路 、’在另一晶片上最後側面通道,形成兩個構件之中心 位置連接,假如使用超過—堆的晶片,則第:個連接方 法亦無法在相鄰晶片之間使用短連接線連接,很容易理 解,假如考慮兩個晶片的例予,彼此相鄰,而是在每一堆 I的頂端上是互相連接的。 對於電子電路增加複雜度時,更.要求在密集的輸入/輸 出-連接不能破壞執行之特性,即,調整阻抗或忽略電 /電容。隨著密度的增加,對準性的要求亦增加,並且网 於高準確性的活性對準成本,要求使用自動對準製造愈形 重要。 當連接複雜系統的部份時,必須取代該系統的一個或更 多個部份以獲得一功能系統的危險性會隨著系統的複雜度 而增加。在相關頻率和操作的條件下,要完全測試機構部 分的困難度亦會加速增加。 使用w#度微折曲時,即使沒有阻抗控制,亦隱含了 表上的阻抗控制。 在歐洲專利案第〇 295 91 4 $3號,Maraco Karnezos,描述了治金的彈性折曲,使用該折曲經由4 夾連接去接觸電性兩面,藉由該彈性,幾乎可將機械經 熱所產生的應力消除,在沒有破壞的情況下可以將接觸 感由 外
S 由面 ——ΊΙ.1Ι丨丨— Γ (請先閲讀背面之注意事項再填寫本頁) ΙΓ丨-ίι·---- Μ^ψ ----------------- 5- 本紙張尺度適用中國國家梯準(CNS ) Α4規格(210><297公釐) A7 B7 經濟部中央標準局貝工消費合作杜印製 五、發明説明( 分開。 發明的簡單説明 本發明係描述一種技術以完成具有阻抗控制的彈性電子 連接器,在架置期間和執行時,具有高密度的連接和高準 確性自動對準,對準功能和電性連接是在相同的結構内, 利用在第一部份的V-型折曲和在其它部份内的v_凹槽來 對準,該凹槽可能爲5角的5面體,或金字塔形狀,其折 曲可能爲去5角5面體頂端或截去金字塔頂端的形狀,其 折曲和凹槽必需有相對的連接路徑。 本發明之基本觀念係使用結構本身來對準,即爲,當對 準結構相對較大時,經由高阻抗控制接觸密集,而得到多 接觸點,該結果能得到高準確性,同時爲彈性連接,本發 明控制使用時,由於熬所造成金屬層或其它層的異位。基 於準確性,連接時要求多個,超過三個彈性的或變形的或 其它的各別接觸點,即,需要所有的接觸點在相同平面幾 乎無法實現。 本發明具有非常高密度滙流排之多一路徑阻抗控制,係 藉由製作金屬線圖案,即路徑,在準確模子彈性折曲上, 並匹配準確姑刻凹槽壁上的阖案線。 本發明亦能夠使用低花費蝕刻和矽微結構技術,在沒有 扇形擴散的情況下,得到可調式阻抗,高密度多一路徑連 接器,i亦能不分開主體下自動對準,並利用前製基板結 構的改變,與在基板上金圖連接的圖案的同時製作。 本發明可使用在各種微電子系統内,例如,小型化高密 CI — (請先閲讀背面之注意事項再填寫本頁) -訂i ,1—1. i m ,6- 五、發明説明() 4 / 度模子,在模子自母板之間,在IC : 8和模子或模子之 間,在三維結構不同層之間,或在基板之間非常高 安置的速接。 在許多案財’统,並^使用烊接或 相等(万法將它們細,這暗示使用連接器,有許多連接 器可用’但並沒有如本連接器密集,具有阻抗控制,頻率 到達數個GHz,非常高密度,且沒有散狀散開現象。彈性 度對毅供时路⑽之制壓力之安全性很重要,即使 用在由不同熱或其它膨脹而產生的尺寸變化或些微的物理 缺陷’均可有效排除。考慮對準性可利用供對準用之接觸 點的許多連接器。料利用非常小尺寸的各別接觸給而 S ’當施加對準時,可能需要高維度的前置對準或可能導 致破壞。利用彈性對準結構和相對應的匹配凹槽取代之, 其上製作類似金屬線之圖案,係由電路延申而來金屬線的 一部份。造暗π在不需要额外空間τ,可得到強勒對準和 非常高的準確性,利用製造接地路徑或平面和在凹槽内的 接觸路徑’並在基板上製造類似接地路徑和在折曲上製造 接觸點而得到連接器結構。以所期待的折曲和凹槽形式, 及愈簡單的步驟,積體接觸點和電線之連接到一般連接圖 製製造。 本發明進-步目的,在純供—種對系統需要非常短的 電子路徑之解決。 本發明進一步目的在於提供—種壓縮包裝系統。 本發明再一目的在於提供—種容易修理的洞孔系統,由 本紙張尺度遠用中國國家標率(CNS ) Α4規格(21〇χ297公兼) A7
^很谷易取代各別部份’因此製料 東西或高度損壞部㈣ T需用任何償値的 贴等等。 ,在附著部份不包括焊接或黏 本發明利用較佳實施例和附圖詳細闡述本發明 囷示的簡單說3月 4 W述本發明。 圖1,係爲二維多-片组件橫截面圖。 :2::::自動對準和可調式阻抗連接器之橫截面圖。 保爲另一種自動對準和具有雙 式^連接器之_面示意圖。雙密度連接器〈了调 :4 ’係爲另—種自動對準和具有經由連接器,接在信 圖。(後的接地路徑之可調式阻抗連接器橫截面示意 圖5,係爲圖3之上視示意圖。 圖6a-b係爲另一種連接器之截面圖。 圖7係爲具有連接器之另—種雙密度連接器橫截面示意 圖。 發明的詳細說明 本發明可以使用在各種微電子系統中,用以供彈性電子 連接和固定晶片對準。它能用在多一片組件内,特別是在 放置之前’對難決定的晶片品質,本發明用來解決目前數 個問题’即’在板和晶片之間不同的熱膨脹係數所產生的 同難度匹配,修復是危險的且費用高,特別是對MCM式 樣而言,修復是不可能的。 圖1係説明利用本發明之一個例子,但並非限制本發 ) (Tiox297^-¾ ) 315518 A7 B7 五、發明説明 6 經濟部中央樣準局貝工消费合作社印製 明,本發明能用在任何一種微甚至次微的系統中,圖1係 説明三維(3D)多片組件100之截面示意圖;該3D组件利 用二維(2D)而形成,多片组件包括矽基板106-114,和 放置其上的積體電路晶片122_136。該矽基板1〇6_114提 供有一接地平面因此在整個3]□多晶片組件100上,組件 的不同平面之間具有良好的屏蔽,在基板1〇6_114上,特 別是不位在頂1〇6或底114上的多片組件,亦放置虛晶 片’通路晶片或通路116-121連接3D多片組件1〇〇之相鄰層。 爲了得到阻抗匹配連接器,使用V字型凹槽蝕刻連接凹 槽2 0 2 ’如圖2所示,在通路晶片i丨6 2 j頂上提供彈性 折曲結構206,並且製造在v字型接觸凹槽202之基板背 面’用以容易得到裝配/分解之連接並得到好的對準,請 參看專利應用領域“供積體電路用之包裝結構”。 在本發明之實施例中,1C晶片122_136和通路晶片 116 -121之倒裝片放置在基板106-U4上。如此的安排, 儘可能在放置1C晶片122-13 6之倒裝片背面和相鄰的基 板106-114背面之間,提供好的熱接觸。 利用提供給頂端冷卻器102之頂平面138和基板之底端 冷卻器104之底平面140 —壓縮力142,而保持3D多片组 件100的各別通路晶片116-121和各別ic晶片122-136的 每一層在一起。 爲了實現該堆疊結構,提供彈性折曲連接通路晶片 U6-121和相鄰的基板106-114平面,並經由壓縮冷卻器 -9 ·Λ s (請先閏讀背面之注意事項再填寫本頁) nn nn
A ---訂 線·Γ----:-I. ·ϋ 五、發明説明( A7 B7 經濟部中央樑準局員工消費合作社印製 102和104之頂端平面138和底端平面14〇而使得组件連 接在一起。利用嵌合方式提供組件1〇〇之外圍部份一壓縮 力 142。 利用製造金屬層圖案以建立並連電壓型式,非永久性 的,可調式阻抗連接以供高速資料傳輸。 囷2係説明連接器結構2〇〇橫截面示意圖,第一部份 2〇4包括.兩層金屬層結構,第一信號路径2丨2和第一接 地路徑或平面21Q,其間爲介電質,爲—非等問性¥_凹槽 202,第二部份208包括:相對應金屬層,第二接地平面 226,和第二信號路徑224,覆蓋在彈性曲折2〇6上,並 匹配V-凹槽202 ,當第一和第二部份2〇4和2〇8在一起 時、’則第一和第二信號路徑212和224彼此連接在一起。 當放在一起,該連接自動對準,請參看應用專利領域“凹 槽折曲以供彈性放置,,。由於彈性折曲2〇6,即使產生 位仍維持電性接觸,例如,由熱膨脹所引起的異位。如 2所不之第一和第二信號路徑212,224,結構暗示雙 安全,因爲相同路徑分別覆蓋在彈性折曲2〇6和v_凹 202兩面壁上。換句話説,假如發生大異位,和折曲206 的邊接觸V凹槽202 ,仍然可維持電性接觸。第一和第 =接地路徑或平面210,226包括任何適合的金屬,第一 仏號路徑金屬212表面必需不能產生絕緣的氧化層,即任 何貴重金屬才可用,第二信號路徑金屬224必需爲延展 好的金屬,且其表面不能產生絕緣的氧化層,即金具有 特性。利用介電質層214和216將路徑和接地金屬層分 異 倍 槽 性 此 (請先M-讀背面之注意事項再填寫本頁) -----C! 、π*_ m ·
經濟部中央揉準局貝工消費合作社印裝 A7 B7 五、發明説明(8 ) 開。第一介電層214包括任何介電層共形地覆蓋在v_凹槽 壁上,即聚對苯二甲基。第二介電層224包括任何介電 層,或與在折曲206内相同的彈性材料。 本發明基於高準確性,兩部份的任何功能的彈性對準, 同時使用彈性折曲以供高準確性的對準和靈活的,彈性的 電子連接器使用,利用製作金屬層圈案以建立並連電壓型 式,非永久性連接,該連接爲可調式阻抗用以供高速資料 傳輸。 當使用S i ( 1 0 0 )晶片之非等向性蝕刻以製作對準凹槽 202,將得到大部份準確對準,像是,僅由使用:非等向 性蝕刻(1 0 0 )矽晶片和高準確性蝕刻,適合的覆上脱模劑 層,和矽化合物,以形成最佳的彈性折曲2〇6。在類似專 利應用領域“製作彈性折曲方法,,和“凹槽折曲以供彈性放 置”中,詳細描述如何製作折曲和凹槽及對準等。當製作 V-凹槽20 2和截去頂端折曲2〇6時,藉由如放置在凹槽 202遇邊内折曲206頂端的一些前置-對準,將部份截去頂 端折曲放入凹槽202内,再經施,壓218,. 220,(可能爲重 力),使得折曲之斜面壁23〇,232靠在222,22S斜壁 上,得到在平行於折曲206或凹槽2〇2之基礎面方向之準 確對準,而使得折曲206對準凹槽2〇2,並且利用蝕刻在 凹槽202内之相關折曲206,使其自動對準,並使路禝 212,224以高準確性被放置,利用折曲2〇6之彈性,路 径212和214在不考慮由於微晶所導致的金屬粗輪度不同 而造成微小的厚度差下,其接觸相符。當然,由於彈性 -11 - 本紙張尺度逍用中國國家樣準(CNS ) A4^格(210X297公釐) —^—Η-----A------訂,—----線〈 (請先閱讀背面之注$項再填寫本頁) ά.". ;»把,: A7 B7 經濟部中央標準局貝工消費合作社印製 . 五、發明説明( 度,發生在部份204,208之間微小的膨脹差亦不會造成 失去接觸或曝露部份204,208造成嚴重的應變。 在此描述如何製造接觸器,一個抛光(1〇〇)矽晶片,該 晶片來自模子晶片,其上沈積一層光阻後,再蓋上一層 S iN,然後利用光罩對準相關的模子晶片之晶軸方向製造 圖案0 利用光軍定義開口然後蝕刻S i N層,然後對模子晶片曝 光形成非等向性蝕刻,利用矽{111}平面來限制所產生凹 槽的斜壁,持續蝕刻,直到完成,蝕刻結構以形成截去頂 端和延長的結構。 利用一種類似但爲鏡像,具有高準度之光罩,利用相同 之製程,重覆使用該第一光罩,在晶片内得到類似但能被 對準的鏡像凹槽’該凹槽必需與第一晶片之凹槽同樣深或 更深,其模子晶片可能包括一些對準結構,而使得它能自 動對準模製彈性折曲上之基板。在模予晶片上覆蓋一些脱 模劑’以非常薄和流順的沈積在其上,以保持準確的地勢 形狀,利用最合理的製程產生金屬和介電層爲折曲的一部 份,在未分開的基板或模子晶片上覆蓋一層療治的彈性混 合物,並利用旋轉,刮平或噴灑以控制其厚度,允許混合 物弄濕相反面,然後利用對準特性對模子晶片和未分開的 基板加壓,而使得折曲對基板結構準確對 在眞空中移走氣泡包裝,而後再提高溫度以治放 而後將模子晶片與基板分開,由於半固化的混合物可成 模’在眞空中固化模子晶片和基板。對料別的應用中, ,. T— 訂一 ^ ~~ 線( (請先閎讀背面之注意事項再填窝本頁) -12- «5518五、發明説明(10 ) 經濟部中央梯率局貝工消費合作杜印裝 利用軟性材質製造基板可有利分離。 對於最合理的製程,在折曲結構部份,首先產生金屬層 226和介電質層214,然後製作折曲,再在折曲上製造分 離金屬路徑224之圖案,並經由通道接觸先前的金屬層。 理論上,有可能先製造接地路徑或平面,然後沈積金屬和 介電質在折曲上。無論如何除了通過折曲下方之通路線或 接地平面機率外,並不是各種介電質和金屬路裎均能足夠 彎曲在f曲的折曲上。 利用光蝕刻光軍對準已存在的結構上,即,雷射或比 或分開之前的基板,利用非等向性蝕刻或技術製造凹槽, 凹槽部份2 04以正常製造方法製作,即,沈積金屬層21〇 和介電質層214, 一致的沈積期待的介電質層214和金屬 路徑212圖案,以維持凹槽2〇2的對準性,當然,適當的 沈積光阻以得到在光阻上滿意的曝光圖案解析度和滿意的 曝光儀器焦距深度。 分離凹槽之後,被放在折曲部份上,和折曲自動對準凹 槽,视折曲的形狀和尺寸和凹槽的前置對準變化角度而 定0 理論上,有可能先製作一般的沈積和製作介電層和金屬 路控的圖案,然後從凹槽的範圍上蚀刻掉金屬和介電質, 蝕刻凹槽並製囷案,進一步,利用前置沈積並製作金屬路 徑和介電質和光阻圖案,但僅能在局部使用。 利用外來壓力而非永久附著方式將部份组件融合在一 起,並很容易的從對準結構分離該部份以供更換或修補。
(請先閲讀背面之注^ih項再填寫本1) J—
A -訂* A7 -----£ 五、發明説明(”) 在折曲外部之薄的模子材料部份,形成通道到金屬路 徑,而使其與折曲非常緊密的接觸。 圖3係説明第一變化的實施例,該圖顯示出具有雙倍密 度連接器之可能性。該製造方法步驟和材料與圖2所^述 的是一致的,無論如何,如圖3所示的例子,在折曲和凹 槽的每一面上有兩個不同的路徑,該路徑圖案亦在圖5中 之滙流排接觸之頂視圖中有所説明β 在圖4中描述本發明第二個變化實施例,除了接地平面 經由通道連接到信號線層上外,其製造過程步樣和材料與 圖2所描述的一致,圖4係説明自動對準和具有接地路徑 (穿過連接器接在信號路徑之後)之可調式阻抗連接器之横 截面示意圖,爲了完成基本的電性執行,使用相同的彈性 折曲,將信號線和接地平面連接在必需的相同位置上。 圖5係爲圖3之變化實施例,具有雙倍密度連接器之自 動對準和可調式阻抗連接器之上视示意圖。 圖6a-b係爲變化連接器6〇〇之橫截面示 該 -具有第-部份6。2和第二部份6〇4,如圖二器 部份延著部份602之邊緣具有信號路徑6〇6,在第一部份 的底部連接到接觸腳612。第二部份6〇4在基板614上具 有導架61〇和延著導架61〇的信號路徑,該兩部份在結構 上,每一部份至少有一邊緣具有倾斜壁616,618。假如 提供晶片傾斜壁,則具有延伸在傾斜壁上路徑之正常接腳 將被交換,並且如早期所述其導架和金屬路徑圖案融合在 —起0
修正前所述讀佳實施例,但會損失—鲜確性,其 曲的形狀可與凹槽不同,如此,其一可以不使用非等向性 蚀刻:而是其它的蚀刻或加工,如此凹槽和折曲並不需要 有相同的形狀,祇要折曲能匹配凹槽即可,以自動對準方 式製造接觸,其混合物除了矽外,如:聚氨酯或—些其它 彈性的或半導性的混合物。 藉由重覆使用數個步驟,能製造”曲模子,在損失正_ 確性下,很容易將模子與基板分離。 假設金屬圖案解析度超過較佳實施例中之一維空間内 (即接近線性空間)所給最高接觸密度之折曲最小尺寸,假 如折曲最小尺寸相等於金屬圖案解析度,則有可能在每單 訂 位面積内得到更高的接觸密度,在此案例中,自動對準在 密集表面上的多微折曲’其中金屬圖案不是在折曲上 在折曲外部。 在此案例中’㈣非常小的折曲尺寸,其連接有可能被 阻抗控制’無論如何’對於如折曲之頂尖部份很難前置對 準到非常小的凹槽週圍内,除非在此結構内也有一些粗大 的對準特徵。 — 經濟部中央揉準局員工消費合作社印装. 假如彈性材料能“較佳地,,沈積在凹槽的壁上,以取代 固化的折曲。有可能利用模子來完成,在部份模子内充入 混合物,但並不是對所有的凹槽壁之間留有很薄的距離, 用此方式可以治癒:彈性混合物。 有數個可能的應用供本發明連接用,完成在相同平面内 IMCM : s之間的滙流排接觸,結合穿過一洞孔通道完成 -15-本紙張减朝巾關家標準(CNS )八4祕(2T〇729tIF) 五、發明説明( 13 A7 B7 經濟部中央棣準局貝工消費合作衽印製 在堆疊MCM : s之間的垂直信號傳輸,結合所需的不同配 置圖能當成一般細微節距高頻連接器,當維持正確的特性 阻抗,比起傳統電子其單位連接所需空間較少,主要是由 於精細節距和高度對準,並且,該接地平面具有接觸點。 除了標準的技術製程供電子裝置製造,該連接器裝置需 要更步製造,如V-凹槽蝕刻,折曲的鑄造,絕緣層的 沈積和整個步驟的蝕刻,利用現行或模子半導體/薄膜製_ 程來完成ΰ '爲了得到最大的準確度,必需在模子上覆上一層非常滑 順和薄的脱模劑,其方法如上所描述之方法,對於表面單 晶對晶體方向有好的對準,其最大準確度能供商業矽一晶 片之非等向性蝕刻用。 比起凹槽和折曲之地勢和厚度,需要將介電金屬和光阻 層沈積的更滑順,對於金屬層之沈積,係利用標準薄膜沈 積技術沈積,對於介電層而言,受限於所選擇的材料,較 不使用旋轉鍍膜法。不過,然有數種材料和製造方法可 用,如聚對苯二甲基(Parylene)方法,利用旋轉塗佈沈 積光阻,其光阻的選擇會更少,在此案例中不視爲可行, 仍有兩種選擇可用,一種係利用在眞空中蒸鍍新的光阻材 料,該方法沒有實質的商業製造效益,但存在有商業效益 的材料,其光阻特性能用該方法沈積。另一種光阻形式的 變化係利用電鍍,具有商業價値,並且保護在印刷電路板 上之穿過一平板通道内之金屬。該電鍍光阻需要金屬層加 編壓以長成光阻,在此案例中,僅爲金屬層需印刷制圖在
(請先閲讀背面之注意事項再填窝本頁) r! ·、ΤΓΙ 14 14 經濟部中央裸準局員工消費合作杜印裂 五、發明説明 折曲上和凹槽内,需要對介電層製圖以得到通道,但不是 在折曲士或凹槽内,而是在其外部,甚至對非常不平的表 面’亦用傳統的光阻覆在孔洞或凹槽内以供製圖,除 亦有可能沈積和製圖出—個硬的金屬光罩以供介電層 製定圖案用。 · 、利用微機械技術,顯示㈣高密度連接器能產生如傳統 連接器相似之精微部份,但尺寸會小得更多,理論上,邊 緣型式連接器和外軍,是如此的小,係不會將線性圈案或 扇狀散開。無論如何,不需要製造冶金的積體部份,而是 以焊接將分開部份接合,至於強度和雜電阻則很少被知道。 彈性折曲顯示用來當信號路徑之目地,每—個路徑有一 個與基板相反面接合在一起的分離折曲,理論上,在不會 扇狀散開的情沉下,儘量小,在此案例中,也考慮阻抗控 制,無論如何,該圖像缺乏對準固有的意義。 需要解析分開的微小部份,’必需各別掌控準確性,而非 如其它較便宜的薄膜製造方式,有許多預置項利用蝕刻方 法產生。 圖7係説明另一種連接器折曲7〇〇橫截面示意圖,該連 接器包括:二個金屬層結構,—介電層704,和彈性結構 216,該金屬層結構可成爲接地路徑或平面7〇2和—信號 路徑706,接地平面702製造在折曲2〇6上,其折曲包括 在'彈性結構216内,通過介電層704上接地平面有—連 接,並部份覆在介電層704上,其它的金屬層結構,信號 路徑706製造在介電層704上。 17- 本紙張尺度適用中國國家揉準(CNS ) A4規格(210X297公釐) ---1 — Λ----- I ^------ (請先S讀背面之注意事項再填寫本頁) . A7 B7 五、發明説明(15 ) 爲闡述本發明以具體化描述之,些許的不同並不脱離本 發明之精神或要義所在,因此,全面的考慮和説明本實施 例,而非限制本發明,藉由揭露專利範圍以指出本發明之 範園,所有在相等於申請專利範圍和意義内之改變亦包括 在其中。 -ml I An j (請先閱讀背面之注意事項再填寫本頁) 訂>· 經濟部中央梂準局員工消費合作社印製 -18- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)
Claims (1)
- ®155l8 A8 B8 C8 D8 申請專利範圍 經濟部中央#準局貝工消費合作杜印製 1-種連接器包括:.至少第一部份和第二部份,第一和第 二部份的每一部份至少有一斜壁,其特徵在於:第一部 份斜壁(228,616)和第二部份斜壁(23〇,41S)具有相同 的傾角,第一部份至少有一個傳導路徑(212,606)和第 二部份至少有一個傳導路徑(224,6〇8),其中,當第一 和第二部份匹配在一起時,其傳導路徑會彼此接觸。 2_根據申请專利範固第1項所述之連接器,其中,第一部 份有V-凹槽,第二部份有隆起物(bulnp),在V-凹槽内 (2〇2)至少有一傳導路徑(212),在隆起結構(2〇6)内至 少有一傳導路徑(224),且該隆起物匹配到\^_凹槽内, 其中當第一(2 0 4)和第二(2 0 8)部份匹配在一起時,其 傳導路徑與其它傳導路徑接觸。 3_根據申請專利範圍第2項所述之連接器,其特徵爲:第 —部份(204)有一個雙金屬層結構,至少一個第—傳導 路徑>(212) ’和至少一個.第一接地平面(21〇),其中, 金屬層覆蓋在V-凹槽(202)上。 4·根據申請專利範圍第2項所述之連接器,其特徽爲:第 二部份(208)有一個雙金屬層結構,至少一個第二信號 路徑(224),和至少一個第二接地平面(226),其中, 信號路徑部份覆蓋在折曲(206)上。 5.根據申請專利範圍第2項所述之連接器,其特徵爲:第 二部份(208)有一個雙金屬層結構,包括至少—個傳導 路徑(706),至少一個接地平面(7〇2)和一個介電媒介 (704),其中接地平面和傳導路徑係製造在隆起物(2〇6> -19 本紙張^適用中國國家揉準(CNS )八顿^ ( 210X297公釐 〈請先聞讀背面之注項再填寫本肓) C 奸· 線r經濟部中央揉準局貞工消費合作社印製頂端上,且利用介電媒介將傳導路徑與接地平面分開。 6·根據中請專利範圍第21|所述之連接器,其特徵爲·傳 導路徑包括金屬層,爲雙部密度,第一部份少 有一個第一信號路徑(3 〇6)、和至少一個 叫)和至少有-個第-接地平面(302),其中,3 層覆在V-凹槽(2〇2)上,第二部份(2〇8)至少有一個第 二信號路徑(3 08),至少有一個第4信號路徑(312),和 至少有-個第二接地平面(3G4),其中,信號路徑部份 覆在隆起物(206)上,當第一和第二部份匹配時,第一 和第三信號路徑(3 06,3〇4)舆第二和第四信號路徑 (3 10,3 12)接觸。 7·根據中請專利範圍第2項所述之連接器,其特徵爲:傳 導路徑包括金屬層,爲雙部密度,第—部份(2G4)至少 有一個第-信號路徑(4G2),和至少有—個第—接地路 徑(406),其中第一信號路徑部份覆在v_凹槽(加) 上’:二部份(208)至少有一個第二信號路徑(4〇8)和 第二接地路徑(4G8),其中,金屬層覆在隆 一 2〇6)上,因此,第二接地路徑覆在V-凹槽上,當 第:和第二部份匹配時,第一和第二信號路徑與第一和 第二接地路禋接觸。 請 先 閲 之 注 3 旁 訂本紙張歧逋用中國國家榡率(CNS〉从絲(21〇><297公着)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9604677A SE516011C2 (sv) | 1996-12-19 | 1996-12-19 | Tätpackade elektriska kontaktdon |
Publications (1)
Publication Number | Publication Date |
---|---|
TW315518B true TW315518B (en) | 1997-09-11 |
Family
ID=20405043
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086100959A TW315518B (en) | 1996-12-19 | 1997-01-29 | High density electrical connectors |
Country Status (11)
Country | Link |
---|---|
US (1) | US6042391A (zh) |
EP (1) | EP0951739B1 (zh) |
JP (1) | JP3954111B2 (zh) |
KR (1) | KR20000069419A (zh) |
CN (1) | CN1145216C (zh) |
AU (1) | AU5505598A (zh) |
CA (1) | CA2275632A1 (zh) |
DE (1) | DE69736488T2 (zh) |
SE (1) | SE516011C2 (zh) |
TW (1) | TW315518B (zh) |
WO (1) | WO1998027596A1 (zh) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6166437A (en) * | 1999-04-12 | 2000-12-26 | International Business Machines Corporation | Silicon on silicon package with precision align macro |
US6411754B1 (en) | 2000-08-25 | 2002-06-25 | Corning Incorporated | Micromechanical optical switch and method of manufacture |
US6495396B1 (en) * | 2001-08-29 | 2002-12-17 | Sun Microsystems, Inc. | Method of coupling and aligning semiconductor devices including multi-chip semiconductor devices |
EP1782078B2 (en) * | 2004-06-21 | 2019-10-16 | Capres A/S | Method and apparatus for providing probe alignment relative to supporting substrate |
US7618844B2 (en) * | 2005-08-18 | 2009-11-17 | Intelleflex Corporation | Method of packaging and interconnection of integrated circuits |
DE102007027434A1 (de) * | 2007-06-14 | 2008-12-18 | X-Fab Semiconductor Foundries Ag | Verfahren zur Herstellung von Justagestrukturen für eine strukturierte Schichtabscheidung auf einem Mikrosystemtechnikwafer mittels einer Beschichtungsmaske |
KR100951456B1 (ko) * | 2007-12-26 | 2010-04-28 | 아이볼타(주) | 전기 접속 시스템 |
US7741652B2 (en) * | 2008-03-07 | 2010-06-22 | Visera Technologies Company Limited | Alignment device and application thereof |
US9136259B2 (en) * | 2008-04-11 | 2015-09-15 | Micron Technology, Inc. | Method of creating alignment/centering guides for small diameter, high density through-wafer via die stacking |
US9786584B2 (en) * | 2012-09-04 | 2017-10-10 | Infineon Technologies Ag | Lateral element isolation device |
US9017092B1 (en) | 2014-05-07 | 2015-04-28 | Microsoft Technology Licensing, Llc | Electronic connector |
US9728915B2 (en) | 2015-05-19 | 2017-08-08 | Microsoft Technology Licensing, Llc | Tapered-fang electronic connector |
US11495560B2 (en) * | 2015-08-10 | 2022-11-08 | X Display Company Technology Limited | Chiplets with connection posts |
US10468363B2 (en) | 2015-08-10 | 2019-11-05 | X-Celeprint Limited | Chiplets with connection posts |
US9660380B1 (en) | 2016-01-22 | 2017-05-23 | Microsoft Technology Licensing, Llc | Alignment tolerant electronic connector |
US9705243B1 (en) | 2016-02-12 | 2017-07-11 | Microsoft Technology Licensing, Llc | Electronic connector with C-shaped tapered extension |
US10750614B2 (en) * | 2017-06-12 | 2020-08-18 | Invensas Corporation | Deformable electrical contacts with conformable target pads |
US10511127B2 (en) | 2018-03-20 | 2019-12-17 | Microsoft Technology Licensing, Llc | High-speed electronic connector |
WO2019242752A1 (zh) * | 2018-06-21 | 2019-12-26 | 矽创电子股份有限公司 | 凸块结构 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3553633A (en) * | 1966-02-28 | 1971-01-05 | Albert A Ondrejka | Multi-contact separable electrical connector |
US3465435A (en) * | 1967-05-08 | 1969-09-09 | Ibm | Method of forming an interconnecting multilayer circuitry |
US4813129A (en) * | 1987-06-19 | 1989-03-21 | Hewlett-Packard Company | Interconnect structure for PC boards and integrated circuits |
US5121299A (en) * | 1989-12-29 | 1992-06-09 | International Business Machines Corporation | Multi-level circuit structure utilizing conductive cores having conductive protrusions and cavities therein |
CA2034703A1 (en) * | 1990-01-23 | 1991-07-24 | Masanori Nishiguchi | Substrate for packaging a semiconductor device |
US5071363A (en) * | 1990-04-18 | 1991-12-10 | Minnesota Mining And Manufacturing Company | Miniature multiple conductor electrical connector |
US5118299A (en) * | 1990-05-07 | 1992-06-02 | International Business Machines Corporation | Cone electrical contact |
US5180311A (en) * | 1991-01-22 | 1993-01-19 | Hughes Aircraft Company | Resilient interconnection bridge |
US5097101A (en) * | 1991-02-05 | 1992-03-17 | Tektronix, Inc. | Method of forming a conductive contact bump on a flexible substrate and a flexible substrate |
CA2135241C (en) * | 1993-12-17 | 1998-08-04 | Mohi Sobhani | Cavity and bump interconnection structure for electronic packages |
DE4438053C2 (de) * | 1994-10-25 | 2002-05-02 | Harting Elektrooptische Bauteile Gmbh & Co Kg | Verfahren zum Herstellen einer elektrisch leitfähigen Struktur |
US5743747A (en) * | 1997-01-13 | 1998-04-28 | Hughes Electronics | Dimpled connector |
-
1996
- 1996-12-19 SE SE9604677A patent/SE516011C2/sv not_active IP Right Cessation
-
1997
- 1997-01-29 TW TW086100959A patent/TW315518B/zh active
- 1997-12-19 JP JP52763098A patent/JP3954111B2/ja not_active Expired - Fee Related
- 1997-12-19 DE DE69736488T patent/DE69736488T2/de not_active Expired - Fee Related
- 1997-12-19 US US08/994,985 patent/US6042391A/en not_active Expired - Fee Related
- 1997-12-19 WO PCT/SE1997/002178 patent/WO1998027596A1/en active IP Right Grant
- 1997-12-19 CA CA002275632A patent/CA2275632A1/en not_active Abandoned
- 1997-12-19 KR KR1019997005197A patent/KR20000069419A/ko not_active Application Discontinuation
- 1997-12-19 CN CNB971808694A patent/CN1145216C/zh not_active Expired - Fee Related
- 1997-12-19 AU AU55055/98A patent/AU5505598A/en not_active Abandoned
- 1997-12-19 EP EP97951404A patent/EP0951739B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69736488D1 (de) | 2006-09-21 |
CN1145216C (zh) | 2004-04-07 |
EP0951739B1 (en) | 2006-08-09 |
KR20000069419A (ko) | 2000-11-25 |
SE9604677D0 (sv) | 1996-12-19 |
CN1241297A (zh) | 2000-01-12 |
JP2001506414A (ja) | 2001-05-15 |
DE69736488T2 (de) | 2007-03-15 |
EP0951739A1 (en) | 1999-10-27 |
SE9604677L (sv) | 1998-06-20 |
AU5505598A (en) | 1998-07-15 |
SE516011C2 (sv) | 2001-11-05 |
US6042391A (en) | 2000-03-28 |
CA2275632A1 (en) | 1998-06-25 |
WO1998027596A1 (en) | 1998-06-25 |
JP3954111B2 (ja) | 2007-08-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW315518B (en) | High density electrical connectors | |
US7388388B2 (en) | Thin film with MEMS probe circuits and MEMS thin film probe head using the same | |
US7459795B2 (en) | Method to build a wirebond probe card in a many at a time fashion | |
TW463280B (en) | Method of producing a contact structure | |
US9281268B2 (en) | Method for fabricating multi-chip module with multi-level interposer | |
JP2016051834A (ja) | プリント配線基板およびその製造方法 | |
JP2002520864A (ja) | プリント回路基板用相互接続アセンブリ及び製造方法 | |
JP3984773B2 (ja) | 半導体装置 | |
US7911048B2 (en) | Wiring substrate | |
TW518916B (en) | An contact element in an interconnect assemblies and a method for forming the same | |
KR100455499B1 (ko) | 반도체 장치를 검사하기 위한 프로브 및 그 제조 방법 | |
JP3379699B2 (ja) | プローバの製造方法 | |
US20080003819A1 (en) | Laser isolation of metal over alumina underlayer and structures formed thereby | |
US7442560B2 (en) | Method for manufacturing anisotropic conductive sheet | |
TW200427138A (en) | Electrical connector and method for making | |
KR100493090B1 (ko) | 배선접속장치 및 그 제조방법 | |
KR20000059158A (ko) | 프로브, 프로브 카드 및 프로브의 제조 방법 | |
JP2023065290A (ja) | 埋め込みパッケージ構造及びその作製方法 | |
JP2002040051A (ja) | プローブカード | |
JP2019071322A (ja) | 配線基板、電子装置、及び、配線基板の製造方法 | |
TW201216808A (en) | Structure of metal lines in multi-layer substrate | |
JPH09106707A (ja) | 異方性導電シート及びその製造方法 |