201216808 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種多層基板金屬線路結構，尤指一種適用 於軟性多層基板之多層基板金屬線路結構。 【先前技4舒】 現今任何類型電子產品之小型化，係無可避免之趨勢，隨 著半導體晶圓製程尺寸不斷地縮小’後段封裝之相關技術亦必 須隨之朝微型化的方向進步。因是，當今積體電路的積集度已 不斷地提高，其中使用多層基板用以對各種元件進行封裝，整 合成高密度系統已為必然之趨勢。而依據業界之現行作法，均 以银刻法或增層法來製作多層基板之金屬線路。多層基板的電 路積集度越高’金屬線路的尺寸要求便越精細。 請參考第1圖，係繪示習知技術以蝕刻法製造金屬線路之 簡單示意圖。表示於一多層基板之介電層100上，先形成一金 屬層’塗佈光阻104並曝光後’以钮刻法形成金屬線路1 〇2之 狀態。業界一般均係以濕姓刻法製造金屬線路，由於濕姓刻之 等向性必然產生如第1圖中箭頭所示，對金屬線路1〇2側表面 亦產生触刻’造成金屬線路產生底切（undercut)結構，並且受限 於金屬晶粒（Grain)的大小’造成金屬線路粗縫之側表面。惟當 因應積體電路的積集度不斷提高之趨勢，金屬線路精細度之要 求隨之不斷提高時，由於前述於金屬線路結構底切、側表面粗 糙之缺點’前述蝕刻法係已無法滿足現今金屬線路精細度之要 求。 再者’製造多層基板時，係使用銅作為金屬線路之材料， 於製作介電層或其他製程時，容易受到侵蝕或污染，特別是以 201216808 聚醯亞胺（Polyimide)作為介電層材料時，如欲於金屬線路之表 面包覆一保護作用之包覆金屬層，避免受到多層基板其他材質 的侵蝕或污染’提高金屬線路之可靠度，蝕刻法必須以額外的 曝光、蝕刻製程方能製作包覆該金屬線路之包覆金屬層，而額 外的曝光、蝕刻製程便可能因金屬線路與包覆金屬層位置對準 之準確性要求’增加製造多層基板金屬線路失敗的可能性同 時亦增加多層基板之製造成本。並且，習知技術之蝕刻法並無 法以一次曝光製程即於金屬線路之側表面，甚至底面形成包覆 金屬層’亦即無法藉由完全地包覆金屬線路，來提高金屬線路 之可靠度’亦無法製作可作為同軸導線應用之金屬線路。 請參考第2A圖至2D圖，係繪示習知技術以增層法製造多 層基板金屬線路之示意圖。第2A圖表示於一多層基板之介電 層100上’先形成一非常薄的金屬層102。第2B圖表示於該預 疋位置以外塗佈一光阻1〇4後，再於該預定位置表面增生一金 屬層（例如.以電鑄法，Electr〇plating)。第2(：圖表示移除光阻 104後之介電層1〇〇以及金屬層1〇2。第21)圖表示對金屬層 進行蝕刻，以移除該預定位置之外的金屬材料，而由於濕蝕刻 法之等向性，亦必然產生如第2圖中箭頭所示，對金屬線路1〇2 侧表面產生蝕刻，並且受限於金屬晶粒（Grain)的大小，造成金 屬線路粗縫之表面。 是以’無論是姓刻法或增層法，均受限於金屬晶粒（Grain) 的大小，金屬線路側表面必然具有一定的粗糙度，而當金屬線 路的尺寸要求越精細時，此缺點便會限制金屬線路之精細度。 、無DW疋飯刻法或是增層法，均無法以一次曝光製程即於金 屬線路之上表面、側表面’甚至底面形成包覆金屬層，而完全 201216808 地包覆金屬線路，提高金屬線路之可靠度。 因此’若能發展一種多層基板金屬線路製造方法及其結 構’能以一道曝光製程即於金屬線路之上表面、側表面，甚至 底面形成包覆金屬層，則能製作精細、可靠度高之金屬線路， 同時亦能製作作為同軸導線應用之金屬線路。 【發明内容】 本發明之主要目的在於提供一種多層基板金屬線路結 構，能以一道曝光製程即於金屬線路之上表面、側表面形成上 包覆金屬層甚至底面形成下包覆金屬層。 本發明之另一目的在於提供一種多層基板金屬線路結 構，忐避免爻到多層基板其他材質的侵蝕或污染，製作精細、 可靠度高之金屬線路。 為達成本發明之前述目的，本發明之多層基板金屬線路結 構包含一金屬線路以及一上包覆金屬層。金屬線路係位於介電 層上之預定位置。上包覆金屬層則形成於金屬線路之上表面以 及兩側表面，甚至於底面形成一下包覆金屬層，用以保護金屬 線路，且如上下包覆金屬層完整包覆金屬線路之上表面、兩側 表面以及底面，於金屬線路與上下包覆金屬層間，更形成上下 包覆介電層’金屬線路、上下包覆介電層、上包覆金屬層以及 下包覆金屬層則可作為一同軸導線之應用。相較該預定位置以 外之介電層，該預定位置之介電層係為一下陷之構造，以增加 金屬線路對介電層之附著強化。 依據本發明之多層基板金屬線路製造方法，能僅以一道光 罩製程即製作金屬線路及其包覆金屬層，且並非使用習知技術 之银刻法或增層法，不會對金屬線路側表面產生㈣，而能滿 201216808 足現今金屬線路精細度之要求。並且，本發明之製造方法係於 金屬線路之上表面以及兩側表面、甚至底面形成上下包覆金屬 層’能完全保護金屬線路’避免受到侵蝕或污染，而提高金屬 線路之可靠度’同時亦能作為同軸導線之應用。是以，能進一 步提昇多層基板之金屬線路密度。本發明之多層基板金屬線路 製造方法亦適用於具有可變形或可撓曲特性之軟性基板。 【實施方式】 請參考第3A圆至3E圖，係繪示本發明多層基板金屬線路 製造方法之第一實施例及其結構之流程圖。第3A圖表示於一 介電層300表面塗佈至少一光阻層3〇4。第3Β_表示塗佈光阻 層3〇4後，對金屬線路之一 預定位置以外之光阻層301進行曝 光之步驟。第3C圖表示去除位於預定位置之光阻層3〇ι之步 驟’而由於本實施例係選用負型光阻，當使用顯影劑⑼油㈣ 去除光阻層3(U時’由於光阻層綱上方之光阻層受光程度較 下方之光阻層為多，因此與預定位置相鄰之光阻層304邊緣會 形成如时所示上側較下側突出之結構。然而，本發明並非限 於使用負型光阻，使用雙層光阻等之方法亦可，例如：塗佈雙 由於上層光阻層與下層光阻層顯影速率不同 上側較下側突出之結構。第201216808 VI. Description of the Invention: [Technical Field] The present invention relates to a multilayer substrate metal wiring structure, and more particularly to a multilayer substrate metal wiring structure suitable for a flexible multilayer substrate. [Previous technology] The miniaturization of any type of electronic products today is an inevitable trend, and the size of semiconductor wafers continues to shrink. The technology of the latter package must also move toward miniaturization. Because of the increasing integration of today's integrated circuits, the use of multi-layer substrates for packaging various components has become an inevitable trend in the synthesis of high-density systems. According to the current practice in the industry, the metal circuit of the multilayer substrate is produced by the silver engraving method or the layering method. The higher the circuit integration of the multilayer substrate, the finer the size requirements of the metal wiring. Referring to Figure 1, a simplified schematic diagram of a conventional process for fabricating metal lines by etching is shown. On the dielectric layer 100 of a multilayer substrate, a metal layer 'coating photoresist 104 is formed and exposed, and the metal line 1 〇 2 is formed by a button method. In the industry, the metal circuit is generally manufactured by the wet surname method. The isotropic nature of the wet surname is inevitably generated as shown by the arrow in Fig. 1, and the surface of the metal line 1〇2 is also inscribed. The undercut structure is limited, and is limited by the size of the metal grain (the size of the metal grain) causing the side surface of the metal line. However, when the demand for the fineness of the metal circuit is continuously increased in response to the increasing tendency of the integrated circuit, the aforementioned etching method cannot satisfy the current etching process due to the disadvantages of the undercut and the side surface roughness of the metal wiring structure. Metal line fineness requirements. Furthermore, when manufacturing a multilayer substrate, copper is used as a material for the metal wiring, which is susceptible to erosion or contamination during the fabrication of the dielectric layer or other processes, especially when 201216808 Polyimide is used as the dielectric layer material. If the surface of the metal circuit is coated with a protective coating metal layer to avoid erosion or contamination of other materials of the multilayer substrate, 'the reliability of the metal circuit is improved, and the etching method must be made by an additional exposure and etching process. Covering the cladding metal layer of the metal line, and the additional exposure and etching process may require the possibility of failing to manufacture the multilayer substrate metal line due to the accuracy of the alignment of the metal line and the cladding metal layer. The manufacturing cost of the substrate. Moreover, the etching method of the prior art cannot form a cladding metal layer on the side surface of the metal line or even the bottom surface in a single exposure process, that is, the reliability of the metal line cannot be improved by completely covering the metal line. It is also impossible to make metal lines that can be used as coaxial conductors. Referring to Figures 2A through 2D, there is shown a schematic diagram of a conventional technique for fabricating a multi-layer substrate metal line by a build-up method. Fig. 2A shows a very thin metal layer 102 formed on the dielectric layer 100 of a multilayer substrate. Fig. 2B shows that after coating a photoresist 1〇4 outside the pre-twisted position, a metal layer is developed on the surface at the predetermined position (e.g., by electroforming, Electroplating). 2 (: the figure shows the dielectric layer 1 移除 and the metal layer 1 〇 2 after removing the photoresist 104. Figure 21) shows etching the metal layer to remove the metal material outside the predetermined position, and Due to the isotropic nature of the wet etching method, it is inevitable that etching occurs on the side surface of the metal line 1〇2 as indicated by the arrow in FIG. 2, and is limited by the size of the metal grain, resulting in a rough line of the metal line. The surface. Therefore, whether it is the name or the layering method, it is limited by the size of the grain of the metal. The side surface of the metal line must have a certain roughness, and when the size of the metal line is required to be fine, this disadvantage This will limit the fineness of the metal lines. No DW 疋 疋 或是 or addition layer method, can not form a cladding metal layer on the upper surface, side surface 'or even the bottom surface of the metal line in one exposure process, and completely cover the metal line in 201216808 to improve the metal line Reliability. Therefore, if a multi-layer substrate metal wiring manufacturing method and structure can be developed to form a cladding metal layer on an upper surface, a side surface, or even a bottom surface of a metal line by an exposure process, a fine and highly reliable metal can be produced. The circuit can also be used as a metal line for coaxial wire applications. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a multi-layer substrate metal wiring structure capable of forming a lower cladding metal layer by forming an upper cladding metal layer or even a bottom surface on an upper surface and a side surface of a metal wiring in an exposure process. Another object of the present invention is to provide a multi-layer substrate metal wiring structure which avoids erosion or contamination of other materials of the multilayer substrate and produces a metal circuit having high precision and high reliability. To achieve the foregoing objects of the present invention, the multilayer substrate metal wiring structure of the present invention comprises a metal wiring and an upper cladding metal layer. The metal circuit is located at a predetermined location on the dielectric layer. The upper cladding metal layer is formed on the upper surface of the metal circuit and on both side surfaces, and even a cladding metal layer is formed on the bottom surface to protect the metal circuit, and the cladding metal layer completely covers the upper surface of the metal circuit as above. The two sides and the bottom surface are formed between the metal circuit and the upper and lower cladding metal layers, and the upper and lower cladding dielectric layers 'metal lines, upper and lower cladding dielectric layers, upper cladding metal layers and lower cladding metal layers are formed as one Application of coaxial wires. The dielectric layer of the predetermined location is a recessed structure compared to the dielectric layer outside the predetermined location to increase the adhesion enhancement of the metal trace to the dielectric layer. According to the method for manufacturing a multilayer substrate metal circuit of the present invention, the metal wiring and the cladding metal layer can be fabricated by only one mask process, and the silver etching method or the build-up method is not used, and the metal wiring side is not used. The surface is produced (4), and it can meet the requirements of the fineness of metal lines in 201216808. Moreover, the manufacturing method of the present invention is to form an upper and lower cladding metal layer on the upper surface of the metal circuit and on both side surfaces or even the bottom surface to completely protect the metal circuit from corrosion or pollution, and to improve the reliability of the metal circuit. Can be used as a coaxial wire. Therefore, the metal line density of the multilayer substrate can be further improved. The multilayer substrate metal wiring manufacturing method of the present invention is also applicable to a flexible substrate having deformable or deflectable properties. [Embodiment] Referring to Figures 3A to 3E, there is shown a flow chart of a first embodiment of a method of manufacturing a multilayer substrate metal circuit of the present invention and a structure thereof. Fig. 3A shows the application of at least one photoresist layer 3〇4 on the surface of a dielectric layer 300. The third Β_ indicates a step of exposing the photoresist layer 301 other than the predetermined position of one of the metal lines after applying the photoresist layer 3〇4. Figure 3C shows the step of removing the photoresist layer 3〇 at a predetermined position. Since the negative photoresist is selected in this embodiment, when the photoresist (3) is removed using the developer (9) oil (4), the photoresist layer is removed. The photoresist layer above the upper portion receives more light than the lower photoresist layer, so that the edge of the photoresist layer 304 adjacent to the predetermined position forms a structure in which the upper side protrudes from the lower side as shown in the above. However, the present invention is not limited to use. For the negative photoresist, a method of using a double-layer photoresist or the like may be used, for example, coating the structure in which the upper photoresist layer and the lower photoresist layer have different development rates on the upper side and the lower side.
3〇1進订曝光’當使用顯影劑（DM。㈣去除光阻層3 ， 圖表示於預定位置形成金屬線 阻層304上方形成一金屬層 一上包覆金屬層306，用 第3E圖表示移除光阻層304以 201216808 於第3D圖所示’於預定位置形成金屬線路3〇2之步驟前， 本發明之多層基板金屬線路製造方法可更包含一步驟，對預定 位置的介電層300之表面400施以一介面附著強化處理，以增 加介電層300與金屬線路3〇2間之附著強度。 ，，清參考第4A圖至4F圖’係繪示本發明多層基板金屬線路 製造方法之第二實施例及其結構之流程圖。第4a圖表示於一 介電層300表面塗佈至少一光阻層3〇4。第4Bffi表示塗佈光阻 層崩後，對金屬線路之一預定位置以外之光阻層3〇1進行曝 光之步驟。第4C圖表示去除位於預定位置之光阻層3〇ι的步 驟後’更包含-以钮刻方式去除位於預定位置的介電層则之 部份。由於本實施例係選用負型光阻，當使用顯影劑⑴⑽叩打） 去除光阻層301時，由於光阻層3G4上方之光阻層受光程度較 下方之光阻層為多’因此鄰接預定位置之光阻層3〇4邊緣會形 成如圖中所示上侧較下侧突出之結構。然而，如前所述，本發 明亦可使用如雙層光阻等之方法，製作相同的結構。第4D圖 表示於預定位置形成金屬線路3〇2之步驟後（同時亦會在光阻 層304上方形成一金屬層3〇3)’再於金屬線路3〇2之表面形成 一上包覆金屬層306,用以保護金屬線路3〇2之步驟。第4£圖 表示移除光阻層304以及金屬層3G3，以利後續製程進行之步 驟。 於本發明第二實施例中’由於去除位於預定位置之介電層 之部份’是以預定位置之介電層扇係為—下陷之構造。 該下陷之構造不僅可增加形成金屬線路3〇2時對介電層_之 附著強化。於形成金屬線路302之步驟中，亦可調整金屬線路 之厚度’使金屬線路逝之上表面與介電層扇表面等高， 201216808 以提供-平坦表面，以利與其他元 4F圓所示，調整金屬線路302之厚卢、制、3者’如第 與介電層3。7中間之金屬線路3。2，；：::介電層咖 可提供較佳之應力平衡，製造 ▲板又外力曲折時， 板。 冑“更具特性撓曲特性之軟性多層基 發明:二圓所不於預定位置形成金屬線路3〇2之步驟前，本 ^多層基板金屬線路製造方法可更包含—步驟，對預定位 人带I電層300之表面4〇〇施以一介面附著強化處理以 "電^3G()與金屬線路302間之附著強度。 9 明參考第5A圖至5E圖’麵示本發明多層基板金屬線路 ^方法之第二實施例及其結構之流程圖。第Μ圖至第冗圆 所顯示之步驟與第-實施例之第3A圖至第3C圖相同，第5〇 圖表示於該預定位置先形成下包覆金屬層306-1後，形成金屬 線路3〇2 (同時亦會在光阻層304上方形成-金屬層3〇3)，再 於金屬線路3〇2之表面形成上包覆金屬層3()6，用以完全包覆 金屬線路3〇2。再者，本發明之多層基板金屬線路製造方法可 更包3下列步驟’即於預定位置形成下包覆金屬層306-1後， 於下包覆金屬層306-1上形成一下包覆介電層，且於金屬線路 3〇2之上表面、側表面形成上包覆金屬層306前，亦先形成一 上包覆介電層。當應用於傳輸高頻訊號時，則金屬線路302、 該上下包覆介電層、上包覆金屬層3〇6以及下包覆金屬層306」 能作為同軸導線之應用，以利導通透過、上包覆金屬層306以 及下包覆金屬層306-1傳輸之高頻訊號。 並且’本發明亦可於第5D圖所示形成上包覆金屬層306 之步驟中’以真空鍍膜之方式，形成一上包覆介電層來取代上 ⑧ 201216808 包覆金屬層306。且於預定位置形成金屬線路3 02前，亦以真 空鍍膜之方式，形成一下包覆介電層取代下包覆金屬層306-1。 是以，對金屬線路之底面、上表面以及側表面，構成一上下包 覆介電層完整之保護。如第5D圖所示，於預定位置形成下包 覆金屬層306-1之步驟前，本發明之多層基板金屬線路製造方 法可更包含一步驟，對預定位置的介電層300之表面400施以 一介面附著強化處理，以增加介電層300與下包覆金屬層306-1 間之附著強度。 請參考第6A圖至6F圖，係繪示本發明多層基板金屬線路 製造方法之第四實施例及其結構之流程圖。第6A圖至第6C圖 所顯示之步驟與第二實施例之第4A圖至第4C圖相同，第6D 圖表示於該預定位置先形成下包覆金屬層306-1後，形成金屬 線路302 (同時亦會在光阻層304上方形成一金屬層303)，再 於金屬線路302之表面形成上包覆金屬層306，用以完全包覆 金屬線路302。再者，本發明之多層基板金屬線路製造方法可 更包含下列步驟，即於預定位置形成下包覆金屬層306-1後， 於下包覆金屬層306-1上形成一下包覆介電層，且於金屬線路 302之上表面、側表面形成上包覆金屬層306前，亦先形成一 上包覆介電層。當應用於傳輸高頻訊號時，則金屬線路302、 該上下包覆介電層、上包覆金屬層306以及下包覆金屬層306-1 能作為同軸導線之應用，以利導通透過上包覆金屬層306以及 下包覆金屬層306-1傳輸之高頻訊號。 並且，本發明亦可於第6D圖所示形成上包覆金屬層306 之步驟中，以真空鍍膜之方式，形成一上包覆介電層來取代上 包覆金屬層306。且於預定位置形成金屬線路302前，亦以真 201216808 空鍵膜之方式，形成-下包覆介電層取代τ包覆金4層30^。 是以，對金屬線路之底面、上表面以及側表面，構成一上下包 覆”電層元整之保護。如第6D圆所示，於預定位置形成下包 覆金屬層306」之步驟前，本發明之多層基板金屬線路製造方 法可更包含-步驟，對預定位置的介電層細之表面侧施以 一介面附著強化處理’以增加介電層3〇〇與下包覆金屬層鳩巧 間之附著強度。 於本發明第四實施例中，由於去除位於預定位置之介電層 300之部份’是以預定位置之介電層3⑼係、為__下陷之構造。 該下陷之構造不僅可增加形成金屬線路3〇2時對介電層3〇〇之 附著強化。於形成金屬線路地之步驟中，亦可調整金屬線路 3〇2之厚度，使金屬線路3〇2之上表面與介電層3〇〇表面等高， 以提供-平坦表面，以利與其他元件之後續封裝。或者，如第 :圓所示，調整金屬線路3〇2之厚度，以製造介於介電層⑽ 、介電詹307中間之金屬線路3G2,當多層基板受外力曲折時， 可提供較佳之應力平衡，製造更賜性撓曲㈣之軟性多 板0 =發明之所有實施例中’介電層3〇〇之材質可為聚酿亞 思金屬線路3〇2之材質可為銅。上包覆金屬们％、下包覆 it 306·1之材f可為鉻、欽、始、金或者錦等。介面附著 強化處理則可為一電漿製程處理。 者 線路toT提Γ，本發明之金屬線路製造方法不僅能於金屬 路如之形成上包覆金屬層3°6,更能同時於金屬線 302之兩側表面同時形成上包覆金屬層 屬線路地，避免金騎路地受到侵傲或污染，i高全 201216808 路之可靠度，再者， 下包覆金屬層306-1 軸導線之應用。 如於金屬線路302與上包覆金屬層 306、 間’再形成上下包覆介電I，則可作為同 二而言之，相較於習知技術，本發明之金屬線路搬並非 ^之方式形成’是以不受金屬晶粒伽⑷的大小所限 ’其表面精細’線緣平直性佳，不會產生粗糙之表面。且由 :本發月餡僅以單一道曝光製程即製造具有上包覆金屬層 、下包覆金屬層30H之金屬線路3()2,當金屬線路3〇2尺 層基板的電路積集度不斷地縮小時，本發明之金屬線 路製&方法除能確保金屬線路逝精細度之要求外，亦因 ，知技術較單純化之製程，更能提高該多層基板之可靠度以及 良率。 ‘上所述’本發明4已符合發明專利之要件，爱依法提出 專利申請。惟，以上所述者僅爲本發明之較佳實施方式，舉凡 熟習本案技術之人士援依本發明之精神所作之等效修飾或變 化，皆涵蓋於後附之申請專利範圍内。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、和優點能更明顯易 樓’配合所附圖式，作詳細說明如下： 第1圖係續·示習知技術以姓刻法製造金屬線路之示意圓· _第2A圖至2D圖係繪示習知技術以增層法製造金屬線路之 示意圖； 第3A圖至3E圖係繪示本發明多層基板金屬線路製造方法 之第一實施例及其結構之流程圖； 第4A圓至4F圖係垮示本發明多層基板金屬線路製造方法 201216808 之第二實施例及其結構之流程圖； 第5A圖至5E圖係繪示本發明多層基板金屬線路製造方法 之第三實施例及其結構之流程圖；以及 第6A圖至6F圖係繪示本發明多層基板金屬線路製造方法 之第四實施例及其結構之流程圖。 【主要元件符號說明】 100介電層 102金屬線路 104光阻層 300介電層 301未曝光區域之光阻層 302金屬線路 303金屬層 304光阻層 306上包覆金屬層 306-1下包覆金屬層 307介電層 400附著強化處理之區域 12 ⑧3〇1Substituting the exposure 'When the developer (DM) is used to remove the photoresist layer 3, the figure shows that a metal layer and a cladding metal layer 306 are formed over the metal line resist layer 304 at a predetermined position, which is represented by the 3E figure. Before the step of removing the photoresist layer 304 to form the metal line 3〇2 at a predetermined position as shown in FIG. 3D in 201216808, the multilayer substrate metal line manufacturing method of the present invention may further comprise a step of dielectric layer to a predetermined position. The surface 400 of 300 is subjected to an interface adhesion strengthening treatment to increase the adhesion strength between the dielectric layer 300 and the metal wiring 3〇2. The cleaning of the multilayer substrate metal wiring of the present invention is illustrated by reference to FIGS. 4A to 4F. A second embodiment of the method and a flow chart of the structure thereof. Fig. 4a shows that at least one photoresist layer 3〇4 is coated on the surface of a dielectric layer 300. The fourth Bffi indicates that after the photoresist layer is collapsed, the metal line is a step of exposing the photoresist layer 3〇1 outside a predetermined position. FIG. 4C is a view showing the step of removing the photoresist layer 3〇 at a predetermined position and further including removing the dielectric layer located at a predetermined position in a button-cut manner. Part of it. Because of this implementation When a negative photoresist is used, when the photoresist layer 301 is removed by using the developer (1) (10), since the photoresist layer above the photoresist layer 3G4 receives more light than the photoresist layer below, the photoresist layer adjacent to the predetermined position is adjacent. The edge of the 3〇4 will form a structure in which the upper side protrudes from the lower side as shown in the figure. However, as described above, the present invention can also produce the same structure using a method such as double-layer photoresist. 4D shows the step of forming the metal line 3〇2 at a predetermined position (and also forming a metal layer 3〇3 over the photoresist layer 304) and forming an upper cladding metal on the surface of the metal line 3〇2. Layer 306 is used to protect metal lines 3〇2. The fourth map shows the removal of the photoresist layer 304 and the metal layer 3G3 to facilitate the subsequent steps of the process. In the second embodiment of the present invention, the portion due to the removal of the dielectric layer located at the predetermined position is a structure in which the dielectric layer of the predetermined position is depressed. This depressed structure not only increases the adhesion strengthening of the dielectric layer when the metal wiring 3〇2 is formed. In the step of forming the metal line 302, the thickness of the metal line can also be adjusted to make the upper surface of the metal line and the surface of the dielectric layer fan the same, 201216808 to provide a flat surface, as shown by other 4F circles. Adjusting the thickness of the metal line 302, the system, and the three people's metal lines in the middle of the dielectric layer 3. 7 3. 2,;::: The dielectric layer can provide better stress balance, and the ▲ board and external force When twisting, the board.软 “Soft multi-layer base invention with more characteristic flexural characteristics: Before the step of forming the metal line 3〇2 at a predetermined position by the two circles, the method for manufacturing the multi-layer substrate metal line may further include a step for the pre-positioned person The surface 4 of the I electrical layer 300 is subjected to an interface adhesion strengthening treatment to adhere the strength between the electric 3G() and the metal line 302. 9 Referring to Figures 5A to 5E, the multilayer substrate metal of the present invention is shown. A flow chart of the second embodiment of the circuit and its structure. The steps from the second to the circumscribed circles are the same as the third to third embodiments of the third embodiment, and the fifth diagram is shown at the predetermined position. After the lower cladding metal layer 306-1 is formed, the metal wiring 3〇2 is formed (the metal layer 3〇3 is also formed over the photoresist layer 304), and the surface is formed on the surface of the metal wiring 3〇2. The metal layer 3 () 6 is used to completely cover the metal wiring 3 〇 2. Further, the multilayer substrate metal wiring manufacturing method of the present invention may further comprise the following steps of forming the lower cladding metal layer 306-1 at a predetermined position. Thereafter, a lower cladding dielectric layer is formed on the lower cladding metal layer 306-1, and the metal is Before the upper surface and the side surface of the surface 3〇2 are formed with the upper cladding metal layer 306, an upper cladding dielectric layer is also formed first. When applied to transmit high frequency signals, the metal wiring 302, the upper and lower cladding dielectrics The layer, the upper cladding metal layer 3〇6 and the lower cladding metal layer 306′′ can be used as a coaxial wire for the high-frequency signal transmitted through the upper cladding metal layer 306 and the lower cladding metal layer 306-1. . Further, the present invention can also form an upper cladding dielectric layer in the step of forming the upper cladding metal layer 306 as shown in Fig. 5D by vacuum coating to replace the upper cladding layer 306 of 201216808. Before the metal line 302 is formed at a predetermined position, a lower cladding dielectric layer is formed instead of the lower cladding metal layer 306-1 by vacuum coating. Therefore, the bottom surface, the upper surface and the side surface of the metal line constitute a complete protection of the upper and lower dielectric layers. As shown in FIG. 5D, before the step of forming the lower cladding metal layer 306-1 at a predetermined position, the multilayer substrate metal wiring manufacturing method of the present invention may further include a step of applying the surface 400 of the dielectric layer 300 at a predetermined position. An interface adhesion strengthening treatment is performed to increase the adhesion strength between the dielectric layer 300 and the lower cladding metal layer 306-1. Referring to Figures 6A to 6F, there is shown a flow chart of a fourth embodiment of the method for fabricating a metal substrate of a multilayer substrate of the present invention and a structure thereof. The steps shown in FIGS. 6A to 6C are the same as those in FIGS. 4A to 4C of the second embodiment, and FIG. 6D shows that the metal wiring 302 is formed after the lower cladding metal layer 306-1 is formed at the predetermined position. (At the same time, a metal layer 303 is formed over the photoresist layer 304), and an over cladding metal layer 306 is formed on the surface of the metal trace 302 for completely covering the metal trace 302. Furthermore, the method for manufacturing a multilayer substrate metal line of the present invention may further comprise the steps of forming a lower cladding dielectric layer on the lower cladding metal layer 306-1 after forming the lower cladding metal layer 306-1 at a predetermined position. Before the upper cladding metal layer 306 is formed on the upper surface and the side surface of the metal line 302, an upper cladding dielectric layer is also formed. When applied to transmit high frequency signals, the metal line 302, the upper and lower cladding dielectric layers, the upper cladding metal layer 306, and the lower cladding metal layer 306-1 can be used as coaxial wires to facilitate conduction through the package. The high frequency signal transmitted by the metallization layer 306 and the lower cladding metal layer 306-1. Further, in the present invention, in the step of forming the upper cladding metal layer 306 shown in Fig. 6D, an upper cladding dielectric layer may be formed by vacuum plating to replace the upper cladding metal layer 306. Before forming the metal line 302 at a predetermined position, the dielectric layer is formed to replace the τ-coated gold layer 30^ in the form of a true 201216808 dummy film. Therefore, the bottom surface, the upper surface, and the side surface of the metal line are protected by an upper and lower cladding "electric layer element. As shown in the sixth circle, before the step of forming the lower cladding metal layer 306 at a predetermined position, The method for manufacturing a multilayer substrate metal line of the present invention may further comprise the step of: applying an interface adhesion strengthening treatment to the surface side of the dielectric layer at a predetermined position to increase the dielectric layer 3 and the under cladding metal layer. The adhesion strength between. In the fourth embodiment of the present invention, since the portion of the dielectric layer 300 which is located at a predetermined position is removed, the dielectric layer 3 (9) of the predetermined position is a structure which is depressed. This depressed structure not only increases the adhesion strengthening of the dielectric layer 3 when the metal wiring 3〇2 is formed. In the step of forming the metal wiring ground, the thickness of the metal wiring 3〇2 may also be adjusted so that the upper surface of the metal wiring 3〇2 is equal to the surface of the dielectric layer 3〇〇 to provide a flat surface to facilitate other Subsequent packaging of components. Or, as shown in the circle: the thickness of the metal line 3〇2 is adjusted to fabricate the metal line 3G2 between the dielectric layer (10) and the dielectric 307, which provides better stress when the multilayer substrate is bent by an external force. Balance, make more flexible (4) soft multi-plate 0 = In all the embodiments of the invention, the material of the dielectric layer 3 can be made of copper. The material f of the upper cladding metal and the material f of the lower cladding it 306·1 may be chromium, chin, beginning, gold or brocade. The interface adhesion enhancement process can be a plasma process. The method for manufacturing the metal circuit of the present invention can not only form the metal layer 3°6 on the metal road, but also form the upper cladding metal layer line on both sides of the metal line 302 at the same time. In order to avoid the arrogance or pollution of the golden road, the reliability of the high road 201216808, and the application of the metal layer 306-1 shaft conductor. For example, when the metal line 302 and the upper cladding metal layer 306 are re-formed to form the upper and lower cladding dielectrics I, as a matter of the second, the metal wiring of the present invention is not the same as the prior art. The formation 'is not limited by the size of the metal grain gamma (4) 'the surface is fine', the line edge is good, and no rough surface is produced. And by: the moon filling is only a single pass exposure process to manufacture the metal line 3 () 2 with the upper cladding metal layer and the lower cladding metal layer 30H, when the metal circuit 3 〇 2 ft layer substrate circuit accumulation When continuously shrinking, the metal wiring system of the present invention can not only ensure the fineness of the metal wiring, but also improve the reliability and yield of the multilayer substrate because the technology is more simplistic. The above invention 4 has met the requirements of the invention patent, and loves to file a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, and advantages of the present invention more obvious, it is described in detail as follows: Figure 1 is a continuation of the teaching technique A schematic circle for manufacturing a metal circuit _ 2A to 2D are schematic views showing a conventional method for manufacturing a metal line by a build-up method; and FIGS. 3A to 3E are diagrams showing a method for manufacturing a metal substrate of a multilayer substrate of the present invention; A flow chart of an embodiment and a structure thereof; FIG. 4A to FIG. 4F are flowcharts showing a second embodiment of the method for manufacturing a multilayer substrate metal circuit of the present invention 201216808 and a structure thereof; FIGS. 5A to 5E are drawings showing A flow chart of a third embodiment of the method for fabricating a multilayer substrate metal line and a structure thereof; and FIGS. 6A to 6F are flowcharts showing a fourth embodiment of the method for manufacturing a metal substrate of a multilayer substrate of the present invention and a structure thereof. [Main component symbol description] 100 dielectric layer 102 metal line 104 photoresist layer 300 dielectric layer 301 unexposed area photoresist layer 302 metal line 303 metal layer 304 photoresist layer 306 coated metal layer 306-1 under the package Metal-clad layer 307 dielectric layer 400 adhesion strengthening treatment area 12 8