TW313682B - - Google Patents

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Publication number
TW313682B
TW313682B TW084113107A TW84113107A TW313682B TW 313682 B TW313682 B TW 313682B TW 084113107 A TW084113107 A TW 084113107A TW 84113107 A TW84113107 A TW 84113107A TW 313682 B TW313682 B TW 313682B
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Taiwan
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layer
silicide
conductive layer
point structure
indirect point
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TW084113107A
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Samsung Electronics Co Ltd
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/905—Plural dram cells share common contact or common trench
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/906—Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/907—Folded bit line dram configuration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/908—Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Description

A7 B7 3136S2 五、發明説明（1 ) 本發明有關於一種半導體記億元件及其製法，更特別 地’偽有關於一種採用層間接點構造，俥藉由降低其上和 下導電層間之接觸電阻來增進元件之電氣特性的半導髏元 件及其製法。 隨著半導體元件之整合度增加，具有多層式'搆造之導 電層的構成物變得更盛行。在這種情況下，於該等導電層 間的接觸待性（即，電阻），對於半導體元件之整锢電氣 特性有·一重要的影響。近期，具有複晶矽化物（Pol ycide) 構造（在複晶矽之頂上的矽化物）的導電層已被用來降低 薄層電阻。 第1 A至1 D圖描繪一種用以製造層間接點在一半導 體記憶元件的上和下導電層之間，每個導電層具有上述之 複晶矽化物搆造。 I青參閲第1 A圖所示，諸如氧化矽（s i 0 2)的氧化物偽 被沉積於一半導體基體10上來形成一閘極氧化層12。然後 ，一摻雜有磷離子的第一複晶矽層14、一第一矽化鎢層 tfSU 16和一封頂層18依序地被沉積在該閘極氧化層12上， 而然後被定以圔型來形成下導電層（14 , 16)。在這裡，封 頂層18是一氧化或者氮化層。然後，諸如硼礎矽酸鹽玻璃 的一絶緣材料傺被沉積在該具有下導電層（14,16)的合成 層上，並且被流回以形成具有一平表面的層間絶緣層20 ( 第1 B圖）。一接觸孔1接著藉由部份蝕刻層間絶緣層20 和封頂層18而形成，以暴露第一矽化鎢層16 (參看第1 C 圖）。隨後，一摻雜有磔離子的第二複晶矽層22和一第二
I —4 - . 本纸張尺度適用中國國家標準（CNS ) Α4規格（21 〇 X 297公釐） — 裝 (請先閱讀背面之注意事項再填寫本頁) 、?τ 經濟部中央揉隼局員工消费合作社印裂 ----- A7 B7 經濟、砰中央標準局員工消費合作杜印製 五、發明説明（2) 矽化鷄層24慠被堆積在該合成層的整値表面上，以形成與 第一矽化_層16接觸的上導電層（22,24)(請參看第1 D 圖）。 ‘然而，在此傳統的層間接點構造（第一矽化_層16係 直接接觸於被摻以礎離子的第二複晶矽層22)中，接觸電 阻由於下列兩個原因而增加。首先，摻雜雜質之第二複晶 矽層22的磷離子朝向第一矽化_層16擴散，藉以降低在其· 界面處的雜質濃度。其次，在形成接觸孔1之後且在第二 複晶矽層22的沉積之前，諸如氧化鋳（W〇3)或氧化矽（Si〇2) 的天然氧化層被形成於第一矽化鴒層16的表面上。 第2 .圖顯示在t値採用傳統層間接點構造（第1 D圖 )之取樣晶圓（a)至（g)中所測量的接觸電阻分佈特性曲 線。在這裡，能夠見到的是該傳統接點構造的接觸電阻大 致上在毎接點Ikft以上（接點尺寸：-0 · 4 X 0.48μιη2)。應 要注意的是*如此高的接觸電阻負面地影_運作速度，且 如果接觸電阻超過大約lOkitte話*無法達到適當的元件蓮 作。 . 第3圖顯示上述接點構诰在（a)退火之前和（b)退火 之後的雜質分佈，其中，第一複晶矽層、第一矽化鶴§、 第二複晶矽層、第二矽化鎢層和在每値界面處的濃度傷被 顯示。在這裡，低濃度的雜質顯然在該第一矽化鴿層與該 第二複晶矽層之間。 tm- 因此，本發明之目的是來提供一種具有層間接點構造 的半導體元件，俥藉由降低其接觸電姐來增進其上和下導 (請先M讀背面之注意事項再填寫本頁) • 1 nn »
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.Ό----I 本紙乐尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） 經濟部中央標準局負工消費合作社印製 A7 B7 五、發明説明（3 ) 層間之接觸特性。 本發明之另一目的是來提供一種製造具有層間接點構 造之半導體元件的方法。 為了逹到以上之笫一目的，提供一種具有層間接點構 造於一下導電層與一上導電層之間的半導體元件，在該下 導電層中，—第一導電層和一第一矽化物層偽被堆積’在 該上導電層中，一摻雜有雜質的第二導電層和一第二矽化 物層像被堆積，其中該第一和第二導罨層僳彼此直接接觸 0 為了逹到以上之第二目的，提供一種製造具有層間接 點構造之半導謾元件的方法，該方法包含如下之步驟：（a) 形成一下導電層，在該下導電層中，第一導電層和第一矽 化物層樣藉由堆積第一矽化物層於第一導電層上而被堆積 ;(b)形成一··層間絶緣層在該具有下導電層之合成層的整 個表面上；（c)藉由部份蝕刻該層間絶緣層而形成一接觸 (d)部份蝕刻該經由接®孔而裸露的第一矽化物層； (e)形成一摻雜有雜質的第二導電層於該完成蝕刻步驟（d) 的合成層上；及（f)形成一上導電層，在該上導電層中， 第二導電層和第二矽化物層傷藉由堆積第二矽化物層於第 二導電層上而被堆積。. 最好的是，該第一和第二導電層傺由非結晶質矽或者 複晶矽製造而成。在這裡，更好的是，該第一和第二矽化 物層傷由砂化鎢（W S i a)、矽化敎（T i S i 2)、矽化笛（η 〇 S i 2) * —δ — . 本紙張尺度適用中國國家榇準（CNS ) A4规格（210X 197公釐） ---------r .裝--- (請先閱讀背面之注意事項再填蔣本頁) n n HI *?τ mf mu· vnn vm fl^itf 1·111 ^^fl.1 mu n—λ m^— Jr > 313682 A7 B7 經濟'邓中央標準局員工消費合作社印裝 五、發明説明（“） 和矽化鉅（TaS i 2)之矽化物組群中所選擇的一個製造而成 »而且被使用的雜質為磷或者砷離子。 在以上的方法中，最好的是，步驟（d)僳利用等向蝕 刻法來被執行。更好的是，該等向蝕刻法是一種使用含有 NfUOH 、H2〇2或者之蝕刻劑的濕蝕刻法，或者是一種 使用C 12/SFs氣體的乾蝕刻法。在步驟（d)期間，該第一 矽化物層傜被蝕刻直到該第一導電層傲被暴露。 因此，根據該採用層間接點構造的半導體元件及其製 法，層間接點的電氣特性能夠藉由降低_在該下導電層與該 上導電層之間的接觸電阻而被改良，該下導電層在其之最 上部份具有一矽化物層，該上導電層在其之最下部份具有 一雜'質摻雜的導電層。 本發明之以上之目的和優點藉由配合附圖詳細描述其 之較佳實施例而將會變得雯明白，其中： - . 第1 A至1 D圖是描繪一種製造具有層間接點構造之 半導體元件之習知方法的截面圖； 第2画是顯示數値使用該習知層間接點構造之取樣晶 元之接觸電阻分佈待性的醒表； 第3圖是顯示在退火之前和之後，於該習知層間接點 構造中之雜質分佈的函表；. 第4圖是顯示根據本發明之第一較佳實施例所製诰之 一種具有層間接點構造之半導髏元件的截面圖； 第5A至5E圖是描繪本發明之第一較佳實施例之一 種製造具有層間接點構造之半導體元件之方法的截面圖； -7 - (請先閲讀背面之注意事項再填寫本頁) ...... -裝--- -9 本紙張尺度遣用中國國家標準（CNS ) A4規格（210X297公釐） .經濟部中央標準局員工C费合作社印製 A7 _____ B7 一五、發明説明（S) 第6A和6 B画是描繪本發明之第二較佳實施例之一 種製造具有層間接點構造之半導體元件之方法的截面圖； 及 第7圖是顯示兩痼使用本發明之第一較佳實施例之層 間接點搆造之取樣晶元之接觸電阻分佈特性的圖表。 在第4圖中，標號10樣示一半導體基體，標號12標示 一閘極絶緣層，標號14標示一第一導電層，標號16 ’標示 一第一矽化物層，標號18標示一封頂層，標號20標示一層 間絶緣層，檫號22 1標示一第二導電層及標號24標示一第 二矽化物層。在這構造中，該第一導電層14和第一矽化物 層16'構成一下導電層，而該第二導電層22’和第二矽化 物層纟4構成一上導電層，第二導電層22'(上導電層的） 傜直接與第一矽化物層16’ （下導電層的）。在這裡，第 一和第二導電層14和22「傺各約1000A厚，而第一和第二 . 矽化物層16'和24傜各約1500A厚。 第二導電層22’傜由摻有雜質的導電物質製造而成， 即，.複晶矽。在這裡，雖然磷僳被使用，用以摻雜第二導 電層22’的雜質亦可以是砷離子。再者，第二導電層22' 亦可以是由非結晶質的矽製造而成而不是複晶矽。 • 第一和第二矽化物層16 '和24皆是由矽化鍚（WSix)製 造而成。然而，在本發明中，它們亦可以是由矽化鈦 (TiSi2)、矽化鉬（M〇Si2)或者矽化鉅（TaSi2)製造而成 Ο 根據本發明的層間接點構造，為了産生一進步的接觸 .m- - - I » (诗先閱讀背面之注意事項再填寫本頁) • ------訂 --^線--- 本紙张尺度適用中國國家梂準（CNS ) A4規格（210 X 297公釐） A7 B7 S13682 五、發明説明丨么） 區域在第二導電層22'與下導電層（14,13’）之間，即，比 該接觸孔本身大，第一矽化物層16，是被等向地蝕刻因此 其之厚度僳被減少至在該初始沉積的厚度之下，藉此降低 在該等導電層之間的接觸電阻。在這裡，雖然第4圖描繪 一値具有直接形成在第一和第二導電層14和22 ’之間之層 間rf點構造的半導髏元件，一較佳實施例可以被形成以致 於第一矽化物層16 ’之稍微較薄的部份維持在該第一和第 二導電層之間。 第5A至5 £_描繪本發明之第一較佳實施例之一種 製造具有層間接點構造之半導體元件的方法。 第5 A圖顯示形成該下導電層的步驟。該步驟包含藉 由沉積如二氧化矽般之一絶緣物質在一半導體基體10上來 形成一閘極絶緣層12和藉由依序堆積一第一導電層14、一 第一矽化物層16和一封頂層18在閘極絶緣層12上並且定以 — . 該合成層之圖型來形成一下導電.層（14,16)的次步驟。在 這裡，第一導電層14是藉由沉積摻有磷離子的複晶矽至大 約1000A的厚度來形成，而第一矽化物層16是藉由沉積如 矽化錫般，但亦可以是矽化鈦（TiSh)、矽化鉬（MoSU) 或者矽化鉅（TaSi 2)，的矽化物至大約1500A的厚度來形 成。封頂層18是由如氧化物或氮化物般的絶緣材料形成而 且在某些情況中是可以被忽略的因為它不直接影響該元件 特性。 ......... 第5 B圖顯示形成層間絶緣層20的步驟。在沉積如硼 磷矽酸鹽玻璃般的絶緣材料在該具有下導電層（14，16 )的 -9 - 本紙浪尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） -----------裝-- (請先閲讀背面之注意事項再填寫本頁) 訂 旅 經濟.那中央檩準局員工消費合作社印製
經濟部中央標準局属工消費合作社印装 五、發明説明（Q ) 合成層之後，該絶線材料像被回流，以藉此形成具有一平 面化表面的層間絶緣層2 0。 第5 C圖顏示形成一接觭孔1的步驟^在這裡，層間 絶緣層20和封頂層18偽利用諸如反應的離子蝕刻的異向性 蝕刻方法來被部份蝕刻。據此，接觸孔1像被形成以暴露 笫一矽化物層16。 笫5 D圖顯示部份蝕刻第一矽化辍層16的步驟。在這 裡，第一砂化物層16的暴露部份傜經由等向蝕刻法被部份 蝕刻。在該第一較佳實施例中，第一碌化杨層16是透過使 用包括NΗ 4 OH，Η 2 0 2和Η 2 0之蝕刻劑的濕蝕刻方法被蝕刻 ，但是利用C丨2 / S F s氣體的乾蝕刻方法亦可以被使用。藉 由使用等向蝕刻法，第一導電層14的暴露區域是比接觸孔 1的接觸區域大，因此第一導霄層14接觸第二導電層（在 下面的步驟中被形成）的區域傜比以習知所形成的大。因 此，如眾所週知*隨著該接觸區域增加，該接觸電阻減少 0 第5 Ε画顯示形成上導電層的步驟。在這裡，第二導 電層22 ’和第二砂化物層24傜被依序堆積在該合成層的整 痼表面上*以藉此形成該上導電層。在該第一較佳實施例 中，鏐有雜質的複晶砂傜被使用於第二導電層22 ’ ，而矽 化鎢换被使用於第二矽化物層24。然而，第二導電層22 ’ 亦可以是由摻有雜質的非結晶質矽製造而成*而第二矽化 ' 物層24亦可以是由矽化鈦（TiSi3) _、矽化鉬（MoSM或者 矽化鉅（TaSi2)製造而成。 -10 - (请先閱讀背面之注意事項再填寫本頁) •裝丨 --訂
T 本紙張尺度逋用中國國家橾準（CNS ) A4规格（2〖〇><297公釐） ..... ----313632 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（f ) 本發明之第一較佳實施例的層間·接觸方法具有三値有 利的結果。第一，因為在該上與下導電層之間的接觸表面 面積被增加，該接觸電阻降低。第二，該第一和第二導電 層直接彼此接觸，因此*接觸電阻由被包括於該第二導電 層内之雜質至該第一矽化物層之擴散所引起的增加傜被防 止。第三，該接觸電阻藉由移去天然氣化層被形成在該第 一矽化物層上的可能性而更被降低。 第6 A和6 B圖描繪本發明之第二較佳實施例之一種 製造具有層間接點構造之半導體元件的方法。 在該第一實施例中，在形成接觸孔1之後，第一矽化 物層16像被等向地蝕刻直至第一導電層14之表面的一部份 被暴露為止。然而，在該第二較佳實施例中，該等向蝕刻 法慑被執行至一較少程度（第6A圖），侔可留下預定厚 度的第一矽化物層16 η在第一導電層14上，且，假設初始 第一矽化物厚度是約1500Α ，這樣會是大約50(U =隨後的 處理是與第一實施例（第6 B圖）的處理相同。 裉據在本發明之第二較佳實施例中的層間接觸方法， 比習知獲得之接觸電阻較低的接觸電阻能夠被得到，因為 在第一與第二導電靥14和22 ’’之間之矽化物層16 "的厚度 是比其之初始沉積厚度薄，而且在矽化物層16 1 '中之雜質 離子的濃度根據被減少的厚度而降低。 第7圖顯示在兩锢取樣晶元（h)和（i)中所測董到之 接觸電阻分佈特性，在其中 > 本發明之第一較佳實施例的 層間接點構造被使用。在這裡，能見到的是在上和下導電 ~ 11 - (請先閱讀背面之注意事項再填寫本頁) τ 裝^— .. I»、1TI .
T i i 本紙張尺度逋用中國國家標隼（CNS ) A4規格（21〇 X邛，公釐） Α7 Β7 五、發明説明 層之間的接觸電阻是比習知方法的少，以藉此增進該元件 的電氣特性。那就是，該接觸電阻在習知方法中是完全在 lkst之上，但是利用本發明之方法的接觸電阻降低至大約 毎接點200Ω：(接點尺寸：〇 · 4 X 〇 . ,48μΐΕ2 )及更少。 因此》在本發明之層間接點構造和層間接點構造的製 法中’在半導體記億元件之上與下導電層之間的接錨電阻 戯劇性地降低，以藉此增進該元件的電氣特性。 應要察覺到的是本發明並不受限於以上的較佳實施例 。變化和進一步的改變對於熟知此技藝之人仕來説，會在 本發明之精神内和在由所附申請專利範圍所定義的範圍内 被想到。 ------------ (請先閲讀背面之注意事項再填寫本頁) 10 基體 14 第一複晶矽層 18封頂層 22 第二複晶矽層 18’第一矽化物 16^第一矽化物層 元件檫號對照表 12 閘氣化層 16 第一矽化鋒層 20 層間絶緣層 24 第二矽化_層 22'第二導電層 22 "第二導電層 .Η-旅 經濟部中央標準局員工消费合作社印製 -12 尽紙乐尺度適用中國國家埭準（CNS ) a4規格（2丨OX297公釐）

Claims (1)

  1. 313682 A8 B8 C8 D8 經濟部中夬標準局員工消費合作社印製 六、申請專利範圍 1.一種具有一層間接點構造的半導體元件，該層間接點 構造傷在一下導電層與一上導電層之間，在該下導電 層中，一第一導電層和一第一矽化物層偽被堆積，而 在該上導電層中，一摻有雜質的第二導電層和一第二 矽化物層#被堆積，其中該.第一和第二導電層僳彼此 直接接觸。 2 .如申請專利範圍第1項所述之具有一層間接點構造的 半導體元件，其中該第一和第二導電層皆是由包含非 結晶質矽和複晶矽之組群中所選擇的一種材料製造而 成。 3 .如申請專利範圍第2項所述之具有一層間接點構造的 半導體元件，其中，該第一和第二矽化物層皆傷由包 含矽化鶴（ysi2)、矽化鈦（TiSi2)、矽化钼（MoSi2) 和矽化鉅（TaS i 2)之組群中所選擇的一値製造而成。 4. 一種製造具有層間接點構造之半導體元件的方法，包 含如下之步驟： (a) 形成一下導電層，在該下導電層中’ 一第一 導電層和一第一矽化物層靠堆積該第一矽化物層在該 第一導電層上而被堆積； (b) 形成一層間絶緣層在該具有該下導電層之合 成層的整値表面上； (c) 藉由部份蝕刻該層間絶緣層而形成一接觸孔 ， (d )部份蝕刻該經由該接觸孔而波暴露的該第一 -13 - 紙張尺度適用中國國家標準（CNS ) A4規格（2iOX2rn公釐） (請先Η讀背面之注意事項再填寫本頁) T 、tr 313682 A8 B8 C8 D8 經濟部中央揉準局員工消費合作社印製 六、+請專利範園 矽化物層； (e) 形成一摻雜有雜質的第二導電層在該完成蝕 刻步驟（d)的合成層上；及 (f) 形成一上導電層，在該上導電層中，一第二 導電層和一第二矽化物層靠.堆積該第二矽化物層在該 第二導電層上而被堆積。 5.如申請專利範圍第4項所述之製造具有層間接點構造 之半導體元件的方法，其中該第一和第二導電層皆是 由包含非結晶質矽和複晶矽之組群中所選擇的一種材 料製造而成。 6 .如申請專利範圍第5項所述之製造具有層間接點構造 之半導體元件的方法，其中，該第一和第二矽化物層 皆傜由包含矽化鎢（WSh)、矽化鈦（TiSh)、矽化鉬 (MoSh)和矽化鉅（TaSi2)之組群中所選擇的一種材 料製造而成。 7 ·如申請專利範圍第6項所述之製造具有層間接點構造 之半導體元件的方法，其中，該等雜質像從包含磷離 子和砷離子之組群中選擇出來。 8. 如申請專利範圍第4項所述之製造具有層間接點構造 之半導體元件的方法，其中*該步驟（d)僳利用等向 蝕刻法來被執行。 9. 如申請專利範圍第8項所述之製造具有層間接點構造 之半導體元件的方法^其中，該等向蝕刻法是一種使 用含有NH4〇H 、Η202和H20之蝕刻劑的濕蝕刻法。 -14 - fm —m vflu · (請先閣讀背面之注意事項再填寫本頁) 裝-- 訂---- 線丨· • - 1 II- -- - ·---1-- -1 -- - - ·: - ......I H . 本紙張尺皮適用令31家淒a ( CNS ) A4規格（210X297公釐） 經濟部中央揉率局員工消費合作社印製 / ABCD 利請 '六 10 .如申請專利範圍第8項所述之製造具有層間接點構造 之半導體元件的方法，其中，該等向蝕刻法是使用 CU/SFs氣體的乾蝕刻法。 11,如申請專利範圍第4項所述之製造具有層間接點構造 之半導體元件的方法，其中，在該步驟（d )期間，該 第一矽化物層傜被蝕刻直到該第一導電層傜被暴露。 (請先閨讀背面之注意事項再填寫本頁) 叫 'tT 線—！ 本纸張尺度逋用中國國家榇準（CNS ) A4乳格（210X297公釐〉
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