TW312853B - Flash memory cell and manufacturing method thereof - Google Patents
Flash memory cell and manufacturing method thereof Download PDFInfo
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- TW312853B TW312853B TW085107439A TW85107439A TW312853B TW 312853 B TW312853 B TW 312853B TW 085107439 A TW085107439 A TW 085107439A TW 85107439 A TW85107439 A TW 85107439A TW 312853 B TW312853 B TW 312853B
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- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract 13
- 239000010703 silicon Substances 0.000 claims abstract 13
- 239000004065 semiconductor Substances 0.000 claims abstract 4
- 238000000034 method Methods 0.000 claims 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 7
- 150000004767 nitrides Chemical class 0.000 claims 6
- 230000003647 oxidation Effects 0.000 claims 5
- 238000007254 oxidation reaction Methods 0.000 claims 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 claims 3
- 238000005530 etching Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 210000004709 eyebrow Anatomy 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 239000007800 oxidant agent Substances 0.000 claims 1
- 238000009834 vaporization Methods 0.000 claims 1
- 230000008016 vaporization Effects 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 abstract 2
- 230000002079 cooperative effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
312853 A5 B5四、中文發明摘要(發明之名稱: ) 狭閃記憶体細胞元及其製法 本發明之高效率分離閘極聖怏园記憶体細胞元+在浮動閘極的側 壁上形成了 ΟΝΟ或ON結構的絕緣空間子,可以避免跼含比例下降, 也能防止電子漏過浮動閛極與控制閜極之間,改善了細胞元的編程與 拭除能力。 (請先閱讀背面之注意事項再填寫本頁各襴) 4- ml nt— Bm· ml·— mu ml l^m f 英文發明摘要(發明之名稱: 訂 經濟部中央樣準局員工消費合作社印策 .I- I p - 1-: I........I i If -!·--1 I . ---1 -1 ---- —It............. 本紙張尺度逍用中國國家標準((::^)八4規格(210父297公嫠)
Claims (1)
- 經濟部中央襁準局員工消费合作社印策 A8 B8 312853_ ο» ___! 六、申請專利範圍 1. 一種半導体元件中的快閃記憶体細胞元,係包含: 一個浮動閘極與一個靂道氧化禳-位在一面矽基板上選定的僵域 上; 絕緣膜空間子,位在該浮動閘欏的兩側; 一層介電膜,位在包括該絕緣膜空間子在內的整個表面上; 一個源極區,位在矽基板內,其中該源欏區延伸至該隧道氣化膜底 下的矽基板部位; 一個汲極區,位在該矽基板內;以及 一個控制閘極,位在該浮動閹種上方的介電膜上,並且延伸到該汲 棰區上方的介電膜上。 2. 根據申請專利範圍第1項的怏閔記憶体細胞元,其中該隧道氧化膜 ®約50至100埃。 3. 根據申請專利範圍第1項的怏閃記慷体細胞元,其中該絕緣膜具有 ΟΝΟ的結構,是由底下的氣化膜、氮化膜和頂面的氧化膜連績堆疊 而成的。 4. 根搛申請專利範圍第3項的快閃記憶体細胞元,其中該底下的氧化 膜是一靥CVD氧化膜。 5·根據申請專利範圍第3項的怏閃記憶体細胞元,其中該底下的氧化 膜是一靥熱氧化膜。 根據申請專利範画第1項的怏閃記憶体細胞元,其中該絕緣膜空間 子厚約50至1〇〇埃。 7·根據申請專利範園第1項的怏閃記憶体細胞元,其中該絕緣膜具有 ON的結搆,是由氧化膜和氮化膜連纘堆叠而成的。 8.根據申請專利範圍第7項的怏閃記憶体細胞元,其中該氧化膜是一 層CVD氧化膜。 本紙張尺度逋用中國國家標準(CNS〉M规格(21〇X297公釐) (请先閲讀背面之注意事項再填寫本頁)經濟部中央標率局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 9. 根據申請專利範圍第7項的快閃記憶体細胞元,其中該氧化膜是一 眉熱氧化膜。 , 10. 根據申請專利範圍第1項的快閃記憶細胞元,其中該介電膜是一 層熱氧化膜。 11. 一種在半導体元件中製造快閃記憶体細胞元的方法,其步驟係包 a 在一面矽基板上連績形成一層隧道氯化膜、一層第一複晶矽層、 和一層氧化膜; 制定該氧化膜與第一複晶矽層的圖案,形成一個浮動閛極; 在該矽基板內形成源極與汲極區; 在形成該源極與汲極區後的整個表面上,形成一層絕緣膜,並利 用均向性的蝕刻製程,在該氯化膜與浮動閜極的側壁形成絕緣膜 空間子; 去除殘留在該浮動閛極上的氧化膜後,進行一道熱氧化製程,在 露出的矽基板上形成一層選擇閘極氧化膜,並在該浮動閛極上形 成一層介電膜;並且 在進行該熱氧化製程後的整個表面上,形成一層第二複晶矽層, 並且制定該第二複晶矽層的圖案,形成一個控制閛極。 12. 根據申請專利範圍第11項的方法,其中該隧道氧化膜厚約50至100 埃。 13. 根據申請專利範圍第11項的方法,其中該氧化膜總厚度約爲300至 600埃。 14. 根據申請專利範圍第11項的方法,其中該絕緣膜具有ΟΝΟ的結 構,是由底下的氧化膜、氮化膜和頂面的氧化膜連纜堆叠而成 的0 (請先閲讀背面之注意事項再填寫本頁) 本紙浪尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) 經濟部中央梂準局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 15. 根據申請專利範圍第14項的方法,其中該底下的氧化膜是一層 / CVD氧化膜-。 16. 根據申請專利範圍第14項的方法,其中該底下的氧化膜是一層熱 氧化膜。 17. 根據申諝專利範圍第11項的方法,其中該絕緣膜具有ON的結構, 是由氯化膜和氮化膜連續堆叠而成的。 18. 根據申請專利範圍第17項的方法,其中該氧化膜是一層CVD氧化 膜0 19. 根據申請專利範圍第17項的方法,其中該氧化膜是一屜熱氯化 膜。 20. —種在半導体元件中製造快閃記憶体細胞元的方法,其步驟係包 含: 在一面矽基板上連續形成一層隧道氧化膜和一層第一複晶矽層; 制定該第一複晶矽層的圖案,形成一個浮動閛極; 在該碎基板內形成源極與汲極區; 在形成該源極與汲極區後的整個表面上,形成一層絕緣膜,並利 用均向性的蝕刻製程,在該氧化膜與浮動閛極的側壁形成絕緣膜 空間子; 進行一道熱氧化製程,在露出的矽基板上形成一層選擇閘極氧化 膜,並在該浮動闡極上形成一眉介電膜;並且 在進行該熱氧化製程後的整個表面上,形成一層第二複晶矽層, 並且制定該第二複晶矽眉的圖案,形成一個控制閘極。 21. 根據申請專利範圍第20項的方法,其中該隧道氧化膜厚約50至100 埃0 22. 根據申請專利範圍第20項的方法,其中該氧化膜總厚度約爲300至 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) .— I與----- 經濟部中央標準局員工消費合作社印製 A8312853 I 六、申請專利範圍 600埃。 23. 根據申請專利範圍第20項的方法,其中該絕緣膜具有ΟΝΟ的結 構,是由底下的氧化膜、氮化膜和頂面的氧化膜連績堆叠而成 的。 24. 根據申請專利範圍第23項的方法,其中該底下的氧化膜是一層 CVD氧化膜。 25. 根據申請專利範圍第23項的方法,其中該底下的氧化膜是一層熱 氧化膜。 26. 根據申請專利範圍第20項的方法,其中該絕緣膜具有ON的結構, 是由氧化膜和氮化膜連續堆®而成的。^ 27. 根據申請專利範圍第26項的方法,其中該氧化膜是一層CVD氧化 膜0 28. 根據申請專利範圍第26項的方法,其中該氧化膜是一層熱氧化 (請先閲讀背面之注意事項再填寫本頁) C — nn n^n fma I —m Km— ml —HI— m 本紙張尺度適用中國國家標準(CNS ) A4规格(210X297公釐)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950017272A KR0172273B1 (ko) | 1995-06-24 | 1995-06-24 | 플래쉬 메모리 셀의 제조방법 |
Publications (1)
Publication Number | Publication Date |
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TW312853B true TW312853B (en) | 1997-08-11 |
Family
ID=19418160
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW085107439A TW312853B (en) | 1995-06-24 | 1996-06-19 | Flash memory cell and manufacturing method thereof |
Country Status (4)
Country | Link |
---|---|
US (1) | US5702965A (zh) |
KR (1) | KR0172273B1 (zh) |
CN (1) | CN1071496C (zh) |
TW (1) | TW312853B (zh) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6124189A (en) * | 1997-03-14 | 2000-09-26 | Kabushiki Kaisha Toshiba | Metallization structure and method for a semiconductor device |
KR19980076997A (ko) * | 1997-04-16 | 1998-11-16 | 성재갑 | 치주질환 치료용 국소약물송달제제 |
US5981341A (en) * | 1997-12-05 | 1999-11-09 | Advanced Micro Devices | Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory core |
KR100451491B1 (ko) * | 1997-12-08 | 2005-04-06 | 주식회사 하이닉스반도체 | 플래쉬이이피롬셀및그의제조방법 |
US5940706A (en) * | 1997-12-11 | 1999-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd | Process for preventing misalignment in split-gate flash memory cell |
TW425660B (en) * | 1997-12-12 | 2001-03-11 | Mosel Vitelic Inc | Method of forming uniform dielectric layer between two conductive layers in integrated circuit |
US6194272B1 (en) | 1998-05-19 | 2001-02-27 | Mosel Vitelic, Inc. | Split gate flash cell with extremely small cell size |
US6346725B1 (en) * | 1998-05-22 | 2002-02-12 | Winbond Electronics Corporation | Contact-less array of fully self-aligned, triple polysilicon, source-side injection, nonvolatile memory cells with metal-overlaid wordlines |
US6184089B1 (en) * | 1999-01-27 | 2001-02-06 | United Microelectronics Corp. | Method of fabricating one-time programmable read only memory |
WO2000051188A1 (en) * | 1999-02-23 | 2000-08-31 | Actrans System, Inc. | Flash memory cell with self-aligned gates and fabrication process |
US6071777A (en) * | 1999-04-29 | 2000-06-06 | Winbond Electronics Corporation | Method for a self-aligned select gate for a split-gate flash memory structure |
US6355527B1 (en) | 1999-05-19 | 2002-03-12 | Taiwan Semiconductor Manufacturing Company | Method to increase coupling ratio of source to floating gate in split-gate flash |
US6174772B1 (en) | 1999-07-06 | 2001-01-16 | Taiwan Semiconductor Manufacturing Company | Optimal process flow of fabricating nitride spacer without inter-poly oxide damage in split gate flash |
KR100376270B1 (ko) * | 1999-12-28 | 2003-03-17 | 주식회사 하이닉스반도체 | 스플리트 게이트형 플래쉬 메모리 소자의 제조방법 |
TW466710B (en) * | 2000-09-08 | 2001-12-01 | United Microelectronics Corp | Manufacturing method of Flash memory |
KR100971206B1 (ko) * | 2002-12-30 | 2010-07-20 | 동부일렉트로닉스 주식회사 | 반도체 장치의 제조 방법 |
US20040142525A1 (en) * | 2002-12-30 | 2004-07-22 | Kim Seok Su | Method of manufacturing a semiconductor device |
WO2004077498A2 (en) * | 2003-02-26 | 2004-09-10 | Koninklijke Philips Electronics N.V. | Method of manufacturing a non-volatile memory cell with a lateral select gate |
JP2004303918A (ja) * | 2003-03-31 | 2004-10-28 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
US6878986B2 (en) * | 2003-03-31 | 2005-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Embedded flash memory cell having improved programming and erasing efficiency |
CN1324693C (zh) * | 2003-07-24 | 2007-07-04 | 旺宏电子股份有限公司 | 闪存的制造方法 |
KR100559994B1 (ko) * | 2003-08-08 | 2006-03-13 | 동부아남반도체 주식회사 | 측벽 방식을 이용한 플래시 메모리의 플로팅 게이트 형성방법 |
KR101068141B1 (ko) * | 2004-06-18 | 2011-09-28 | 매그나칩 반도체 유한회사 | Meel 소자 제조방법 |
US7319618B2 (en) * | 2005-08-16 | 2008-01-15 | Macronic International Co., Ltd. | Low-k spacer structure for flash memory |
CN1983602B (zh) * | 2005-12-13 | 2012-01-04 | 松下电器产业株式会社 | 半导体存储装置、其制造方法及其驱动方法 |
US8528888B2 (en) | 2011-05-27 | 2013-09-10 | Gregory A. Header | Flanged material and standing seam clamp |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4981813A (en) * | 1987-02-24 | 1991-01-01 | Sgs-Thomson Microelectronics, Inc. | Pad oxide protect sealed interface isolation process |
US5153145A (en) * | 1989-10-17 | 1992-10-06 | At&T Bell Laboratories | Fet with gate spacer |
JPH04217373A (ja) * | 1990-12-18 | 1992-08-07 | Sharp Corp | 不揮発性記憶装置およびその製造方法 |
US5284784A (en) * | 1991-10-02 | 1994-02-08 | National Semiconductor Corporation | Buried bit-line source-side injection flash memory cell |
US5496747A (en) * | 1993-08-02 | 1996-03-05 | United Microelectronics Corporation | Split-gate process for non-volatile memory |
US5479368A (en) * | 1993-09-30 | 1995-12-26 | Cirrus Logic, Inc. | Spacer flash cell device with vertically oriented floating gate |
US5474947A (en) * | 1993-12-27 | 1995-12-12 | Motorola Inc. | Nonvolatile memory process |
US5445984A (en) * | 1994-11-28 | 1995-08-29 | United Microelectronics Corporation | Method of making a split gate flash memory cell |
-
1995
- 1995-06-24 KR KR1019950017272A patent/KR0172273B1/ko not_active IP Right Cessation
-
1996
- 1996-06-19 US US08/666,013 patent/US5702965A/en not_active Expired - Lifetime
- 1996-06-19 TW TW085107439A patent/TW312853B/zh not_active IP Right Cessation
- 1996-06-24 CN CN96110736A patent/CN1071496C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1071496C (zh) | 2001-09-19 |
KR970004035A (ko) | 1997-01-29 |
CN1155762A (zh) | 1997-07-30 |
US5702965A (en) | 1997-12-30 |
KR0172273B1 (ko) | 1999-02-01 |
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