五、發明説明（ 414951 A7 B7 發明領域： 本發明係與 形成電極之方法 成電容單元。 發明背景： 種半導體製程有關1特別是有關於一種 可配合高介電常數介電材質的應用，形 請 先 閱， 讀 背 ιέ 之 注 意 事 項書镦 經濟部中央標準局員工消f合作社印裝 自從積體晶片的誕生後，半導體工業已進行了近半世 紀的持續研發，以生產高效能、高密度的積體電路，在積 體電路晶月的應用之中，記憶體晶片是在多數電子產品應 用上最為重要的晶片之一，随著電腦、通訊、以及消費性 電子產品銷售市場的快速成長，對不同種類記憶體、例如 揮發性的動態隨機存取記憶體（d y n a m i c r a n d 〇 m a c c e s s memory;· DRAM)與靜態隨機存取記憶體（static random access memory; SRAM)、以及非揮發性的快閃記憶體（flash m e m o r y)等，其需求曰益殷切，以進一步提昇元件的功能與 操作性。一般而言，目前在單一積體電路晶片上已能容納 高達數百萬個、甚至數億個以上的元件，以擴充積體電路 的記憶體容量及電路的功能性；而以應用頻繁的動態隨機 存取記憶體而言，單一晶片的記憶容量已由1 6至6 4百萬 位元組（megabyte; MB) '逐漸增加至百萬位元，组、甚至是 更高的容量。 傳統上動態隨機存取記憶單元的結構主要可包含一個 訂 )線 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2!ΟΧ2ί>7公釐} 經濟部中央標準局員工消費合作社印製 414951 A7 ' B7 五、發明説明（） _ 操作的電晶體以及一做為儲存單元的電容，為了增加單位 一 晶片面積上記憶單元的元件密度，必需將電晶體及電容的 尺寸加以縮減，並在縮減的同時避免其操作特性及容量受 到影響；為了達成此一目的，習知技術中亦發展出許多種 方法，例如改變電容或電極的結構、使用不同的電極或介 電材質等，以增加小尺寸元件的儲存能力。 在目前半導體的製造技術之中，具有高介電常數 (dielectricconstant)的介電材質，已逐漸應用於揮發性及非 揮發性記憶單元的製造之中，以提昇其運作特性，現今如 鎖链欽化合物（b a r i u m s t r ο n t i u m t i t a n a t e ; B S T)及船鋅欽化 合物（lead zirconate titanate; PZT)等的高介電常數之介電 材，皆為製造高達四十億位元组（4 g i g a b y t e ; G Β )以上動態隨 機存取記憶體、以及高電容效應的非揮發性記憶體應用上 的較佳選擇；而相配合於這些高介.電常數之介電材質，可 使用如 4白（platinum; Pt)' 氧化釕（Ruthe.ii ium oxide; Ru〇2)， 氧化银（Iridium oxide; Ir〇2)等等的電極材質，以提昇良好 的電容效應。 然而，上述的電極材質，並非目前半導製造中經常使 用的電極材料，如目前慣用的多晶矽、鈦、及以鋁做為主 成分的金屬材料等，因此在姓刻化學成分、控制、以及污 染問題上的的挑戰，會形成其應用上的障礙。以鉑為例， 傳統用以定義圖案及形狀的鉑蝕刻製程，會因揮發性鉑蝕 刻副產物的生成，而有尺寸控制上準確度不佳的問題。 本紙張尺度適用中國國家標準（CNS ) A4墀格（210X 297公漦） (請先閱讀背面之注意事項再填寫本頁) 訂 414951 A7 B7 五、發明説明（ 除了使用不同的介電材質及電極材料之外，另一種增 加動態隨機存取記憶體之效能的方法，即是藉由增加電容 電極的表面積，來增加其儲存容量。其中的方法之一，即 是藉由改變電極的外形及形狀、例如加入鰭狀或是使用半 球形晶粒（hemispherical grain; HSG)的多晶石夕表面等，來增 加其可供利用的表面積。然而，在上述的新一代電極材料 之中，例如鉑、氧化.釕、氧化銥等，由於蝕刻製程上的限 制，並無法定義較為複雜的形狀*因此使得以改變彤狀來 增加表面積的應用，在受限於圖案定義的限制及製程挑戰 上，無法有效的應用。 發-明目的及概述： 請 先 閱V. Description of the invention (414951 A7 B7 Field of the invention: The present invention is a capacitor unit formed by the method of forming electrodes. Background of the invention: Related to a semiconductor process 1 In particular, it is related to an application that can be used with a high dielectric constant dielectric material. Read the first, read the back of the book of caution 镦 The staff of the Central Standards Bureau of the Ministry of Economic Affairs has printed the cooperative. Since the birth of the integrated chip, the semiconductor industry has been conducting continuous research and development for nearly half a century to produce high-efficiency, high-density Integrated circuit, in the application of integrated circuit crystal moon, memory chip is one of the most important chips in the application of most electronic products. With the rapid growth of the computer, communications and consumer electronics sales market, Different types of memory, such as volatile dynamic random access memory (DRAM) and static random access memory (SRAM), and non-volatile flash memory ( flash memory), etc., and its demand is eager to further improve the function and operation of components Generally speaking, at present, a single integrated circuit chip can accommodate up to millions, even hundreds of millions of components, in order to expand the memory capacity of the integrated circuit and the functionality of the circuit; In terms of dynamic random access memory, the memory capacity of a single chip has gradually increased from 16 to 64 megabytes (megabytes; MB) to millions of megabytes, and even higher capacities. Traditionally, the structure of the dynamic random access memory unit can mainly include one order. The size of the paper is applicable to the Chinese National Standard (CNS) Λ4 specification (2! 〇Χ2ί > 7 mm) printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 414951 A7 'B7 V. Description of the invention () _ Operating transistor and a capacitor used as a storage unit. In order to increase the element density of the memory unit per chip area, the size of the transistor and capacitor must be reduced. At the same time, its operating characteristics and capacity are not affected; in order to achieve this, many methods have been developed in the conventional technology, such as changing the structure of capacitors or electrodes, Use different electrodes or dielectric materials to increase the storage capacity of small-sized components. In the current semiconductor manufacturing technology, dielectric materials with high dielectric constant have gradually been used in volatile and non-volatile materials. In the manufacture of sexual memory cells, in order to improve its operating characteristics, today, such as high-k dielectric materials such as bariumstr ο ntiumtitanate (BST) and lead zirconate titanate (PZT), Both are better choices for manufacturing up to 4 gigabytes (4 gigabytes; G B) of dynamic random access memory, and non-volatile memory with high capacitance effect; and match these high media. For the dielectric material of the dielectric constant, electrode materials such as 4 white (platinum; Pt) 'ruthenium oxide (Ruthe.ii ium oxide; Ru〇2), silver oxide (Iridium oxide; Ir〇2), etc. can be used to improve Good capacitance effect. However, the above-mentioned electrode materials are not the electrode materials often used in the current semiconductor manufacturing, such as polycrystalline silicon, titanium, and aluminum-based metal materials. Therefore, the chemical composition, control, and pollution are engraved on the surname. Challenges on issues can create obstacles to their application. Taking platinum as an example, the traditional platinum etching process used to define the pattern and shape has the problem of poor accuracy in size control due to the generation of volatile platinum etching by-products. This paper size applies Chinese National Standard (CNS) A4 grid (210X 297 cm) (Please read the precautions on the back before filling out this page) Order 414951 A7 B7 V. Description of the invention (except the use of different dielectric materials and electrodes In addition to materials, another way to increase the performance of dynamic random access memory is to increase the storage capacity of the capacitor electrode by increasing its surface area. One of the methods is to change the shape and shape of the electrode For example, adding fin-shaped or polycrystalline stone surfaces using hemispherical grain (HSG) to increase the available surface area. However, among the new generation electrode materials mentioned above, such as platinum, Oxidation. Ruthenium, iridium oxide, etc., due to the limitation of the etching process, can not define a more complex shape. Therefore, the application of increasing the surface area by changing the shape of the tung is not effective due to the limitations of the pattern definition and the process challenges. Application-Vision and Overview: Please read
I 經濟部中央標準局員工消費合作社印製 本發明的目的為提供一種形成電極的方法。 本發明的另一目的為提供形成電極的方法，可配合高 介電常數介電材的使用，以形成電容元件。 本發明的再一目的為提供形成電極的方法，可避免傳 統製程須應用蝕刻步驟來定義導體材料圖案的缺點，提昇 尺寸的控制性。 本發明的再一目的為提供一種形成電極、以增加其表 面積的方法。 . 本發明中形成電極於一半導體基材上之方法，可包含 以下步驟：首先形成一電極定義層於基材上；接著圖案化 電極定義層以形成開口於其内；並形成第一導體層填入於 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X2W公釐） 414951 A7 B7 五、發明説明 開口之内、並形成於電極定義.層之上；再去除位於開口以 外的第一導體層；之後去除電極定義層以留下第一電極。 以較佳實施例而言，上述之電極定義層可使用氧化矽 層及氮化矽層、或是光阻層等，並可配合低溫濺鍍的方法 來形成第一導體層；而部分第一導體層之去除、可使用化 學機械研磨的製程。除了上述製作電極的步驟之外，亦可 進一步加入以下之步驟，以製作電容，包含於上述之電極 定義層去除後，形成介電層於第一電極上；最後並形成第 二導體層於介電層上，以形成電容。 圖式簡單說明： 請 龙 閱 讀 背 面 之 注 意 事 項I Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economics The object of the present invention is to provide a method for forming electrodes. Another object of the present invention is to provide a method for forming an electrode, which can be used with a high-k dielectric material to form a capacitor. A further object of the present invention is to provide a method for forming an electrode, which can avoid the disadvantages of the conventional process in which an etching step is required to define a conductive material pattern, and improve the size controllability. A further object of the present invention is to provide a method for forming an electrode to increase its surface area. The method for forming an electrode on a semiconductor substrate in the present invention may include the following steps: first forming an electrode defining layer on the substrate; then patterning the electrode defining layer to form an opening therein; and forming a first conductor layer Fill in the paper standards applicable to Chinese National Standards (CNS) Λ4 specifications (210X2W mm) 414951 A7 B7 V. Description of the invention Within the opening and formed on the electrode definition layer. Remove the first conductor outside the opening Layer; the electrode defining layer is then removed to leave a first electrode. In a preferred embodiment, the above-mentioned electrode definition layer may use a silicon oxide layer, a silicon nitride layer, or a photoresist layer, etc., and may be formed with a low-temperature sputtering method to form a first conductor layer; The conductive layer can be removed by a chemical mechanical polishing process. In addition to the above steps for making an electrode, the following steps can be further added to make a capacitor, which includes a dielectric layer formed on the first electrode after removing the electrode definition layer described above; and finally a second conductor layer on the dielectric Electrical layer to form a capacitor. Schematic description: Please read the notes on the back.
t 第 圊 極 電 之 上 材 基 匕 /Ί 案 圖 ο 並圖 成意 形示 中面 明截 發的 本層 示義 顯定 第 圖 成 fr& 形f 中於 成 明 發 本 示内。 顯之圖 形 並 第 極 口 意 開示 於面 入截 填的 層上 體之 導層 一 義 定 經濟部中央標準局貝工消費合作社印製 圖 圖 三 四 第 第 圖 五 第 導 1 第 的 外 以 D 開 於 位。 除圖 去意 中示 明面 發截 本之 示層 顯體 控截 的之 程面 製表 磨链 研粗 械層 機體 i導 1 化 由 藉 中 明 發產圖 本X意 示，示 顯制面 第 後 磨 研 生 產 以 完 以 層 體 導 二 第 及 c 層圖 電示 介面 成截 形的 明作 發製 本容 示電 顯成 本紙張尺度適用中國國家標华（CNS ) A4規格（210X 297公釐） A 7 B7五、發明説明（） 經濟部中央標华局員工消費合作社印製 發明詳細說明： 本發明中提出一種形成.電極的方法，特別是應用於使 用高介電常數介電材的電容中之電極；藉由本發明中之電 極定義層的定義，可使第一導體層於沈積時、即形成電極 定義層.内開口之形狀；本發明中之.製程可避免傳統製程須 應用#刻步驟來定義如銘、氧化釕、氧化銀等材料的缺點， 因而免除尺寸控制上所會遭遇的問題，藉由本發明中所使 用的化學機械研磨、配合製程條件及研磨厚度的控制，可 進一步增加第一電極的表面積。 在不限制本發明之應用範圍下，茲以後述之實施例介 紹本發明之應用。參見第一圖所示，首先提供一半導體基 材1 0，以形成電極於其上；一般而言，在製作電極以前， 基材1 0上已形成所需的隔離區域、如場氡化區或溝渠區域 等，以及大多數的元件、如電晶體等，以藉由電容的加入 形成所需的儲存單元。基材1 0可為一矽基材，其較佳例係 使用晶向為< 1 0 0 >之矽基材，亦可視不同設計使用其他材質 或是晶向的基材。 接著形成電極定義層12於基材1 0上，以供定義電極 形狀之用，電極定義層1 2在本例中係用以做為單純定義電 極外形用途的犧牲層，因此可使用如介電材質、或是光阻 層等不同之材料，並於後續製程中再加以去除；以較佳實 施例而言，可使用如氡化矽或氮化矽等之介電材、或是傳 (諳先閱讀背面之注意事項再填寫本頁) 訂 赇； 本紙張尺度適用中國國家標準（CNS ) Λ4规格（210><297公釐） 414951 A7 B7 五、發明説明（ 經濟部中央標準局貝工消費合作社印$ί 統製程中所應用的各種光阻材料’形成之厚度約為3〇〇〇至 8000埃之間。 之後並圖案化電極定義層12,以形成開口 14於其内， 開口 14之形狀可為一般常見之圓柱形、橢圓形 '甚至是矩 形或是其他特殊的形狀等；以應用介電層做為電極定義層 12而言，電極定義層1 2可利用習知的微影製程，以形成並 定義光阻層丨6於其上方，並加入蝕刻製程來定義其形狀， 最後再將光阻層16去除；而以光阻層做為電極定義層12 而言，電極定義層12可直接使用微影製程中的曝光及顯影 步驟加以定義，而進一步簡化製程的步釋。 參見第二圖.所示，接著形成第一導體層u，以填入於 開口 1 4之内、並形成於電極定義層！ 2之上，在較佳例之 中’第一導體層 18係使用姑（platinum; Pt)、氧化釕 (Ruthenium oxide; Ru〇2)、氧化銥（Iridium oxide; Ir02)、 紘（Iridium)、以及釕（Ruthenium)等等的導電材料，為了完 全填入於開口 14之内，第一導體層18沈積之厚度可約為 2 000至4000埃以上，上述之導體材料的形成，一般係使用 如習知之化學氣相沈積法（chemical vapor deposition; CVD) 或是物理氣相沈積法（physical vapor _deposition; PVD);在 較佳實施例中，並可應用低溫濺鍍的方式加以形成，以配 合使用光阻層做為電極定義層12的應用，其製程之溫度可 低於1 5 0 °C以下、甚至低至室溫2 5 °C的範圍内，例如可利用 準直管藏鑛（collimator sputtering)、或是長直喉管減鍵（long 諳 先 閲 背 面 之 注 意 事 項t The figure of the top material base of the 圊 pole electrode is shown in the figure. ο The figure is shown intentionally in the middle of the layer. The figure is displayed on the surface of the cut-out layer. The guide layer is defined by the Central Bureau of Standards of the Ministry of Economic Affairs and printed by the Shellfish Consumer Cooperative. Figure 34. Figure 5. Drive in place. In addition to the drawing, the process of surface-level display of the surface-cut display is shown intentionally. The process of watch-making, grinding, chain-grinding, and mechanical processing of the body is guided by the X-ray of the production map of Zhongmingfa. After the first grinding process, the production is completed with the layered guide and the second layer and the c-layer diagram of the electrical display interface in the form of a cut piece. This display shows the cost of the electrical display paper. The paper size is applicable to China National Standard (CNS) A4 specifications (210X 297). (%) A 7 B 7 V. Description of the invention () Printed by the Consumers' Cooperative of the Central Standardization Bureau of the Ministry of Economic Affairs Detailed description of the invention: This invention proposes a method for forming electrodes, especially applied to the use of high dielectric constant dielectric materials. The electrode in the capacitor; by the definition of the electrode definition layer in the present invention, the first conductor layer can form the electrode definition layer when it is deposited. The shape of the internal opening; in the present invention, the manufacturing process can avoid the traditional process to be applied # Engraving steps to define the disadvantages of materials such as inscriptions, ruthenium oxide, silver oxide, etc., thus avoiding the problems encountered in size control, by using the chemical mechanical polishing used in the present invention, matching process conditions and polishing The degree of control can be further increased surface area of the first electrode. Without limiting the scope of application of the present invention, the following embodiments describe the application of the present invention. As shown in the first figure, a semiconductor substrate 10 is first provided to form an electrode thereon. Generally, before the electrode is fabricated, a required isolation region such as a field-capped region has been formed on the substrate 10. Or the trench area, etc., and most of the components, such as transistors, etc., to form the required storage unit by adding a capacitor. The substrate 10 may be a silicon substrate. A preferred example is a silicon substrate having a crystal orientation of < 10 0 >, and other materials or crystal substrates may be used depending on different designs. Next, an electrode definition layer 12 is formed on the substrate 10 to define the shape of the electrode. The electrode definition layer 12 is used in this example as a sacrificial layer that simply defines the shape of the electrode. Therefore, a dielectric such as dielectric can be used. Materials, or photoresist layers and other materials, and will be removed in subsequent processes; in a preferred embodiment, a dielectric material such as silicon nitride or silicon nitride, or Please read the notes on the back before filling in this page.) Order; This paper size applies the Chinese National Standard (CNS) Λ4 specification (210 > < 297 mm) 414951 A7 B7 V. Description of invention (Central Bureau of Standards, Ministry of Economic Affairs) The thickness of the photoresist materials used in the consumer cooperative printing process is about 3,000 to 8000 angstroms. Then, the electrode definition layer 12 is patterned to form an opening 14 therein, and the opening 14 The shape may be generally cylindrical, elliptical, or even rectangular or other special shapes. For the application of a dielectric layer as the electrode definition layer 12, the electrode definition layer 12 may use a conventional lithography. Process to form and define The resist layer 6 is formed on top of it, and an etching process is added to define its shape. Finally, the photoresist layer 16 is removed. As for the photoresist layer as the electrode definition layer 12, the electrode definition layer 12 can directly use a lithography process. The exposure and development steps are defined in this step, which further simplifies the process. See the second figure. Then, a first conductor layer u is formed to fill in the opening 14 and form the electrode definition layer! 2 above, in a preferred example, 'the first conductor layer 18 is made of platinum (Pt), ruthenium oxide (Ruthenium oxide), iridium oxide (Iridium oxide, Ir02), osmium (Iridium), In order to fill the conductive material such as ruthenium (Ruthenium) completely into the opening 14, the thickness of the first conductor layer 18 may be deposited in the range of about 2,000 to 4000 angstroms. The formation of the above conductive materials is generally used as Conventional chemical vapor deposition (CVD) or physical vapor deposition (PVD); in a preferred embodiment, it can be formed by low-temperature sputtering to match the use Photoresist layer For the application of the electrode definition layer 12, the process temperature can be below 150 ° C, or even as low as 25 ° C at room temperature. For example, collimator sputtering can be used, or Straight throat minus key (long 谙 first read the precautions on the back
裝 訂 )線 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公簸） 414951 Λ7 B7 *--—-· 五、發明説明 throat sputtering)等方式，以避免光阻層在傳統製程的高溫 下、例如300°C或是更高的溫度下，產生變形的問題。 參見第三圖所示’之後即去除位於開口 1 4以外及電極 定義層12上方的第一導體層18，本例中可使用如化學機械 研磨（chemical mechanical polish; CMP)、式 3 甘， J驭疋其他具相近 效果的平坦化方法；在較佳實施例之中，可於化學機械研 磨製程中加入較為粗糙的研漿、例.如顆粒大小約為至 2000埃之間的研漿，以形成第一導體層18研磨後的粗糙表 面，如第四圖所示，本例中立表面相姑由1、土 4 π τ，、衣m祖糙度可達到8〇〇埃或 以上。 、 本發明十另一種增加表面粗糙度以摇 θ , t 知供較大表面積的 方法，即是形成厚度較厚的第一導體屉 + 祖增18，使其表面高度Binding) The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297). 414951 Λ7 B7 * -----V. Description of invention: Throat sputtering) and other methods to avoid photoresist layer under the high temperature of traditional process , Such as 300 ° C or higher temperature, the problem of deformation. Referring to the third figure, 'the first conductive layer 18 located outside the opening 14 and above the electrode definition layer 12 is removed. In this example, chemical mechanical polish (CMP), formula 3, J Yuhuan has other flattening methods with similar effects. In a preferred embodiment, a rougher slurry, such as a slurry with a particle size of about 2000 angstroms, can be added to the CMP process. As shown in the fourth figure, the rough surface of the first conductor layer 18 after grinding is formed. As shown in the fourth figure, the neutral surface in this example has a roughness of 1, 4 π τ, and a roughness of 800 m or more. 10. Another method of increasing the surface roughness of the present invention to shake θ, t is to provide a larger surface area, that is, to form a thicker first conductor drawer + Zu Zeng 18 to make its surface height
與電極定義層表面之高度差達到20〇〇 S 至7000埃之間*以 增加研磨製程處理的時間，在較長_ π 了间的研磨作用之下， •可藉由研漿、以及因研磨同步產生的w 堪1屑，來加強研磨 的作用’使研磨後的表面吏為粗链；D i 以本例而言，第一導 體層18在沈積形成後的表面粗糙度热 、J為5 0埃，而在利用 上述的方法進行研磨之後，其表面杈㈣ 、 以上。因此，藉由上述的兩種方式，疋 ^ ^ ·*使電極的總面稽、 經濟部中央標準局員工消費合作社印製 也就是電容的可利用面積大為增加，_^± “ 、 在較佳例中，盆表面 積可增加至原來平坦表面時之表面積的， τ 货的1.5倍至3倍之間。 接著即去除電極定義層12，以留τ* 一 W下多個第—電極u， 如第五圖所示，在以介電材料做為電★ ^ 疋義層1 2的應用之 本紙悵尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） 414951 A7 -----一 」7 五、發明說明（ ） —— 中’殘餘的氧化矽可以溼蝕刻的方式利用稀釋的氫氟酸（HF) 或疋緩衝性的氧化層姓刻劑（buffere(j 〇xide etch; BOE)加以 去除’若是使用氮化矽，則可使用熱磷酸（H3p〇4)溶液加以 去除’而以光阻做為電極定義層12的應用之中，則可使用 般的光阻剝除程序加以處理；而於最後留下依照開口 i 4 形狀所定義的第一電極1 8。 除了上述用以形成第一電極1.8的製程之外，並可進— 步加入兩道後續的製程，以完成電容單元的製作。首先形 成”電層2 0 .於第一電極1 8之上，在較佳實施例之中可使 用具有高介電常數（high k)、也就是介電常數在約2〇〇以上 的』1电材料、如銷链欽化合物（bariuin strontium titanate; BST)、錯鋅叙化合物（iead zirconate titanate; PZT)、以及摻 亦隹鋼之船鋅鈦化合物（lanthanum-doped PZT (PLZT)等，以提 昇電容的效能及操作特性，本例中介電層2 〇之厚度可約為 5〇至200埃之間；接著並形成第二導體層22於介電層2〇 上’在較佳實施例中，第二導體層22可使用與第一電極1 8 相同之材料’如上述之翻（platinum;pt)'氧化.釕（Ruthenium 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) oxide; Ru02)、氧化銀（indium oxide; Ir〇2)、銀（Iridium)、 以及針（Ruthenium)等等的導電材料；亦可使用其他的導電 材料，如多晶石夕或金屬等。 因此’本發明中用以形成電極之方法，尤其是應用於 翻（platinum; Pt)、氧化釕（Ruthenium oxide; Ru02)、氧化銥 (Iridium oxide; Ir02)、銀（Iridium)、以及釕（Ruthenium)等 本紙張尺度適用中國國家標準（CNS )八4規格（210X29"/公釐） 414951 A7 B7 五、發明説明（ 等以往較 數材質的 寸控制的 義時使用 一步減少 化，提昇 本發 解本發明 域技藝者 範圍内， 保護範圍 少利用導體材料之製 應用之中，並避免傳 問題，藉由低溫濺鍍 介電層所需的額外沈 製程的數目及時間 電極可供利用的表面 明以一較佳實施例說 之實施，非用以限定 於領悟本發明之精神 當可作些許更動潤飾 當視後附之申請專利 程方法，可配合於高介電常 統蝕刻製程的挑戰問題及尺 的應用，可消除電極形狀定 積、蝕刻、及去除步驟，進 =並藉由本發明中製程的變 積。 明如上，僅用於藉以幫助了 本發明之精神，而熟悉此領 後，在不脫離本發明之精神 及等同之變化替換，其專'利 範圍及其等同領域而定。 請 聞 ♦ 背 之 注 意 ψ 項 再 填 寫 本 頁 經濟部中央標準局員工消費合作社印製 本纸張尺度適用中國國家標準（CNS ) A4規格（2】Ο X 297公釐）The height difference from the surface of the electrode definition layer is between 200 s and 7000 angstroms * to increase the processing time of the grinding process, under the longer grinding effect of π π. Simultaneously generated w can be 1 chip to enhance the grinding effect, so that the polished surface is a thick chain; D i In this example, the surface roughness of the first conductor layer 18 after deposition is hot, and J is 5 0 angstroms, and after grinding by the above-mentioned method, the surface of the surface is ㈣ 以上 or more. Therefore, with the two methods mentioned above, 疋 ^ ^ · * makes the general surface of the electrode, printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, that is, the available area of the capacitor is greatly increased. In a good example, the surface area of the basin can be increased to 1.5 times to 3 times the surface area of the original flat surface. Then, the electrode definition layer 12 is removed to leave τ * -W multiple first electrodes u, As shown in the fifth figure, in the application of the dielectric material as the electrical layer, the paper's standard is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) 414951 A7 ----- 一”7 V. Explanation of the invention () —— Residual silicon oxide can be used in the manner of wet etching using dilute hydrofluoric acid (HF) or thorium-buffered oxide layer etcher (buffere (j 〇xide etch; BOE) Removal 'If silicon nitride is used, it can be removed by using hot phosphoric acid (H3p04) solution'. In applications where photoresist is used as the electrode definition layer 12, it can be processed using a general photoresist stripping procedure. ; And at the end leave the first electric power defined by the shape of the opening i 4 1 8. In addition to the above-mentioned process for forming the first electrode 1.8, two further processes can be further added to complete the production of the capacitor unit. The "electrical layer 2 0" is first formed. The first electrode 1 8 Above, in a preferred embodiment, a "1" electrical material having a high dielectric constant (high k), that is, a dielectric constant above about 2000, such as a bariuin strontium titanate; BST can be used. ), Iead zirconate titanate (PZT), and lanthanum-doped PZT (PLZT), etc., to improve the performance and operating characteristics of the capacitor. In this example, the dielectric layer 2 〇 The thickness may be between 50 and 200 angstroms; then a second conductor layer 22 is formed on the dielectric layer 20. In a preferred embodiment, the second conductor layer 22 may be the same as the first electrode 18 The material is "platinum; pt" as described above. Oxidation. Ruthenium (printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) oxide; Ru02), silver oxide (indium oxide; Ir〇2), silver (Iridium), and needle Ruthenium) and other conductive materials; other conductive materials can also be used, such as polycrystalline stone or metal. Therefore, 'the method used to form the electrode in the present invention, especially applied to platinum (Pt), ruthenium oxide (Ruthenium oxide; Ru02), Iridium oxide (Ir02), silver (Iridium), and ruthenium (Ruthenium) and other paper standards applicable to the Chinese National Standard (CNS) eight 4 specifications (210X29 " / mm) 414951 A7 B7 V. Description of the invention (In the past, the size control of previous comparative materials was used to reduce the use of one step to improve the scope of the present invention. It is within the scope of the artist of the present invention, and the protection scope is less in the application of conductor materials, and to avoid transmission problems. The number of additional sinking processes required for the low temperature sputtering of the dielectric layer and the time available for the electrodes are implemented in a preferred embodiment, not limited to understanding the spirit of the present invention. The patented process method attached after retouching can be used to meet the challenges of high-dielectric conventional etching processes and the application of rulers, which can eliminate electrode shape fixation, etching, and Addition step, and by feeding = variable area of the present invention the process. The above description is only used to help the spirit of the present invention, and after being familiar with this, it can be replaced without departing from the spirit of the present invention and equivalents. Please read ♦ Note on the back Please fill in this page. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs.