472339 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 發明領域： 本發明係有關於一種半導體元件及製造技術’特別是 有關於一種具有垂直結構之鐵電電容（Ferroelectric capacitor) 〇 發明背景： 近年來，非揮發性鐵電記憶體（FRAM)已普遍地引起各 界的注意，並且不斷地發展其製造技術。在非揮發性鐵電 記憶體中，每一個鐵電記憶胞之電容器均具有一層鐵電薄 膜作為電容器之介電層，用以儲存資料。 鐵電薄膜具有電場極化之特性，當電場施加於鐵電薄 膜’鐵電薄膜會隨電場方向極化，並且在電場移除之後， 極化現象依然存留於鐵電薄膜，不會隨外加電場的移除而 消失。利用鐵電薄膜極化且可長久保留之特性，逐發展出 可長久保存資料之鐵電電容’進而應用製造出鐵電記憶 體。 一般每一個鐵電記憶胞由一個金氧半（M〇S)電晶體以 及一個鐵電電容所組成。藉由MOS電晶體的切換，將鐵電 電容切換在兩個相反的極化狀態，藉以储存資料，，〇” 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ,-----------裝---------訂---------皆 (請先閱讀背面之注意事項再填寫本頁) 472339 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 與”1”，即使電源關閉，儲存在記 kIT的資料亦可县 保存’不會流失。4些特性是傳統的記憶體所無法達到的 特性’傳統的快閃€憶體（Flash memQry)雖然亦可以在電源 關閉之後將資料保留，不過必須 作，否則儲存的資料亦會流失。而/ ^再寫入的動 ^ ^ t 鐵電記憶體的操作 電壓僅需5V，遠低於快閃記憶體操作所需的i8v，所消耗 的電力更少。 傳統的鐵電記憶胞之電容器如同一般記憶體的電蓉 器，通常為堆疊形式之結構，如第i圖所示。以一電晶體/ 一電容器（1171C)之結構為例，其形成方法一般是先在半導 體基底10上形成電晶體的閘極12、閘極介電層14以及源 極/汲極區16之後，再覆蓋上一層介電層2〇，然後在介電 層20中形成接觸窗插塞22連接到源極/汲極區i 6之一’ 最後再接觸窗插塞22上形成鐵電電容^傳統的鐵電電容係 以「平面方式」由下向上堆疊，在下電極24上形成鐵電薄 膜26 ’並且在鐵電薄膜26上形成上電極28。此種鐵電電 各為.了維持足夠之電容量’必須提供足·夠的平面面積，以 保持儲存資料的長久性。當記憶體的積集度不斷增加，使 鐵電記憶胞的可用面積縮小，相對地鐵電電容的面積就必 須縮小，往往造成電容量不足的問題。 此外，一般平面電容的形成均是利用沉積方式形成薄 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I— 1IIIIIU — ---I ! I I I ^ « — — — III I I ^ (請先閱讀背面之注意事項再填寫本頁) 472339 A7 B7 五、發明說明（ 膜’然後利用微影及蝕刻技術，定義出電容器的形狀。但 是在電極沉積的過程中，會因為上下結晶的差異，造成局 部導電性不佳的問題，而且在蝕刻的過程中，電容器的邊 緣往往會因為蝕刻的破壞，造成結構性不佳，容易有區域 漏電的問題發生。 發明目的及概述： 鑒於上述之發明背景中，平面堆疊電容結構使用過大 的面積無法再縮小，影響記憶體容量的提昇，以及製作過 程中所發生的製程問題。因此’本發明提供一種垂直鐵電 電容結構及其製造方法’可以進一步地縮小電容的使用面 積’增進記憶體的記憶容量，而且可以降低製造過程中沉 積及餘刻的問題。 不發明提供一種鐵電 基底上。此鐵電電容之結構包括兩片垂直之平板電極，以 及夾於平板電極之間的鐵電層。平板電極的高度大於其厚 度，而且平板電極的高度大於鐵電層的厚度。 —-----------裝--------訂· (靖先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本發明亦提供一種垂直鐵電電容的製造方法。首先在 半導體基底上形成一層絕緣層，且絕緣層中具有一第一開 口與一第二開口 ，第一開口與第二開口之高度大於兩者之 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） 472339 A7 _____ B7 五、發明說明（ 間的距離。接著在第一開口與第二開口中填入導電材料， 比如是舶，以形成下電極與上電極。之後去除下電極與上 電極之間的部分絕緣層，在下電極與上電極之間形成開 口。然後在下電極與上電極之間的開口填入鐵電材料，比 如是鈦酸鉛锆（PZT)，作為電容器的介電層。 由於本發明之上、下電極係以垂直並行的方式排列， 因此只要增加電容器的高度即可有效地縮小電容器的使用 面積，藉此記憶體内記憶胞的數量，提昇記憶體的記憶容 量。而且’可以大幅地降低製作過程中蝕刻破壞的問題。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述，其中： 第1圖為習知一種具有平面結構之鐵電電容；以及 第2A-2H圖為本發明之垂直鐵電電容之製程剖面示意 圖。 圖號對照說明： I --------••裝--------訂---------«# (請先閱讀背面之注音？事項再填窵本頁) 經濟部智慧財產局員工消費合作社印製 1〇 半導體基底 14 閘極介電層 12 閘極 16 源極/ >及極區 私紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 472339 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 20 絕緣層 _ 22 接觸窗插塞 24 下電極 26 鐵電層 28 上電極 30 絕緣層 100 半導體基底 102 閘極 104 閘極介電層 106 源極/淡極區 110 絕緣層 112 接觸窗插塞 120 絕緣層 122 下電極開口 124 上電極開口 126 ' 12 6a 阻障層 128 導電層 132 下電極 134 上電極 136 開口 138 鐵電層 140 電容鐵電層 Wh 電容寬度 Wv 電容寬度 Wj > w2 電極厚度 D 電極高度 A7 B7 d 鐵電層厚度 發明詳細說明： 本發明提供一種垂直鐵電電容之結構及其製造方法， 可縮小每個電容的使用面積，增加單位面積的記憶元件數 量，進而增進記憶體的記憶容量。 第2A-2H圖為本發明之垂直鐵電電容之製程剖面示意 圖。請參照第2A圖，首先提供一半導體基底100，例如是 本紙張尺度適用+國國家標準（CNS)A4規格（210 X 297公釐） —-----------裝--------訂.--------r (請先閱讀背面之注意事項再填寫本頁) 472339 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 具有<100>結構之P型矽基底。在基底100上已完成部分之 半導體元件之製作，在基底100之主動區域上製作出電晶 體’通常包括閘極102,在閘極102與基底1〇〇之間的閘 極氧化層104’以及位於閘極1〇2兩側之源極/汲極區。 在電晶體上覆蓋有一層第一絕緣層i 10，比如是二氧化矽、 旋塗式玻璃（SOG)、低介電（Low-k)材質或是其組合。在絕 緣層11〇中具有一接觸窗插塞112耦接至源極/汲極區 1〇6，接觸窗插塞i 12所使用之材質比如是鎢、複晶矽 (Poly-Si)或是掺雜複晶石夕（D〇pedp〇ly_si)等，其製造方法一 般是利用微影及蝕刻技術，在第一絕緣層j丨〇上形成一層 圖案化光阻層（未顯示），接著以此圖案化光阻層為罩幕， 蝕刻暴露出之第一絕緣層110，在第一絕緣層11〇中形成 接觸窗開D，之後去除圖索化総層，㈣在接觸窗開口 中填入導電物質，比如是鎢，形成接觸窗插塞 凊參照第2B圖，接著在第一絕緣層又1〇上覆蓋一層第 二絕緣層120,其材質比如是二氧化矽、s〇G、L〇w_k材質 或是其組合。接著在第二絕緣層12〇上形成一層圖案化光 阻層（未顯示），其具有所需之圖案，然後以此圖案化光阻 層為罩幕’蝕刻暴露之部分第二絕緣層l2〇，在第二絕緣 層120中形成第一開口 122與第二開口 124，亦分別稱為 下電極開口與上電極開口，第一開口 122之底部暴露出底 下的接觸窗插塞112，之後去除圖案化光阻層。所形成之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） -^--------^---------# (請先間讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 472339 A7 -----B7____ 五、發明說明（） 第一開口 122與第二開口 124之間的距離小於第一開口；[22 與第一開口 124之深度。而且第一開口 122與第二開口 124 之縱寬比約在1.5 : 1以上，且可達1 〇 : 1以上，縱寬比愈 问’所形成之鐵電電容所佔面積愈小’但需視實際之製程 技術來決定。 請參照第2C圖，在第一開口 122與第二開口 124内填 入導電材料之前’較佳是先在第一開口 122與第二開口 124 之底部與側壁形成一層阻障層126，其材質比如是鈦（Ti)、 氣化鈦（TiN)、鎢（W)等。例如可利用化學氣相沉積法（CVD) 或是物理氣相沉積法（pVD)在基底100的表面形成一層共 形的阻障層126，可避免第二絕緣層、2〇令的水氣侵入後 續填入的導電材料。 請參照第2D圖，在第二絕緣層120上形成一層導電材 料128，並且填滿第一開口 122與第二開口 124，導電材料 層128之材質比如是鉑（pt)、釕（ru)、铑（Rh)或是铑氧化物 等。 請參照第2E圖，接著進行平坦化步驟，比如使用化學 機械研磨（CMP)或是毯覆式触刻（Blanket etching)，去除第 一絕緣層.120上之部分導電材料128以及阻抗層126，僅 留下在第一開口 122與第二開口 124内之部分導電材料與 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） II -敦-------—訂·--------# (請先閱讀背面之注意事項再填寫本頁} 五、發明說明（） 阻·ί几層126a’在第—開口 &笛-ua 122與第—開口 124内的導電材 料分別形成下電極13 2與上雷^ j 興上電極134。其中，下電極132 與接觸窗插塞112耦接，计b & 4 祸按並且透過接觸窗插塞112與電晶 體之源極/没極區1 〇 6雷性捸姑 .Φ n 4 f生連接，由電晶體控制電容之電性 操作》在形成下電極132與上電極134之後，可選擇性地 利用毯覆式蝕刻技術去除部分下電極132與上電極ΜΑ， 然後再填人阻障層，包覆整個下電極m與上電極134。 請參照第2F圖，接著去除在下電極132與上電極134 之間的部分第二絕緣層12〇，以在下電極132與上電極134 之間形成開口 136。形成開口 136的方法先在第二絕緣層 120上形成一層圖案化光阻層（未顯示），此圖案化光阻層中 具有形成開口 136所需之圖案，接著以此圖案化光阻層為 罩幕，蝕刻暴露之部分第二絕緣層12〇，直到暴露出底下 的第一絕緣層11 〇，形成開口 13 6。 經濟部智慧財產局員工消費合作社印製 請參照第2G圖，在基底1〇〇上形成一層鐵電材料138， 並且填滿開口 136，鐵電材料層138為具有鈣鈦礦 (perovskite)結構之鐵電材料，比如是鈦酸鉛鉛（ρζ;τ)、鈦酸 鎖銘（BST)或是鈕酸锶鉍（SBT)等。形成鐵電材料層136的 方法比如是化學氣相沉積法（CVD)或是有機化學氣相沉積 法（M0CVD)等。在沉積鐵電材料層138時，由於其同時在 開口 136兩側之側壁上沉積，因此其在侧壁與底部均具有 9 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） 472339 A7472339 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (Field of the invention: The invention relates to a semiconductor element and manufacturing technology ', especially to a ferroelectric capacitor with a vertical structure. Background of the Invention: In recent years, non-volatile ferroelectric memory (FRAM) has generally attracted the attention of various circles and has continuously developed its manufacturing technology. In non-volatile ferroelectric memory, the capacitor of each ferroelectric memory cell Each layer has a ferroelectric film as the dielectric layer of the capacitor for storing data. The ferroelectric film has the characteristic of electric field polarization. When an electric field is applied to the ferroelectric film, the ferroelectric film will be polarized with the direction of the electric field and move in the electric field. After the removal, the polarization phenomenon still exists in the ferroelectric thin film, and will not disappear with the removal of the applied electric field. Using the characteristics of ferroelectric thin film polarization and long-term retention, the ferroelectric capacitors that can store data for a long time are developed. Ferroelectric memory is manufactured by application. Generally, each ferroelectric memory cell consists of a metal oxide semiconductor (MOS) transistor and a It is composed of ferroelectric capacitors. By switching the MOS transistor, the ferroelectric capacitors are switched to two opposite polarization states to store data. 〇 ”This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm), ----------- install --------- order --------- all (please read the precautions on the back before filling this page) 472339 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The invention description (and "1", even if the power is turned off, the data stored in the kIT can be stored in the county, and will not be lost. 4 Some characteristics are traditional memory Unattainable features Although the traditional Flash memQry can also retain data after the power is turned off, it must be done, otherwise the stored data will be lost. And the movement of / ^ rewriting ^ ^ t The operating voltage of the ferroelectric memory only needs 5V, which is much lower than the i8v required for flash memory operation, and consumes less power. The capacitors of traditional ferroelectric memory cells are just like the electric fuses of ordinary memories, usually Stacked structure, as shown in Figure i. A transistor / capacitor (1171 The structure of C) is taken as an example. The formation method is generally to first form a gate 12, a gate dielectric layer 14 and a source / drain region 16 of a transistor on a semiconductor substrate 10, and then cover the dielectric layer 2 〇, and then a contact window plug 22 is formed in the dielectric layer 20 and connected to one of the source / drain regions i 6 ′. Finally, a ferroelectric capacitor is formed on the contact window plug 22 ^ Traditional ferroelectric capacitors are "Methods" are stacked from bottom to top, forming a ferroelectric thin film 26 'on the lower electrode 24 and an upper electrode 28 on the ferroelectric thin film 26. This type of ferroelectricity has its own characteristics. To maintain sufficient capacitance, a sufficient and sufficient plane must be provided. Area to maintain the longevity of stored data. When the accumulation of memory continues to increase, the usable area of the ferroelectric memory cell is reduced, and the area of the subway electric capacitor must be reduced, often causing a problem of insufficient electric capacity. In addition, the formation of general planar capacitors is formed by the deposition method. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). I— 1IIIIIU — --- I! III ^ «— — — III II ^ (Please read the precautions on the back before filling out this page) 472339 A7 B7 V. Description of the invention (The film 'then uses lithography and etching technology to define the shape of the capacitor. However, during the electrode deposition process, it will crystallize because of the upper and lower parts. The difference between them causes the problem of poor local conductivity, and during the etching process, the edges of capacitors are often damaged due to etching, resulting in poor structure, which is prone to regional leakage problems. Purpose and Summary of the Invention: In view of the above In the background of the invention, the use of an excessively large area of a planar stacked capacitor structure cannot be reduced, which affects the increase of memory capacity and process problems that occur during the manufacturing process. Therefore, the present invention provides a vertical ferroelectric capacitor structure and a manufacturing method thereof Can further reduce the use of capacitors' to increase the memory capacity of the memory, and can reduce The deposition and remaining problems during the manufacturing process. The invention does not provide a ferroelectric substrate. The structure of the ferroelectric capacitor includes two vertical plate electrodes and a ferroelectric layer sandwiched between the plate electrodes. The height of the plate electrode is greater than Its thickness, and the height of the plate electrode is greater than the thickness of the ferroelectric layer. ——————————————————— Order (Jing first read the precautions on the back before filling in this page Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention also provides a method for manufacturing a vertical ferroelectric capacitor. First, an insulating layer is formed on a semiconductor substrate, and the insulating layer has a first opening and a second opening. The height of the opening between the first opening and the second opening is greater than the size of the paper. Chinese national standard (CNS > A4 size (210 X 297 mm)) 472339 A7 _____ B7 V. Description of the invention (The distance between the first opening and the The second opening is filled with a conductive material, such as a ship, to form a lower electrode and an upper electrode. Then, a part of the insulating layer between the lower electrode and the upper electrode is removed, and an opening is formed between the lower electrode and the upper electrode. The opening between the lower electrode and the upper electrode is filled with a ferroelectric material, such as lead zirconate titanate (PZT), as the dielectric layer of the capacitor. Since the upper and lower electrodes of the present invention are arranged in a parallel parallel manner, as long as Increasing the height of the capacitor can effectively reduce the use area of the capacitor, thereby memorizing the number of memory cells in the body and increasing the memory capacity of the memory. Moreover, the problem of etch damage during production can be greatly reduced. The diagram simply explains: The preferred embodiments of the present invention will be described in more detail in the following explanatory texts with the following figures, where: Figure 1 is a conventional ferroelectric capacitor with a planar structure; and Figures 2A-2H are A schematic cross-sectional view of the manufacturing process of the invented vertical ferroelectric capacitor. Drawing number comparison description: I -------- •• installation -------- order --------- «# (Please read the phonetic on the back? Matters before filling out the transcript (Page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, 10 Semiconductor Substrates, 14 Gate Dielectric Layers, 12 Gates, 16 Sources, and Private Paper Scales Applicable to China National Standard (CNS) A4 (210 X 297) (Mm) 472339 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () 20 Insulation layer 22 Contact window plug 24 Lower electrode 26 Ferroelectric layer 28 Upper electrode 30 Insulation layer 100 Semiconductor substrate 102 Gate 104 Gate Electrode dielectric layer 106 Source / light electrode region 110 Insulating layer 112 Contact window plug 120 Insulating layer 122 Lower electrode opening 124 Upper electrode opening 126 '12 6a Barrier layer 128 Conductive layer 132 Lower electrode 134 Upper electrode 136 Opening 138 Iron Electric layer 140 capacitor ferroelectric layer Wh capacitor width Wv capacitor width Wj > w2 electrode thickness D electrode height A7 B7 d ferroelectric layer thickness Detailed description of the invention: The present invention provides a structure of a vertical ferroelectric capacitor and its manufacturing method, which can be reduced Use area of each capacitor Increasing the number of memory elements per unit area, and further enhance the memory capacity of the memory. Figures 2A-2H are schematic cross-sectional views of the manufacturing process of the vertical ferroelectric capacitor of the present invention. Please refer to Figure 2A, first provide a semiconductor substrate 100, such as the paper size applicable + National National Standard (CNS) A4 specifications (210 X 297 mm) ------------- install- ------ Order .-------- r (Please read the notes on the back before filling out this page) 472339 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (with < 100 > structure of a P-type silicon substrate. On the substrate 100, a part of the semiconductor device has been completed, and a transistor is formed on the active area of the substrate 100. Generally, the gate 102 is included, and the gate 102 and the substrate 100 are formed. The gate oxide layer 104 'between the gate and source / drain regions located on both sides of the gate 102. The transistor is covered with a first insulating layer i 10, such as silicon dioxide, spin-on glass (SOG), Low-k material, or a combination thereof. In the insulating layer 11, a contact window plug 112 is coupled to the source / drain region 106, and the contact window plug i 12 The materials used are, for example, tungsten, poly-Si, or doped polysilicon. The manufacturing methods are generally lithography and etching. To form a patterned photoresist layer (not shown) on the first insulation layer j, and then use the patterned photoresist layer as a mask to etch the exposed first insulation layer 110 and place the first insulation layer on the first insulation layer. The contact window opening D is formed in 110, and then the graphitization layer is removed. Then, a conductive material such as tungsten is filled in the contact window opening to form a contact window plug. Referring to FIG. 2B, then the first insulating layer is again 10 is covered with a second insulating layer 120, and the material is, for example, silicon dioxide, SOG, LOwk or a combination thereof. Then a patterned photoresist layer (not shown) is formed on the second insulating layer 120. (Shown), which has a desired pattern, and then uses this patterned photoresist layer as a mask to etch exposed portions of the second insulating layer 120, forming a first opening 122 and a second opening 124 in the second insulating layer 120 Also referred to as the lower electrode opening and the upper electrode opening, respectively, the bottom of the first opening 122 exposes the lower contact window plug 112, and then the patterned photoresist layer is removed. The paper size formed is applicable to the Chinese National Standard (CNS) A4 specifications (210 X 297 male Chu)-^ -------- ^ --------- # (Please read the notes on the back before filling out this page) Consumption Cooperation by Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 472339 A7 ----- B7____ 5. Description of Invention () The distance between the first opening 122 and the second opening 124 is smaller than the first opening; [22 and the depth of the first opening 124. Moreover, the aspect ratio of the first opening 122 and the second opening 124 is about 1.5: 1 or more, and It can reach more than 10: 1. The more the aspect ratio is, the smaller the area occupied by the ferroelectric capacitor is formed, but it depends on the actual process technology. Referring to FIG. 2C, before the first opening 122 and the second opening 124 are filled with a conductive material, it is preferred to form a barrier layer 126 on the bottom and sidewalls of the first opening 122 and the second opening 124. Examples include titanium (Ti), titanium gasified (TiN), tungsten (W), and the like. For example, a chemical vapor deposition (CVD) method or a physical vapor deposition (pVD) method can be used to form a conformal barrier layer 126 on the surface of the substrate 100, which can prevent the second insulating layer from invading 20 orders of moisture. Subsequent filling of conductive material. Referring to FIG. 2D, a layer of conductive material 128 is formed on the second insulating layer 120, and the first opening 122 and the second opening 124 are filled. The material of the conductive material layer 128 is, for example, platinum (pt), ruthenium (ru), Rhodium (Rh) or rhodium oxide. Please refer to FIG. 2E, and then perform a planarization step, such as using chemical mechanical polishing (CMP) or blanket etching, to remove a portion of the conductive material 128 and the resistance layer 126 on the first insulating layer 120. Only a part of the conductive material left in the first opening 122 and the second opening 124 and 8 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) II-Dun ----------- Order · -------- # (Please read the precautions on the back before filling out this page} V. Description of the invention () 几 several layers of 126a 'in the first-opening & flute-ua 122 and the first- The conductive material in the opening 124 respectively forms the lower electrode 132 and the upper electrode 134. Among them, the lower electrode 132 is coupled to the contact window plug 112, and b & 4 presses and passes through the contact window plug 112. It is connected to the source / inverter region of the transistor 1 〇6 lightning connection. Φ n 4 f is connected, and the electrical operation of the capacitor is controlled by the transistor. After forming the lower electrode 132 and the upper electrode 134, it can be selectively A blanket etching technique is used to remove a part of the lower electrode 132 and the upper electrode MA, and then a barrier layer is filled to cover the entire area. The lower electrode m and the upper electrode 134. Referring to FIG. 2F, the part of the second insulating layer 120 between the lower electrode 132 and the upper electrode 134 is removed to form an opening 136 between the lower electrode 132 and the upper electrode 134. An opening is formed The method of 136 first forms a patterned photoresist layer (not shown) on the second insulating layer 120. The patterned photoresist layer has a pattern required to form the opening 136, and then uses the patterned photoresist layer as a mask. The exposed second insulating layer 12 is etched until the first insulating layer 11 is exposed below, forming an opening 13 6. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 2G, on the substrate 100. A layer of ferroelectric material 138 is formed thereon and fills the opening 136. The ferroelectric material layer 138 is a ferroelectric material having a perovskite structure, such as lead titanate (ρζ; τ), a titanate lock ( BST) or strontium strontium bismuth (SBT) etc. The method of forming the ferroelectric material layer 136 is, for example, chemical vapor deposition (CVD) or organic chemical vapor deposition (MOCVD), etc. The ferroelectric material layer is deposited 138 o'clock due to its simultaneous opening at 136 Deposited on the side walls on both sides, so it has 9 papers on the side walls and the bottom. The paper size is applicable to National Standards (CNS) A4 (210 X 297 mm) 472339 A7
I I I k 丁 472339 A7 B7 綜上所述，本發明所提供之垂直鐵電電容結構可 少記憶元件所使用之面積，增加記憶元件之數量， 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 以減 進而增 進記憶體之記憶容量’而且可以減少製作過程中，曾^ 电各結 構不佳的問題。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 之較佳實施例而已’並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐）III k D 472339 A7 B7 In summary, the vertical ferroelectric capacitor structure provided by the present invention can reduce the area of memory elements and increase the number of memory elements. It is printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. (In order to reduce and then increase the memory capacity of the memory ', and can reduce the problem of poor electrical structure during the production process. As understood by those skilled in the art, the above is only a preferred embodiment of the present invention It has not been used to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the scope of patent application described below. This paper standard applies to countries National Standard (CNS) A4 specification (210 X 297 mm)