A7A7
經濟部智慈財產局員工消費合作社印製 519720 五、發明説明（) 發明領域： 本發明係有關於一種半導體元件及製造技術，特別 係與一種鐵電電容（Ferr〇electric capacit〇r)之製造有關。 發明背景： 近年來，非揮發性鐵電記憶體（FRAM)已普遍地引起 各界的注·意，並且不斷地發展其製造技術。在非揮發性鐵 電記憶體中，每一個鐵電記憶胞之電容器均具有一層鐵電 薄膜作為電容器之介電層，用以儲存資料。 ik著半導體工業持續的進展，鐵電記憶體元件已廣泛 的應用於積體電路中。一般而·^，一隨機存取鐵電記憶體具 有許多1己憶胞（mem〇ry cell)，且其記憶胞通常由—鐵電電容 與電晶體所構成，用以儲存一位元（bit)之訊號。其中，電晶 體之汲極或源極與鐵電電容之一端連接，而鐵電電容之另一 端則與參考電位連接，至於電晶體之另一端及閘極則分別與 位元線（bit line)及字元線（word line)連接。因此在製造隨機存 取鐵電圮憶體之記憶胞時，往往也包含了電晶體與鐵電電容 之製程，並藉著電容器與電晶體之源極區或汲極區之電性接 觸，將數位資訊儲存在電容器中，再藉由電晶體、位元線和 字元、線陣列來存取鐵電電容器之數位資料。 然而，隨著超大型積體電路（ULSI)的發展，為求得具 競爭價值之電容和佔據最小空間兩者的平衡，製程技術的改 2 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)· — --- - -----------.........、可.........%. (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 519720 五、發明説明（） 良就不可）。其中一種方式是將電容架構在較 如此，則-般上電極板就和#存節點彼此 成一般所稱的堆疊電容（stacked 。捲_㈣而形 一電二統堆二式:鐵電記憶胞之電容器如第-圖所示。以 …鐵電電容器(1T/1C)之結構為例 般是先在半導體基底10上形”形成万法— …及……之極广閘極介電 -在介電層2。中形成接觸窗鎢插塞二 源極/及極區16之一，最後再於接觸窗鎢插塞㈡上 電容。傳統的鐵電電容係以「平面方式」由下向…’： 鐵電材質薄膜26，並且在鐵電薄膜： =^ μ η μ “材f薄膜26 _般為pw3 此種堆疊式之鐵電電容雖然是最省面積的， ::鐵：材質。薄膜26時’需要-高溫製程，此製程溫度通 …於500 C，因為若此製程溫度不夠高，鐵電材質薄膜 26之結晶品質會受影響。然而在此 扠 ^ ^ 表柱下，由於猶啻 材鲁薄膜26包含Ti〇3,當執行此高溫製程時，會遭遇到高 温珉擴散導致鎢插塞22氧化的問題。傳統上對此的解 .法，有使用多晶碎插塞代替鶏插塞，來減少氧化可能性 因為多晶繼阻值較高，因此所形成之鐵電記憶體 表現上將不如使用嫣插塞。而另一種方法是以降低製程溫 Π避免產生南溫氧擴散’但是以此方法，會造 容之特性變差。因此’極需一改善方法之發明來解決上述之 本紙張尺度適用中國國家標準(CNS)A4規格(2l〇X297公爱） ----…廣.........訂.........% (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 519720 A7 B7 五、發明説明（） 問題。 發明目的及概述： 鑒於上述之發明背景中，平面堆疊電容結構在形成 過程中常常會伴隨產生高溫氧擴散，而導致鶴插塞氧化的 問題，雖可使用多晶矽插塞代替鎢插塞，來減少氧化可能 性，但因為多晶矽插塞阻值較高，會造成整體電性表現變 差。因此，本發明提供一種鐵電電容結構及其製造方法， 來降低製造過程中產生高溫氧擴散而導致鎢插塞氧化的問 題。 本發明提供一種鐵電電容之結構，其架構在一半導 體基底上。此鐵電電容之結構包括一導體間壁隙，此導體 間壁隙係架構在一導體層上，並且透過此導體層和接觸窗 鎢插基來與電晶體之源極/汲極區電性連接，由電晶體控制 電容之電性操作。同時在導體層上方與電容下電極間，夾 有一擴散阻擋層，在進行高溫製程時，可保護鎢插塞，防 止南溫氧擴散進入而與鎢插塞反應，形成一層鎢氧化層。 本發明亦提供一種具導體間壁隙鐵電電容的製造方 法首先在半導體基底上依序形成第一導體層、一層阻擔 層、下電極層及鐵電材料層，此鐵電材料層比如是鈦酸鉛 锆（PZT)，作為電容器的介電層。接著於鐵電材料層上形成 一圖案化光阻層，並以此層為罩幕蝕刻阻擋層、下電極層 及鐵電材料層。接著沈積第二導體層，同時利用乾蝕刻進 本紙張尺度適用中國國家標準(CNS)A4規格(2Ϊ0Χ297公釐) -------- —h — -11^.................. (請先閲讀背面之注意事項再填寫本頁) 519720 A7 B7 五、發明説明（） 行此層之非等向行蝕刻，形成一導體間壁隙層。接著於表 面全面性沈積一層絕緣層，同時利用另一圖案化光阻層為 罩幕對此絕緣層進行姓刻，來暴露出鐵電材料層表面，接 著沈積第三導電層作為鐵電電容之上電極。 圖式簡單說明： 由以下本發明中較佳具體實施例之細節描述，可以 對本發明之目的、觀點及優點有更佳的了解。同時參考下 列本發明之圖式加以說明： 第一圖為習知一種具有堆疊結構之鐵電電容； 第二A至第二E圖為本發明之具導體間壁隙鐵電電 容之製程剖面示意圖； 第二F圖為本發明之具導體間壁隙鐵電電容之另一 種結構示意圖；以及 第三圖為使用本發明結構於電阻性記憶體當中。 圖號對照說明： (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 10 半導體基底 12 閘極 14 閘極介電層 16 源極/汲極區 20 絕緣層 22 接觸窗插塞 24 下電極 26 鐵電層 28 上電極 30 絕緣層 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 519720 五 、發明說明（ 100 104 108 112 116 120 124 128 半導體基底 102 閘極 閘極介電層 106 源極/汲極區 鎢黏著層 110 絕緣層 接觸窗插塞 114 導體層 擴散擋層 118 下電極 鐵電材料層 122 導體間壁隙 介電層 126 導體層 開口 130 硫族化合物 發明詳細說明： (請先閲讀背面之注意事項再填寫本頁) 經濟部智慈財產局員工消費合作社印製 在不限制本發明之精神及應用範圍之下，以 —貫施例，介紹本發明之實施；熟悉此領域技藝者 解本發明之精神後，當可應用此種鐵電電容之製造 其結構於各種不同之鐵電記憶體單元中。藉由本發 法與結構，可解決傳統上於鐵電電容製造過程中所 生向溫氧擴散，而導致鵠插塞氧化的問題。同時應 明之方法與結構可不需使用多晶矽插塞來代替鎢插 減少氧化可能性，因此並不會影響整個鐵電記憶體 表現。本發明之應用當不僅限於以下所述之實施例 第二A至第二E圖為本發明之具導體間壁隙 容之製程剖面示意圖。請參照第二A圖，首先提供 體基底100，例如是具有<1〇〇>結構之P型碎基底。 100上已完成部分之半導體元件之製作，在基底100 下即以 ，在瞭 方法及 明之方 伴隨產 用本發 塞，以 之電性 〇 鐵電電 一半導 在基底 之主動 訂· 519720 A7 B7 五、發明説明（） 區域上製作出電晶體，通常包括閘極1〇2，在閘極1〇2與基 底100之間的閘極氧化層104，以及位於閘極1〇2兩側之源 極/汲極區10 6。在電晶體上覆蓋有一層絕緣層11 〇，比如是 二氧化矽、旋塗式玻璃（S0G)、低介電（L〇w㈦材質或是其組 合。在絕緣層110中具有一接觸窗插塞112耦接至源極/汲 極區106 ’接觸窗插塞112所使用之材質比如是鎢（w)、複 晶矽（Poly-Si)或是掺雜複晶矽（Doped p〇ly-Si)等，以本最佳 實施例而3為鎢。其製造方法一般是利用微影及蝕刻技 術，首先—在絕緣層110上形成一層圖案化光阻層（未顯示）， 接著以此圖案化光阻層為罩幕，蝕刻絕緣層ιι〇，以在絕緣 層110中形成接觸窗開口 ’之後去除圖案化光阻層。 在接觸窗開口内填入導電材料之前，較佳是先在接 觸窗開口之底部與側壁形成一層鎢黏著層108，其材質比如 是鈦ΓΠ)、氮化鈦（TlN)等，其製造方法一般是利用濺鍍之 方式在絕緣層110的表面形成一層共形的鎢黏著層1〇8，如 此可提升後續在接觸窗開口中形成鎢插塞之附著力。接著 在接觸窗開口中填入導電材料形成接觸窗插塞ιι2，依本最 佳實施例而言，是使用鎢當作此導電材料。 接著巧參知、第一 B圖，在鎢黏著層1〇8與鎢插塞112 上，依序沈積一層導體層U4和一層擴散擋層ιι6，依本最 佳實施例而言，導體層U4之材質為氮化鈦（ΤιΝ)。擴散 擋層116之材質為氛化碎（^Ν〇。其中此導體層u4，主 要是於最終之完成結構中，提供鐵電電容下層極板與鎢插 塞112電性連接之用。而擴散擋層116之主要目的是作為 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公楚) ..... (請先閱讀背面之注意事項再填寫本頁) 訂· 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 519720 A 7 ΒΊ_ 五、發明説明（) 高溫氧之阻擋層，亦即在進行高溫製程時，用來保護鎢插 塞112，防止高溫氧擴散進入而與鎢插塞反應，形成一層鎢 氧化層。上述中導體層114其製造方法一般是利用濺鍍之 方式來形成，擴散擋層116的氮化矽層可使用傳統的化學 氣相沈積（chemical vapor deposition; CVD)方式、例如電漿 增強式化學氣相沈積（PECVD)或是低壓化學氣相沈積 (LPCVD)等、力口以开j成之。 仍然參閱第二B圖，在擴散擋層116上形成下電極 118。接著在下電極118上形成一層鐵電材料層12〇，鐵電 材料層120為具有鈣鈥礦（perovskite)結構之鐵電材料，比 如是鈦酸鉛錘（Pb/Zr/Ti〇3, PZT)、鈦酸鋇锶（BST)或是钽酸 鳃鉍（SBT)等。形成鐵電材料層120的方法比如是化學氣相 沉積法（CVD)或是有機化學氣相沉積法（M0CVD)等。在此製 程過程中’為了讓鐵電材料層Uo有一良好結晶程度，通 常溫度均大於500°C，常常會伴隨產生高溫氧擴散，而導致 鎢插塞112表面氧化的問題，但是因為於本發明之結構中， 於導體層II4上會另外形成一層擴散擋層116，用來保護鎢 插塞112 ’防止高溫氧擴散進入而與鎢插塞1丨2反應，形成 一層鎢氧化層。 請參閱第二C圖定義下電極118，塗佈一光阻層（圖 中未顯示出）於鐵電材料層120之上，接著圖案化此光阻 層’使其具有所需之下電極118圖案，然後以此圖案化光 阻層為罩幕，蝕刻暴露之部分鐵電材料層120，下電極118 和擴散擒層116。最後再將光阻層去除而完成下電極118的 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) ——-------------—I-------- (請先閲讀背面之注意事項再填寫本頁) 519720 A7Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 519720 V. Description of the invention () Field of the invention: The present invention relates to a semiconductor element and manufacturing technology, especially to the manufacture of a ferroelectric capacitor (Ferroelectric Capacit〇r) related. Background of the invention: In recent years, non-volatile ferroelectric memory (FRAM) has generally attracted the attention of all walks of life, and has continuously developed its manufacturing technology. In non-volatile ferroelectric memory, the capacitor of each ferroelectric memory cell has a ferroelectric film as the dielectric layer of the capacitor, which is used to store data. With the continuous progress of the semiconductor industry, ferroelectric memory elements have been widely used in integrated circuits. Generally, a random access ferroelectric memory has many memory cells, and its memory cell is usually composed of a ferroelectric capacitor and a transistor to store a bit. ). The drain or source of the transistor is connected to one end of the ferroelectric capacitor, and the other end of the ferroelectric capacitor is connected to the reference potential. The other end of the transistor and the gate are respectively connected to the bit line. And word line connections. Therefore, when manufacturing the memory cell of the random access ferroelectric memory, it often includes the process of the transistor and the ferroelectric capacitor, and through the electrical contact between the capacitor and the source or drain region of the transistor, the The digital information is stored in the capacitor, and then the digital data of the ferroelectric capacitor is accessed by the transistor, bit line, character, and line array. However, with the development of ultra large integrated circuits (ULSI), in order to find a balance between capacitors with competitive value and occupying the smallest space, the process technology has been modified. 2 This paper size applies the Chinese National Standard (CNS) A4 specification ( 210X297 mm) ·----------------........., but .........%. (Please read the note on the back first Please fill in this page again for details) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519720 V. Description of Invention () Good will not work). One way is to structure the capacitor in such a way that the electrode plate and the #storage node are generally called stacked capacitors (stacked. Volume _ ㈣ 形 形 电 电 电 电 二 二 2 type: ferroelectric memory cells The capacitor is as shown in the figure. Taking the structure of the ferroelectric capacitor (1T / 1C) as an example, it is first formed on the semiconductor substrate 10 "to form a method of… and ... The dielectric layer 2 forms one of the contact window tungsten plugs and one of the two source / and electrode regions 16, and finally a capacitor is placed on the contact window tungsten plugs. The traditional ferroelectric capacitor is from the bottom to the "plane" ... ': The thin film 26 of ferroelectric material, and the thin film of ferroelectricity: = ^ μ η μ "Material f film 26 _ is generally pw3 Although this stacked ferroelectric capacitor is the most area-saving, :: Iron: Material. Film At 26:00, a high-temperature process is required. The temperature of this process is 500 ° C, because if the temperature of this process is not high enough, the crystal quality of the ferroelectric material film 26 will be affected. However, under this fork ^ ^ Cai Lu thin film 26 contains Ti〇3, when performing this high temperature process, it will encounter high temperature rhenium diffusion leading to tungsten insertion 22 The problem of oxidation. Traditionally, the solution to this problem is to use polycrystalline broken plugs instead of chirped plugs to reduce the possibility of oxidation. Because the polycrystalline relay has a higher resistance value, the resulting ferroelectric memory behaves better. It would be better to use a Yan plug. Another method is to reduce the process temperature to avoid the occurrence of oxygen diffusion in the south temperature. However, this method will deteriorate the capacity-building characteristics. Therefore, an invention of an improvement method is highly needed to solve the above problem. This paper size applies to China National Standard (CNS) A4 specification (2l0X297 public love) ----... wide ......... order .........% (Please read the back first Please note this page, please fill in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519720 A7 B7 V. Description of the invention () Questions and objectives of the invention: In view of the above background of the invention, planar stacked capacitor structures are often formed in the process of formation It will accompany the diffusion of high-temperature oxygen, which leads to the oxidation of crane plugs. Although polycrystalline silicon plugs can be used instead of tungsten plugs to reduce the possibility of oxidation, the high electrical resistance of polycrystalline silicon plugs will cause the overall electrical performance to change. Poor. Therefore, the present invention provides Provided is a ferroelectric capacitor structure and a manufacturing method thereof to reduce the problem of oxidation of tungsten plugs caused by high-temperature oxygen diffusion during manufacturing. The present invention provides a structure of a ferroelectric capacitor, which is structured on a semiconductor substrate. The ferroelectric The structure of the capacitor includes a gap between conductors. The gap between conductors is structured on a conductor layer, and is electrically connected to the source / drain region of the transistor through the conductor layer and the contact window tungsten plug. The transistor controls the electrical operation of the capacitor. At the same time, a diffusion barrier layer is sandwiched between the conductor layer and the lower electrode of the capacitor. During the high temperature process, it can protect the tungsten plug and prevent the south temperature oxygen from diffusing into and reacting with the tungsten plug. A tungsten oxide layer is formed. The present invention also provides a method for manufacturing a ferroelectric capacitor with a wall gap between conductors. First, a first conductor layer, a barrier layer, a lower electrode layer, and a ferroelectric material layer are sequentially formed on a semiconductor substrate. The ferroelectric material layer is, for example, lead zirconate titanate (PZT) as a dielectric layer of a capacitor. Then, a patterned photoresist layer is formed on the ferroelectric material layer, and the layer is used as a mask etching barrier layer, a lower electrode layer, and a ferroelectric material layer. Then deposit a second conductor layer, and dry etch into the paper at the same time. Applicable to China National Standard (CNS) A4 specification (2Ϊ0 × 297 mm) -------- —h — -11 ^ ....... ........... (Please read the precautions on the back before filling this page) 519720 A7 B7 V. Description of the invention () Non-isotropic row etching of this layer forms a gap layer between conductors . Next, an insulating layer is deposited on the surface, and another patterned photoresist layer is used as a mask to engrav the insulating layer to expose the surface of the ferroelectric material layer, and then a third conductive layer is deposited as a ferroelectric capacitor. On the electrode. Brief description of the drawings: The following detailed description of the preferred embodiments of the present invention will provide a better understanding of the objects, viewpoints and advantages of the present invention. At the same time, it will be described with reference to the following drawings of the present invention: The first picture is a conventional ferroelectric capacitor with a stacked structure; the second A to the second E are schematic cross-sectional views of the manufacturing process of the ferroelectric capacitor with a wall gap between conductors according to the present invention. Figure 2F is a schematic diagram of another structure of the ferroelectric capacitor with a wall gap between conductors according to the present invention; and Figure 3 is a diagram showing the use of the structure of the present invention in a resistive memory. Comparative description of drawing numbers: (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 10 Semiconductor substrate 12 Gate 14 Gate dielectric layer 16 Source / drain region 20 Insulation layer 22 Contact window plug 24 Lower electrode 26 Ferroelectric layer 28 Upper electrode 30 Insulating layer The paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm) 519720 V. Description of the invention (100 104 108 112 116 120 124 128 Semiconductor Substrate 102 Gate Gate Dielectric Layer 106 Source / Drain Region Tungsten Adhesive Layer 110 Insulating Layer Contact Window Plug 114 Conductor Layer Diffusion Barrier Layer 118 Lower Electrode Ferroelectric Material Layer 122 Interlayer Conductor Dielectric Layer 126 Conductor Layer Opening 130 chalcogenide invention detailed description: (Please read the notes on the back before filling in this page) The Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is printed without restricting the spirit and application scope of the present invention. For example, to introduce the implementation of the present invention; after a person skilled in the art understands the spirit of the present invention, when the ferroelectric capacitor can be applied, its structure can be used in various irons. In the electrical memory unit, the method and structure can solve the problem that the traditionally produced ferroelectric capacitors diffuse to warm oxygen and cause the plug plug oxidation. At the same time, it should be clear that the method and structure can be used without polycrystalline silicon. The plug instead of the tungsten plug reduces the possibility of oxidation, so it will not affect the performance of the entire ferroelectric memory. The application of the present invention is not limited to the embodiments described below. The second A to the second E are conductors of the present invention. A schematic cross-sectional view of the manufacturing process of the wall gap capacity. Please refer to the second A diagram, and first provide a bulk substrate 100, such as a P-type crushed substrate having a < 100 > structure. Under the substrate 100, the method and method of the invention are used to produce the plug, and the electricity is 0. The ferroelectricity is half of the active order on the substrate. 519720 A7 B7 V. Description of the invention () The transistor is made on the area It usually includes a gate electrode 102, a gate oxide layer 104 between the gate electrode 102 and the substrate 100, and a source / drain region 106 located on both sides of the gate electrode 102. On the transistor Covered with a layer of insulation 11 〇, such as silicon dioxide, spin-on glass (S0G), low dielectric (Lww) material or a combination thereof. In the insulating layer 110, a contact window plug 112 is coupled to the source / drain. The material used in the region 106 ′ contact window plug 112 is, for example, tungsten (w), poly-Si, or doped poly-Si. In this preferred embodiment, And 3 is tungsten. Its manufacturing method generally uses lithography and etching technology. First, a patterned photoresist layer (not shown) is formed on the insulating layer 110, and then the patterned photoresist layer is used as a mask to etch insulation. Layer 10 to remove the patterned photoresist layer after the contact window openings are formed in the insulating layer 110. Before filling the contact window opening with a conductive material, it is preferred to form a tungsten adhesive layer 108 on the bottom and side walls of the contact window opening. Its material is, for example, titanium ΓΠ), titanium nitride (TlN), etc., and its manufacturing method is generally A conformal tungsten adhesive layer 108 is formed on the surface of the insulating layer 110 by sputtering, which can improve the adhesion of the tungsten plug formed in the opening of the contact window. Then, a conductive material is filled in the opening of the contact window to form a contact window plug 2. According to the preferred embodiment, tungsten is used as the conductive material. Then referring to FIG. 1B, on the tungsten adhesive layer 108 and the tungsten plug 112, a conductor layer U4 and a diffusion barrier layer ι6 are sequentially deposited. According to this preferred embodiment, the conductor layer U4 The material is titanium nitride (TiN). The material of the diffusion barrier layer 116 is sintered (^ NO). The conductor layer u4 is mainly used in the final completed structure to provide the electrical connection between the lower electrode of the ferroelectric capacitor and the tungsten plug 112. Diffusion The main purpose of the barrier 116 is to apply the Chinese National Standard (CNS) A4 specification (210x297) as the paper size ... (Please read the precautions on the back before filling this page) Printed by the Consumer Consumption Cooperative, printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Consumption Cooperative, 519720 A 7 ΒΊ_ V. Description of the invention () High temperature oxygen barrier layer, which is used to protect the tungsten plug 112 and prevent high temperature oxygen during high temperature process Diffusion enters and reacts with tungsten plugs to form a tungsten oxide layer. The manufacturing method of the above-mentioned middle conductor layer 114 is generally formed by sputtering, and the silicon nitride layer of the diffusion barrier layer 116 can be traditional chemical vapor deposition. (Chemical vapor deposition; CVD) methods, such as plasma enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), etc., to open up. Still referring to the second figure B, the diffusion A lower electrode 118 is formed on the barrier layer 116. Next, a ferroelectric material layer 120 is formed on the lower electrode 118. The ferroelectric material layer 120 is a ferroelectric material having a calcium perovskite structure, such as a lead titanate hammer (Pb / Zr / Ti〇3, PZT), barium strontium titanate (BST) or gallium bismuth tantalate (SBT), etc. The method of forming the ferroelectric material layer 120 is, for example, chemical vapor deposition (CVD) or organic chemistry Vapor deposition (M0CVD), etc. During this process, 'in order to allow the ferroelectric material layer Uo to have a good degree of crystallization, the temperature is usually greater than 500 ° C, and often accompanied by high-temperature oxygen diffusion, which results in the surface of the tungsten plug 112. The problem of oxidation, but because in the structure of the present invention, another layer of diffusion barrier 116 is formed on the conductor layer II4, which is used to protect the tungsten plug 112 ′ from the diffusion of high-temperature oxygen and react with the tungsten plug 1 丨 2, A tungsten oxide layer is formed. Please refer to the second figure C to define the lower electrode 118, apply a photoresist layer (not shown) on the ferroelectric material layer 120, and then pattern this photoresist layer to have The required lower electrode 118 pattern, and then pattern the light The resist layer is a mask, and the exposed part of the ferroelectric material layer 120, the lower electrode 118, and the diffusion layer 116 are etched. Finally, the photoresist layer is removed to complete the lower electrode 118. The paper size of this paper applies to China National Standard (CNS) A4 specifications (210x297mm) ---------------- I -------- (Please read the precautions on the back before filling this page) 519720 A7
五、發明説明（） 定義。 月多閱第一 D圖’接著在表面上全面沈積一層導體 層，用來製作導體間壁隙122,其導體材料可為多晶石夕、石夕 化鎢或金屬鎢等，依本發明之最佳實施例而言，係採用金 屬鎢當作此導體材料，*製造方法-般是利用化學氣相沈 '、去（CVD )之方式來形成。接著利用乾蚀刻法，以非等 向蚀刻方式進行間壁隙触刻，同時於此步驟中亦可同時 將導體層114蝕去。依本發明之最佳實施例而言，其製作 導體間壁隙122和導體層U4的乾蝕刻製程，可使用具有 非等向性的乾蝕刻製程、例如反應性離子蚀刻丨㈣ etch; RIE)等。其韻刻完成後之導體間壁隙122圖形如第二 D圖所示’其中，下電極118與導體間壁隙122耦接，並且 透過導體層II4和接觸盲鎢插塞112來與電晶體之源極以及 極區106電性連接，由電晶體控制電容之電性操作。依據 本發明之方法’其下電極板是透過此導體間壁隙122 來與電晶體之源極/汲極區106電性連接，因此本發明之結 構具有自對準（Self-Align )優點，亦即本發明之下電極板 118未必得位於接觸窗鎢插塞U2之正上方，其即使偏移一 段距離，因其係透過導體層114來做電性連接，只要此導 體層114能與接觸窗鎢插塞112耦接，即不會影響其電性 表現。另一方面，於導體層114上具一層擴散擔層ιι6，可 防止高溫氧擴散進入而與鎢插塞112反應，形成一層鎢氧 化層。 請參閱第二E圖，當形成完導體間壁隙122後，於表 9 本紙張尺度適用中國國家標準(CNS)A4規格(21〇X297公楚) ——...... (請先閱讀背面之注意事項再填寫本頁) 訂· 經濟部智慧財產局員工消費合作社印製 經濟部智慈財產局員工消費合作社印製 519720 A7 B7_ 五、發明説明（） 面上全面性沈積一層介電層124，用來隔離後續之所製作之 上電極與導體間壁隙122。上述中介電層12可為氮化矽層或 氧化矽層，使用傳統的化學氣相沈積（chemical vap〇r deposition; CVD)方式、例如電漿增強式化學氣相沈積（pECVD) 或是低壓化學氣相沈積（LPCVD)等加以形成之。接於介電層 124上形成一層圖案化光阻層（未顯示），此圖案化光阻層中 具有形成開口 128所需之圖案，接著以此圖案化光阻層為罩 幕，蝕刻暴露，之部分介電層124，直到暴露出底下的鐵電材 料層120，形成開口 128。最後，形成上電極126於介電層 124之表面’以作為記憶體電容器之上方電極板。此導電層 126可採用摻雜之多晶矽的材質、也可以用金屬層或矽化金 屬層來代替。 參閱第二F圖，為本發明之另一種結構示意圖，此結 構與上述所述結構最大之不同在於，當進行鐵電材料層 120，下電極118和擴散擋層116之蝕刻時，同時進行導體層 114之蝕刻，亦即於本結構中，導體間壁隙層122非建構在 導體層114之上，其係建構在鎢黏著層1〇8之上。但依本結 構而τ ,由於導體間壁隙i22仍與導體層114具接觸，因此 仍可透過導體層114來與接觸插塞U2做電性連接。 因此 纟*上所述，很明顯的本發明之導體間壁隙12 2 結構，可具有很多之變形，也就是說，導體間壁隙層丄22並 非足得建構在導體層II4之上，只要此導體間壁隙層122 可與導fs：層114做電性連接即可。因此，若進行鐵電材料層 12 0，下黾極118和擴散擒層丄i 6之|虫刻時，同時進行導體層 10 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ——:ΛΨ.........訂.........S (請先閲讀背面之注意事項再填寫本頁) 519720 A7 ________ B7 五、發明說明（） 工工4 ’與鎢黏住層108之蝕刻，讓導體間壁隙層122直接建構 在半導體基底100之表面上，仍不會影響本發明之電性表 現。 综上所述，本發明相較於先前技術，具有諸多優點。 首先本發明所提供之鐵電電容結構可以解決製作過程中，因 高溫氧擴散，而導致鎢插塞氧化的問題。且另一方面本發明 所特殊具有之導體間壁隙122結構，可使得本發明具自對準 功效，亦即透過導體層U4來做電性連接，只要此導體層114 能與接觸''窗鎢插塞112耦接，即不會影響其電性表現。 本發明之結構亦可應用在另一種應用中，如一種電阻 性記憶體當中，其係使用一種硫族化合物當作記憶材料，利 用不同之相變化，此種材料電阻值大小會有很大之差異，來 記憶不同之資料，其結構請參照第三圖。硫族化合物130放 置於導體間壁隙122與導電層126間，而介電層124，亦用 已隔開導體間壁隙122與導電層126，利用硫族化合物130 之不同相所呈現出之不同電阻值來記憶資料。 如熟悉此技術之人員所暸解的’以上所述僅為本發 明之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 :::.....•:餮.........訂.........$ (請先閲讀背面之注意事項再填寫本頁} 經濟部智慈財產局員工消費合作社印製 11 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐)5. Description of the invention () Definition. Read the first D picture in the next month, and then deposit a conductor layer on the surface to make the conductor gap 122. The conductor material can be polycrystalline stone, tungsten tungsten or metal tungsten, etc. According to the invention, In the preferred embodiment, metal tungsten is used as the conductor material. The manufacturing method is generally formed by chemical vapor deposition (CVD). Next, the interlayer gap etching is performed by a dry etching method using an anisotropic etching method, and the conductor layer 114 can be etched away at the same time in this step. According to a preferred embodiment of the present invention, the dry etching process for fabricating the inter-conductor wall gap 122 and the conductor layer U4 can use an anisotropic dry etching process, such as reactive ion etching (㈣etch; RIE) Wait. The graph of the inter-conductor wall gap 122 after the rhyme is completed is shown in the second D diagram. 'The lower electrode 118 is coupled to the inter-conductor wall gap 122 and communicates with the transistor through the conductor layer II4 and the contact blind tungsten plug 112. The source and the electrode region 106 are electrically connected, and the electrical operation of the capacitor is controlled by a transistor. According to the method of the present invention, the lower electrode plate is electrically connected to the source / drain region 106 of the transistor through the gap 122 between the conductors. Therefore, the structure of the present invention has the advantage of self-alignment. That is, the electrode plate 118 under the present invention may not necessarily be located directly above the tungsten plug U2 of the contact window. Even if it is offset a certain distance, it is electrically connected through the conductor layer 114 as long as the conductor layer 114 can be in contact with The window tungsten plug 112 is coupled, that is, it does not affect its electrical performance. On the other hand, a diffusion support layer 6 is provided on the conductor layer 114 to prevent high-temperature oxygen from diffusing into and reacting with the tungsten plug 112 to form a tungsten oxide layer. Please refer to the second figure E. After forming the wall gap 122 between conductors, the paper size in Table 9 applies the Chinese National Standard (CNS) A4 specification (21 × 297). ...... (please first (Please read the notes on the back and fill in this page) Ordering · Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519720 A7 B7_ V. Description of the invention A layer 124 is used to isolate the gap 122 between the upper electrode and the conductor manufactured later. The above-mentioned dielectric layer 12 may be a silicon nitride layer or a silicon oxide layer, using a conventional chemical vapor deposition (CVD) method, such as plasma enhanced chemical vapor deposition (pECVD) or low-pressure chemical It is formed by vapor deposition (LPCVD) and the like. A patterned photoresist layer (not shown) is formed on the dielectric layer 124. The patterned photoresist layer has a pattern required to form the opening 128, and then the patterned photoresist layer is used as a mask to expose and expose. A portion of the dielectric layer 124 is formed until the underlying ferroelectric material layer 120 is exposed to form an opening 128. Finally, an upper electrode 126 is formed on the surface 'of the dielectric layer 124 as an upper electrode plate of the memory capacitor. The conductive layer 126 may be made of doped polycrystalline silicon, or may be replaced by a metal layer or a silicide metal layer. Refer to the second F diagram, which is another schematic diagram of the structure of the present invention. The biggest difference between this structure and the structure described above is that when the ferroelectric material layer 120, the lower electrode 118 and the diffusion barrier layer 116 are etched, the conductor is simultaneously performed The etching of the layer 114, that is, in the present structure, the inter-conductor gap layer 122 is not constructed on the conductor layer 114, and it is constructed on the tungsten adhesive layer 108. However, according to this structure, τ, because the gap i22 between the conductors is still in contact with the conductor layer 114, the conductor layer 114 can still be used to make an electrical connection with the contact plug U2. Therefore, as stated above, it is obvious that the inter-conductor wall gap 12 2 structure of the present invention can have many deformations, that is, the inter-conductor wall gap layer 丄 22 is not sufficient to be constructed on the conductor layer II4, as long as The inter-conductor gap layer 122 may be electrically connected to the conductive fs: layer 114. Therefore, if the ferroelectric material layer 12 0, the lower pole 118 and the diffusion trap layer 丄 i 6 are used, the conductor layer 10 is simultaneously performed when the worm is engraved. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). ——: ΛΨ ......... Order ......... S (Please read the notes on the back before filling this page) 519720 A7 ________ B7 V. Description of the invention () Worker 4 The etching of the tungsten adhesion layer 108 allows the inter-conductor gap layer 122 to be directly constructed on the surface of the semiconductor substrate 100 without affecting the electrical performance of the present invention. In summary, the present invention has many advantages over the prior art. Firstly, the ferroelectric capacitor structure provided by the present invention can solve the problem of oxidation of tungsten plugs due to the diffusion of high temperature oxygen during the manufacturing process. On the other hand, the inter-conductor wall gap 122 structure of the present invention can make the present invention self-aligning, that is, the electrical connection is made through the conductor layer U4, as long as the conductor layer 114 can contact the window. The tungsten plug 112 is coupled, that is, it does not affect its electrical performance. The structure of the present invention can also be used in another application, such as a resistive memory, which uses a chalcogen compound as a memory material and uses different phase changes. The resistance value of this material will be very large. Difference, to memorize different data, please refer to the third figure for its structure. The chalcogen compound 130 is placed between the gap 122 between the conductors and the conductive layer 126, and the dielectric layer 124 is also separated by the gap 122 between the conductors and the conductive layer 126. Different resistance values to memorize data. As understood by those familiar with this technology, 'The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application for the present invention; all other things that are completed without departing from the spirit disclosed by the present invention, etc. Effective changes or modifications should be included in the scope of patent application described below. ::: ..... •: 餮 ......... Order ......... $ (Please read the notes on the back before filling out this page} Intellectual Property Office, Ministry of Economic Affairs Printed by Employee Consumer Cooperatives 11 This paper size applies to China National Standard (CNS) A4 (210X 297 mm)