JP3319928B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a ferroelectric memory device, and more particularly to a method of manufacturing a nonvolatile semiconductor memory device made of a ferroelectric material.

[0002]

2. Description of the Related Art A first conventional non-volatile memory device using a ferroelectric material comprises at least one switching transistor and at least one ferroelectric capacitor, and the transistor and the capacitor are interconnected. Connected by layers. FIGS. 4 to 6 show a conventional first embodiment.
FIG. 9 is a structural sectional view of a nonvolatile semiconductor memory element using the third to third ferroelectrics. 4 to 6, 21 is a silicon substrate, 22 is a gate electrode, 23 is a diffusion layer, 24,
32 denotes an interlayer insulating film, 25 denotes a polysilicon plug, 26 denotes a lower electrode, 27 denotes a ferroelectric film, 28 denotes an upper electrode, 29 denotes a bit line, 30 denotes a drive line, and 31 denotes a barrier layer.

The conventional nonvolatile memory element using a ferroelectric shown in FIG. 4 is manufactured by the following steps.

[0004] First, after a switching transistor is formed in an active region surrounded by element isolation, a lower electrode corresponding to a drive line is formed on the element isolation region.
A ferroelectric film is formed. After that, the ferroelectric and the upper electrode are processed to form a capacitor. Next, one source /
A bit line is connected to the drain region, and another source / drain region is electrically connected to a plate electrode of the ferroelectric capacitor by a wiring.

[0005] A ferroelectric capacitor has the characteristics shown in FIG. Since the ferroelectric film has spontaneous polarization even when the applied electric field is removed, information (1 or 0) is stored according to the polarization direction. When applied to a memory element, the positive and negative threshold voltages for polarization inversion are equal, and the difference between the amount of inversion charge and the amount of non-inversion charge is detected by a sensing amplifier of the memory element.
^{About 2} are required.

[0006] Ferroelectric materials include lead zirconate titanate (PbZr _x) as a material satisfying the above characteristics.
Ti _x-1 O ₃ , hereinafter referred to as “PZT”. ) Etc. are used. In addition, as the electrode material, Pt having excellent lattice matching with the PZT film and excellent oxidation resistance, such as Pt or oxide, and RuO ₂ having a characteristic of conductivity are used.

[0007]

However, as shown in FIG. 4, in the first conventional memory element structure, a ferroelectric capacitor is formed on an element isolation region. Therefore, the element isolation region needs to be designed with a sufficient margin for the capacitor, and it is difficult to reduce the cell size.

On the other hand, by employing a stack structure in which a ferroelectric capacitor as shown in FIG. 5 is formed on a switching transistor, a memory element area can be reduced and high integration can be realized. In order to realize such a stack structure, the wiring connecting the switching transistor and the ferroelectric capacitor needs to have a plug structure. 2. Description of the Related Art Conventionally, tungsten and polysilicon are buried in fine contacts of a semiconductor memory element for which high integration is intended.

Further, since a platinum or oxide conductor having excellent oxidation resistance is used as the electrode material of the ferroelectric capacitor, the material used for the plug is stable with respect to the platinum or oxide conductor. Good contact characteristics must be obtained.

However, the polysilicon plug easily reacts with platinum by heat treatment in the ferroelectric capacitor forming step to form platinum silicide. For this reason, volume expansion occurs in the electrode region, resulting in a contact failure. Also,
When a conductive oxide is used, silicon is oxidized at the interface between the conductive oxide and polysilicon, and it is difficult to obtain a good ohmic contact.

On the other hand, since the tungsten plug locally has a large stress, poor adhesion occurs in the contact region with the drain region due to the stress accompanying the heat treatment process at 600 to 700 ° C. for crystallization of the ferroelectric film. Might be. Therefore, when platinum is used for the lower electrode and polysilicon is used for the plug in the ferroelectric memory element having the stack structure, it is necessary to insert a barrier layer at the interface between the lower electrode and polysilicon. TiN is known as a film having such a barrier property. For example, polysilicon for contact plug, platinum for lower electrode, TiN film for barrier layer, PZ for ferroelectric
When a T film is used, the crystallization temperature of the PZT film (600 to 7)
(00 ° C.), it is necessary to use T
The thickness of the iN film needs to be 2000 mm or more. Further, in order to obtain good ferroelectricity, the thickness of the PZT film must be 2000
Since the thickness of the lower electrode is required to be 1000 mm or more,
Since a step of 5000 ° or more occurs, it becomes difficult to perform fine processing and high integration.

Further, in order to form the upper electrode as a drive line after processing the ferroelectric film and the lower electrode, an interlayer insulating film may be formed before forming the drive line. The step after the formation of the drive line is ultimately 7500 to 10000 by the structure shown in FIG.
Becomes Å.

In order to reduce the step, instead of inserting a barrier layer, a material having a barrier property to the lower electrode, for example, TiN, is used for the plug as shown in Japanese Patent Application Laid-Open No. 5-299601.

However, when the lower electrode, the ferroelectric film, and the upper electrode are simultaneously etched using the same mask as in Japanese Patent Application Laid-Open No. 5-299601, the upper electrode cannot be used as a drive line. It is necessary to form a drive line connected to the upper electrode. Also,
A reaction product of Pt generated when Pt and the ferroelectric film are simultaneously etched adheres to the side wall of the ferroelectric film, and the upper electrode and the lower electrode may be electrically connected.

An object of the present invention is to provide a method of manufacturing a non-volatile semiconductor memory device having a stack structure which can be planarized, in which an upper electrode is processed separately from a lower electrode and the upper electrode is formed as a drive line. Is what you do.

[0016]

A method of manufacturing a semiconductor memory device according to the present invention is directed to a method of manufacturing a semiconductor memory device including a switching transistor and a capacitor having a ferroelectric film, wherein the switching transistor is formed on a semiconductor substrate. Forming a first interlayer insulating film, forming a contact hole on the diffusion region of the switching transistor in the first interlayer insulating film, burying a diffusion barrier film in the contact hole, the diffusion barrier layer on the insulating film is etched back and forming a contact plug, after depositing the bottom electrode material is patterned into a predetermined shape, forming a lower portion electrode, the entire surface Forming a buffer layer having a predetermined thickness, flattening the surface and exposing the surface of the lower electrode; Depositing a body membrane material is patterned and a step of patterning to a predetermined shape covering at least the lower electrode over the entire surface, after the entire surface by depositing the top electrode material, the upper portion electrode Ru driveline Tomona into a predetermined shape And a process.

Further, according to a method of manufacturing a semiconductor memory device of the present invention, in the method of manufacturing a semiconductor memory device including a switching transistor and a capacitor having a ferroelectric film, the method comprises the steps of: Forming a first interlayer insulating film and forming a contact hole on the diffusion region of the switching transistor in the first interlayer insulating film; burying a diffusion barrier film in the contact hole; by etching back the diffusion barrier film, forming a contact plug, after depositing the lower portion electrode material is patterned into a predetermined shape, and forming the lower electrode, the predetermined entire surface thickness after forming the the buffer layer, the surface flat, thereby exposing the lower electrode surface, the ferroelectric film及beauty After the part electrode material is deposited and patterned into a predetermined shape to cover at least the lower electrode,
Simultaneously forming the ferroelectric film and the upper electrode also serving as a drive line.

Further, in the method of manufacturing a semiconductor memory device according to the present invention, after the diffusion barrier film is buried in the contact hole, the diffusion barrier film on the first interlayer insulating film is removed by etch back. 3. The method according to claim 1, further comprising the step of forming said contact plug.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments of the present invention.

FIGS. 1 and 2 are views showing a manufacturing process of a semiconductor memory device according to the first embodiment of the present invention. FIG. 3 is a diagram showing a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention. FIG. 1 to 3, 1 is a silicon substrate,
2 is a gate electrode, 3 is a diffusion layer, 4 is a first interlayer insulating film, 5
Is a Ti film, 6a is a TiN layer, 6b is a TiN plug, 7 is a lower electrode, 8 is a buffer layer, 9 is a ferroelectric film, 10 is a second interlayer insulating film, 11 is an upper electrode, and 12 is a third interlayer insulating film. Reference numeral 13 denotes a bit line.

Next, a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention will be described with reference to FIG.

First, a silicon substrate 1 is formed by a conventional technique.
A switching transistor having a gate electrode 2 and a diffusion layer 3 thereon is formed. Thereafter, a first interlayer insulating film 4 is deposited, and a resist (not shown) is formed on the first interlayer insulating film 4.
Is deposited, patterned by a photolithography process, and a contact hole is formed by an RIE method or the like (FIG. 1A).

After removing the resist (not shown), a Ti film 5 is formed by DC magnetron sputtering to obtain a good ohmic contact with the diffusion layer 3. In order to obtain good ohmic characteristics, the Ti film 5
Is preferably 500 to 1000 °. Titanium tetrachloride is used as a Ti raw material, and methylhydrazine or ammonia is used as a reducing gas. The Ti raw material is not limited to the above raw materials, and an organic metal raw material such as tetrakisdimethylaminotitanium may be used.

Next, a TiN layer 6a is deposited on the entire surface including the inside of the contact hole as a material having a barrier property to the lower electrode by the CVD method. TiN layer 6a
Is formed by heating the substrate to a temperature of 400 to 600 ° C., introducing the raw material onto the substrate, and reducing the pressure to 1 to 5 Torr. When the diameter of the contact hole is 0.5 μm, T
7000-10000 for complete embedding with iN layer 6a
望 ま し い It is desirable to deposit (FIG. 1B). In the sputtering method, it is difficult to completely fill the contact hole because the step coverage is poor,
Method.

Next, the TiN film 6a on the first interlayer insulating film 4 is etched back with Cl ₂ , SF ₆ or CF ₄ . After the etch-back, the TiN layer 6a remains as a TiN plug 6b only in the contact hole (FIG. 1C).
Further, by using a TiN plug 6b as a contact plug and not providing a barrier layer between the first interlayer insulating film 4 and the lower electrode 7, a step difference due to a conventional barrier layer can be reduced.

Next, a platinum (Pt) film to be the lower electrode 7 is formed. Pt is about 1000Å by sputtering method.
It is desirable to form. The lower electrode 7 is not limited to Pt, and may be an oxide conductor such as RuO ₂ or ReO ₃ . The thickness of these electrodes is also desirably about 1000 °. After forming the platinum film, the lithography process
A resist (not shown) is patterned, and a lower electrode 7 is formed by RIE (FIG. 1D).

Next, a titanium oxide film or a zirconium oxide film serving as a buffer layer 8 for preventing a reaction between the ferroelectric film 9 and the first interlayer insulating film 4 is formed on the lower electrode 7 by CVD.
It is formed by a method. As the titanium raw material and the zirconium raw material, it is desirable to use these metal alkoxide raw materials. For example, Ti (OC ₂ H ₅ ), T
Z such as i (i-OC ₃ H ₇ ) ₄ , Ti (t-OC ₄ H ₉ ) ₄
As r raw _{material, Zr (i-OC 3 H} 7) 4, Zr (i-O
It is desirable to use C ₄ H ₉ ) ₄ , Zr (C ₁₁ H ₁₉ O ₂ ) or the like.

Further, titanium oxide (TiO.sub.2) formed by CVD is used.
₂ ) The formation of the film and the zirconium oxide (ZrO ₂ ) film
The above raw material is bubbled with an inert gas, and the silicon substrate 1 under reduced pressure of 1 to 5 Torr together with the vaporized vapor.
Introduce on top. It is desirable that the silicon substrate 1 is heated to 400 to 500 ° C. and O ₂ or O ₃ is used as a reaction gas. It is desirable that the TiO ₂ film or the ZrO ₂ film is deposited 1.5 to 2 times the thickness of the lower electrode 7.

Thereafter, a titanium oxide film or a zirconium oxide film serving as the buffer layer 8 is formed by CMP (Chemical).
The surface of the lower electrode 7 is polished until the surface is exposed using a Mechanical Polishing (chemical mechanical polishing) method,
The surface is flattened (FIG. 1E). The buffer layer 8
It is desirable that a stable and favorable insulating property between the ferroelectric film 9 and the underlying first interlayer insulating film 4 be obtained during the heat treatment of the ferroelectric film.

Next, a ferroelectric film 9 is formed on the entire surface of the silicon substrate 1 by a sol-gel method or the like, and is crystallized by lamp heating or an electric furnace. The crystallization temperature varies greatly depending on the ferroelectric material, but in the case of a PZT film or a PLZT film,
A temperature of 600 to 700 ° C. is desirable (FIG. 1F). In the present invention, the method for forming the ferroelectric film 9 is not limited to the sol-gel method, and a CVD method or a sputtering method is also applicable.
When the CVD method or the high-temperature sputtering method is used, the above-described crystallization step of the ferroelectric film 9 can be omitted.

After patterning the ferroelectric film 9, the second
After an interlayer insulating film 10 is formed and the second interlayer insulating film 10 on the ferroelectric film 9 is partially removed, an upper electrode 11 serving as a drive line is formed to a thickness of about 1000 ° (FIG. 1).
(G)). The step of forming the second interlayer insulating film 10 may not be performed. However, when the side surface of the ferroelectric film 9 is not used as a capacitor due to poor film quality or the like, the second interlayer insulating film 10 may be formed. Is desirable. Next, a silicon nitride film, a PSG film, a BPSG film, or the like is formed as the third interlayer insulating film 12, a contact hole is formed on the source side of the switching transistor, and the bit line 1 is formed by metal wiring.
3 is formed (FIG. 1 (h)).

Next, a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIG.

First, the buffer layer 8 is polished until the surface of the lower electrode 7 is exposed using the same steps (FIGS. 1A to 1E) as in the first embodiment, and the surface is flattened. After the formation, a ferroelectric film 9 is formed on the entire surface of the silicon substrate 1 by a sol-gel method or the like, and crystallized by lamp heating or an electric furnace. The crystallization temperature varies greatly depending on the ferroelectric material, but the PZT film or the PLZT film has a crystallization temperature of 600 to 700.
C is desirable. Further, a Pt film is formed on the ferroelectric film 9 as the upper electrode 11 at about 1000 ° (FIG. 2A).
Patterning is performed by a photolithography process. The upper electrode 11 is not limited to Pt, but may be an oxide conductor. The upper electrode 11 and the ferroelectric film 9 are simultaneously processed by dry etching (FIG. 2).
(B)).

Next, a silicon nitride film, a PSG film, a BPSG film or the like is formed as the third interlayer insulating film 12, a contact hole is formed on the source side of the switching transistor, and a bit line 13 is formed by metal wiring (FIG. 2
(C)).

[0035]

As described above in detail, since the present invention is used to make the surface of the buffer layer and the surface of the lower electrode coplanar, there is no step due to the lower electrode as in the prior art. Since the interlayer insulating film to be formed can be made thinner, the step on the surface can be reduced (the final step can be suppressed to about 3000 to 4000 ° by using the present invention), and the drive line can be easily formed.

In addition, since the lower electrode and the ferroelectric film are separately etched for patterning, when the lower electrode and the ferroelectric film are simultaneously etched, the reaction generation of Pt adhering to the side wall of the ferroelectric film occurs. The generation of objects can be suppressed.

Further, by providing titanium oxide or zirconium oxide as a buffer layer between the first interlayer insulating film and the ferroelectric film, the ferroelectric film is stable and excellent in heat treatment of the ferroelectric film. Insulation between the dielectric film and the underlying interlayer insulating film is obtained.

Further, after the lower electrode is formed, planarization is performed by using a buffer layer for preventing a reaction between the ferroelectric film and the interlayer insulating film, so that the lower electrode is made stronger than the lower electrode. Since the dielectric film is processed, when the upper electrode and the ferroelectric film are simultaneously etched, the reaction product of Pt generated when the upper electrode and the ferroelectric film are simultaneously etched is a ferroelectric film. Even if it adheres to the side wall, the reaction product does not cause conduction between the upper electrode and the lower electrode. Therefore, the upper electrode and the ferroelectric film can be processed in the same pattern, the number of steps can be reduced, and the formation of the drive line is facilitated.

Further, using the present invention described in claim 3, the first
By not providing a barrier layer between the interlayer insulating film and the lower electrode, a step difference due to the conventional barrier layer can be reduced.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a first conventional semiconductor memory device.

FIG. 5 is a configuration diagram of a second conventional semiconductor memory device.

FIG. 6 is a configuration diagram of a third conventional semiconductor memory device.

FIG. 7 is a diagram showing a hysteresis characteristic of accumulated charges with respect to an applied electric field.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 gate electrode 3 diffusion layer 4 first interlayer insulating film 5 Ti film 6a TiN layer 6b TiN plug 7 lower electrode 8 buffer layer 9 ferroelectric film 10 second interlayer insulating film 11 upper electrode 12 third interlayer insulating film 13 bit line

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/105 H01L 27/108 H01L 21/8242 H01L 21/822 H01L 27/04

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor memory device comprising a switching transistor and a capacitor having a ferroelectric film, comprising: forming a switching transistor on a semiconductor substrate, forming a first interlayer insulating film; Forming a contact hole on the diffusion region of the switching transistor in the interlayer insulating film, burying a diffusion barrier film in the contact hole, etching the diffusion barrier film into a predetermined shape, and forming a contact plug; After depositing the lower electrode material, patterning it into a predetermined shape and forming the lower electrode, after forming a buffer layer of a predetermined thickness on the entire surface, flattening the surface, Exposing, after depositing the ferroelectric film and the upper electrode material, a predetermined covering at least the lower electrode Patterned into a shape, and having a step of simultaneously forming the upper electrode also becomes the ferroelectric film and driveline, the method of manufacturing a semiconductor memory device. 2. The method according to claim 2, further comprising, after embedding the diffusion barrier film in the contact hole, removing the diffusion barrier film on the first interlayer insulating film by etch back to form the contact plug. A method for manufacturing a semiconductor memory device according to claim 1 . 3. The method according to claim 1, wherein the buffer layer is a titanium oxide film or an acid.
And zirconium oxide.
A method for manufacturing a semiconductor memory device according to claim 2.