經濟部智慧財產局貝工消費合作社印製 4444 0 0 6 2 19 twf . doc/ 0 0 6 A7 B7 五、發明說明（/) 本發明是有關一種記憶體元件(Memory Device)的製造 方法，且特別是有關一種記憶體之電容器（Capacitor)下電 極的製造方法。 電容器是動態隨機存取記憶體（DRAM)的重要元件， 爲避免DRAM儲存之資料發生錯誤，並增加DRAM的操 作效率，通常會製造具有大面積的立體式電容器，例如常 見的柱狀電容器（Cylinder Capacitor)。 習知柱狀電容器之下電極的製造方法是先在基底上形 成第一絕緣層，再於第一絕緣層中形成與基底電性連接的 節點接觸窗。接下來於第一絕緣層上形成具有開口的第二 絕緣層，此開口暴露出節點接觸窗，然後在開口內壁與底 部形成導體層，作爲柱狀電容器下電極。由於習知柱狀電 容器下電極的製造方法中，形成節點接觸窗與柱狀電容器 下電極之模板（Template)，第二絕緣層中的開口）各需要一 道光罩製程，故共需要兩道光罩製程。因此，習知之方法 不但耗費時間，也容易造成對準（Alignment)上的問題。 本發明提出一種記憶體之電容器下電極的製造方法， 其所得之電容器下電極的表面積大於由習知技藝所得者， 且僅需要一道光罩製程。此方法適用於一基底，而此基底 上已形成有第一絕緣層，其步驟如下：首先於第一絕緣層 中形成一自行對準接觸窗(Self-aligned Contact; SAC)開口， 其暴露出基底上之一導電區域，再於第一絕緣層上與自行 對準接觸窗開口中形成共形之第一導體層，此時自行對準 接觸窗開口底部之第一導體層係作爲一接觸窗。接著以第 3 本紙張尺度適用中國國家標準（CNS)A4規格（210* 297公釐） ----I----.!^裝.丨丨丨 — — —|訂，|__---- -線〆 (請先閱讀背面之注意事項再填寫本頁) 4444 0 0 6219twf.doc/006 A7 B7 五、發明說明（1) (請先閱讀背面之注意事項再填寫本頁) 二絕緣層塡滿此自行對準接觸窗開口’再回蝕第一導體 層，以完全除去自行對準接觸窗開口之外的第一導體層’ 並繼續除去自行對準接觸窗開口內之第一導體層至一特定 深度。接下來於自行對準接觸窗開口內之第一絕緣層與第 二絕緣層的側壁形成第二導體層，此第二導體層即作爲一 電容器下電極。 如上所述，在本發明之記憶體之電容器下電極的製造 方法中，作爲電容器下電極主體的第二導體層不僅形成在 自行對準接觸窗開口內側壁，同時也形成在自行對準接觸 窗開口中央之第二絕緣層的側壁，所以此方法所得之電容 器下電極的表面積會大於由習知方法所得之柱狀電容器下 電極的表面積。另外，由於此方法中電容器下電極的模板 即是自行對準接觸窗開口的上半部，所以節點接觸窗與電 容器下電極之形成總共只需要一道「定義自行對準接觸窗 開口的光罩製程」。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 經濟部智慧財產局員工消費合作社印製 圖式之簡單說明： 第ΙΑ-ΙΕ(ΙΕ’）圖所繪示爲本發明之較佳實施例中，記 憶體之電容器下電極的製造方法。 圖式之標號說明： 100 :基底 110 :淺溝渠隔離（Shallow Trench Isolation ; STI) 4 本紙張尺度適用中國國家檁準（CNS)A4規格（2】0 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4444 Ο Ο 6219twf.d〇c/006 Α7 __Β7___ 五、發明說明（彡） 120 :閘介電層（Gate Dielectric Layer) 130 :字元線(Word Line) HO :帽蓋層（Cap Layer) 150 :間隙壁（Spacer) 155 :源極/汲極區（S/D Region) 160、190 ' 210 :絕緣層 170 :位元線接觸窗(Bit Line Contact) 180 :位元線（Bit Line) 192:自行對準接觸窗開口（Self-Aligned Contact; SAC) 200 :導體層 200a :節點接觸窗(Node Contact) 220、230 :電容器下電極 較佳實施例說明 請參照第1A圖，首先提供基底100，其上形成有淺溝 渠隔離層110。接著於基底100上形成閘介電層120、閘介 電層120上方之字元線130、字元線130上方之帽蓋層140， 以及位於字元線130與帽蓋層140側壁的間隙壁150，其 中帽蓋層140與間隙壁150之材質例如爲氮化矽（SiN)。接 下來在間隙壁150兩側之基底100中形成源極/汲極區155， 即製成一金氧半電晶體(MOS)。接著於基底100上形成絕 緣層160，再於絕緣層160中形成位元線接觸窗170，並在 絕緣層160上形成位元線180。接下來在基底100上覆蓋 絕緣層190，此絕緣層190與160所用材質的蝕刻速率遠 大於帽蓋層140與間隙壁150的蝕刻速率，以利於後續之 5 本紙張尺度適用中固國家標準（CNS)A4規格<21Q X 297公爱) ----I------W裝- - ----訂1—1!_線"V. {請先閱讀贺面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 4444 00 6219twf,doc/006 A7 B7 五、發明說明) 自行對準接觸窗製程。也就是說，當帽蓋層140與間隙壁 150之材質爲氮化矽時，絕緣層190與160之材質可以是 蝕刻速率遠大於氮化矽的氧化矽。 請參照第1B圖，接著於絕緣層190與160中形成自 行對準接觸窗開口 192，以將汲極/源極區155暴露出來。 然後於絕緣層190上與自行對準接觸窗開口 192中形成共 形之導體層200，其材質例如爲多晶矽，此時自行對準接 觸窗開口 192底部之導體層200即成爲節點接觸窗200a。 接著在導體層200上形成絕緣層210,其係將自行對準接 觸窗開口 192塡滿。 請參照第1C圖，接著將自行對準接觸窗開口 192外 的絕緣層210除去，其方法例如爲電漿蝕刻法(Plasma Etch) 或化學機械硏磨法(Chemical Mechanical Polishing ; CMP)。 請參照第ID圖，接下來回蝕導體層200，其方法例如 爲電漿蝕刻法，以完全除去自行對準接觸窗開口 192之外 的導體層200，並繼續除去自行對準接觸窗開口 192內之 導體層200至一特定深度爲止。 接下來的步驟可分爲兩種，其分別以第1E與1E’圖爲 輔作說明。 請參照第1E圖，接下來於基底100上形成共形之導 體層（圖中未顯示），其材質例如爲多晶矽（Polysilicon)。然 後除去位於絕緣層190與210頂端，以及節點接觸窗200a 表面的導體層，其方法例如爲電漿蝕刻法，而使保留之導 體層成爲電容器下電極220。 6 本紙張尺度適用卡國國家標準（CNS)A4規格（21〇x 297公釐） ------!_!.)裝------訂i丨---繞) (請先閱讀背面之注意事項再填寫本頁) 4444 00 6219twf.d〇c/006 A7 B7 五、發明說明（f) 另一種作法請參照第1E’圖，接下來於基底上形成數 量夠多，足以完全覆蓋基底100表面的半球形矽晶粒層（圖 中未顯示）。然後除去位於絕緣層190與210頂端，以及節 點接觸窗200a表面的半球形矽晶粒層，其方法例如爲電 漿蝕刻法，而使保留之半球形矽晶粒層成爲電容器下電極 230,其所具有之表面積更大於上述電容器下電極220的 表面積。 如上所述，請參照第1Ε與1Ε’圖，在本發明較佳實施 例之記憶體之電容器下電極的製造方法中，作爲電容器下 電極220(230)不僅形成在自行對準接觸窗開口 192之內側 壁，同時也形成在自行對準接觸窗開口 192中間絕緣層210 的側壁，所以此方法所得之電容器下電極220(230)的面積 大於由習知方法所得之柱狀電容器下電極的表面積。另 外，由於此方法中電容器下電極220(230)的模板係爲自行 對準接觸窗開口 192的上半部，所以節點接觸窗200a與電 容器下電極220(230)之形成總共只需要一道「定義自行對 準接觸窗開口 192的光罩製程」。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 7 本紙張尺度適用中因國家榡準（CNS>A4規格（2】0 X 297公釐〉 (請先閱讀背面之注意事項再填寫本頁) *----I I 訂--------I ) 經濟部智慧財產局員工消費合作社印製Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 4444 0 0 6 2 19 twf .doc / 0 0 6 A7 B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing a memory device, and In particular, it relates to a method for manufacturing a lower electrode of a capacitor of a memory. Capacitors are important components of dynamic random access memory (DRAM). In order to avoid errors in the data stored in DRAM and increase the operating efficiency of DRAM, three-dimensional capacitors with large areas are usually manufactured, such as common cylindrical capacitors (Cylinder Capacitor). A conventional method for manufacturing an electrode under a columnar capacitor is to first form a first insulating layer on a substrate, and then form a node contact window electrically connected to the substrate in the first insulating layer. Next, a second insulating layer having an opening is formed on the first insulating layer. This opening exposes the node contact window, and then a conductor layer is formed on the inner wall and the bottom of the opening as the lower electrode of the columnar capacitor. Since in the conventional manufacturing method of the lower electrode of the columnar capacitor, a mask process is required for forming a node contact window and a template of the lower electrode of the column capacitor (the opening in the second insulating layer), so a total of two mask processes are required. Therefore, the conventional method is not only time consuming, but also easily causes problems in alignment. The invention proposes a method for manufacturing a capacitor lower electrode of a memory. The surface area of the capacitor lower electrode obtained is larger than that obtained by conventional techniques, and only a photomask process is required. This method is suitable for a substrate, and a first insulating layer has been formed on the substrate. The steps are as follows: firstly, a self-aligned contact (SAC) opening is formed in the first insulating layer, and it is exposed. A conductive area on the substrate forms a conformal first conductor layer on the first insulating layer with the self-aligned contact window opening. At this time, the first conductive layer on the bottom of the self-aligned contact window opening serves as a contact window . Then the third paper size applies the Chinese National Standard (CNS) A4 specification (210 * 297 mm) ---- I ----.! ^ 装. 丨 丨 丨 — — — | order, | __-- --- Cable (please read the notes on the back before filling this page) 4444 0 0 6219twf.doc / 006 A7 B7 V. Description of the invention (1) (Please read the notes on the back before filling this page) Second insulation The layer is filled with this self-aligning contact window opening 'and then the first conductor layer is etched back to completely remove the first conductor layer outside the self-aligning contact window opening' and continue to remove the first conductor in the self-aligning contact window opening. Layer to a specific depth. Next, a second conductive layer is formed on the side walls of the first insulating layer and the second insulating layer aligned in the opening of the contact window, and this second conductive layer serves as a capacitor lower electrode. As described above, in the method for manufacturing the capacitor lower electrode of the memory of the present invention, the second conductor layer as the main body of the capacitor lower electrode is formed not only on the inner wall of the self-aligning contact window opening, but also on the self-aligning contact window. The sidewall of the second insulating layer in the center of the opening, so the surface area of the lower electrode of the capacitor obtained by this method will be larger than the surface area of the lower electrode of the columnar capacitor obtained by the conventional method. In addition, since the template of the capacitor lower electrode in this method is self-aligning the upper half of the contact window opening, the formation of the node contact window and the capacitor lower electrode only requires a total of "the mask process that defines the self-aligning contact window opening." ". In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Brief description of the formula: Figures IA-ΙΕ (ΙΕ ') illustrate a method for manufacturing a capacitor lower electrode of a memory in a preferred embodiment of the present invention. Description of drawing numbers: 100: substrate 110: Shallow Trench Isolation (STI) 4 This paper size is applicable to China National Standard (CNS) A4 (2) 0 X 297 mm) Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the Consumer Cooperative 4444 Ο Ο 6219twf.d〇c / 006 Α7 __Β7 ___ V. Description of the Invention (彡) 120: Gate Dielectric Layer 130: Word Line HO: Cap Layer 150: Spacer 155: S / D Region 160, 190 '210: Insulation layer 170: Bit Line Contact 180 (Bit Line Contact) 180: Bit Line (Bit Line) 192: Self-Aligned Contact (SAC) 200: Conductor layer 200a: Node Contact 220, 230: Capacitor lower electrode For a description of the preferred embodiment, please refer to Figure 1A, first A substrate 100 is provided on which a shallow trench isolation layer 110 is formed. Next, a gate dielectric layer 120, a character line 130 above the gate dielectric layer 120, a cap layer 140 above the character line 130, and a gap wall on the sidewall of the character line 130 and the cap layer 140 are formed on the substrate 100. 150. The material of the cap layer 140 and the spacer 150 is, for example, silicon nitride (SiN). Next, a source / drain region 155 is formed in the substrate 100 on both sides of the spacer 150 to form a metal-oxide-semiconductor (MOS). Next, an insulating layer 160 is formed on the substrate 100, a bit line contact window 170 is formed in the insulating layer 160, and a bit line 180 is formed on the insulating layer 160. Next, the substrate 100 is covered with an insulating layer 190. The etching rate of the materials used for the insulating layers 190 and 160 is much higher than the etching rate of the capping layer 140 and the spacer 150, so as to facilitate the subsequent 5 paper standards applicable to the national solid standard ( CNS) A4 specifications < 21Q X 297 public love) ---- I ------ W installed------ Order 1-1! _ 线 " V. {Please read the note of the mee first Please fill in this page for further information) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4444 00 6219twf, doc / 006 A7 B7 V. Description of the invention) Self-alignment of the contact window process. That is, when the material of the capping layer 140 and the spacer 150 is silicon nitride, the material of the insulating layers 190 and 160 may be silicon oxide whose etching rate is much higher than that of silicon nitride. Referring to FIG. 1B, a self-aligned contact window opening 192 is formed in the insulating layers 190 and 160 to expose the drain / source region 155. Then, a conformal conductive layer 200 is formed on the insulating layer 190 and the self-aligned contact window opening 192, and the material is, for example, polycrystalline silicon. At this time, the self-aligned conductive layer 200 at the bottom of the contact window opening 192 becomes the node contact window 200a. An insulating layer 210 is then formed on the conductor layer 200, which is self-aligned to the contact window opening 192. Referring to FIG. 1C, the insulating layer 210 outside the self-aligned contact window opening 192 is removed, and the method is, for example, Plasma Etch or Chemical Mechanical Polishing (CMP). Please refer to FIG. ID. Next, the conductive layer 200 is etched back. The method is, for example, plasma etching to completely remove the conductive layer 200 except for the self-aligned contact window opening 192, and to continue to remove the self-aligned contact window opening 192. The inner conductive layer 200 reaches a certain depth. The next steps can be divided into two types, which are supplemented by illustrations 1E and 1E ', respectively. Referring to FIG. 1E, a conformal conductive layer (not shown) is formed on the substrate 100, and the material is, for example, polysilicon. Then, the conductive layer on the top of the insulating layers 190 and 210 and the surface of the node contact window 200a is removed, for example, by a plasma etching method, and the remaining conductive layer becomes the capacitor lower electrode 220. 6 This paper size applies the National Standard of the Country (CNS) A4 (21 × 297 mm) ------! _ !.) Packing ----- Order i 丨 --- Winding) (Please (Please read the notes on the back before filling this page) 4444 00 6219twf.d〇c / 006 A7 B7 V. Description of the invention (f) For another method, please refer to Figure 1E '. A layer of hemispherical silicon grains that completely covers the surface of the substrate 100 (not shown). Then, the hemispherical silicon grain layer located on the top of the insulating layers 190 and 210 and on the surface of the node contact window 200a is removed, for example, by a plasma etching method, and the retained hemispherical silicon grain layer becomes the capacitor lower electrode 230. The surface area is larger than the surface area of the lower electrode 220 of the capacitor. As described above, please refer to FIGS. 1E and 1E ′. In the manufacturing method of the capacitor lower electrode of the memory of the preferred embodiment of the present invention, the capacitor lower electrode 220 (230) is not only formed in the self-aligned contact window opening 192 The inner side wall is also formed on the side wall of the intermediate insulating layer 210 aligned with the self-aligned contact window opening 192, so the area of the capacitor lower electrode 220 (230) obtained by this method is larger than the surface area of the column capacitor lower electrode obtained by the conventional method. . In addition, since the template of the capacitor lower electrode 220 (230) is self-aligned to the upper half of the contact window opening 192 in this method, the formation of the node contact window 200a and the capacitor lower electrode 220 (230) only requires a "definition" Align the photomask process of the contact window opening 192 by yourself ". Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 7 Due to national standards in the application of this paper size (CNS > A4 specification (2) 0 X 297 mm> (Please read the precautions on the back before filling out this page) * ---- II Order ------ --I) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs