TW396617B - Manufacturing method of memory cell capacitor for dynamic random access memory in semiconductor device - Google Patents

Abstract

This is manufacturing method of memory cell capacitor for dynamic random access memory (DRAM) in semiconductor device. The method includes forming store node, which is self-aligned with the lower store node contact window opening. A first isolation layer is formed on a semiconductor substrate with a device region. A first material layer, a second isolation and a second material layer determine the store node height is sequentially formed. The first and second material layers correspond to the first and second isolation layers with etch selectivity. By using a first mask pattern to form a first opening, a first opening is formed in the second material layer and the portion from the second isolation layer to the first material layer. The first opening defines the store node region. A second opening is formed in the first material layer and the portion from the first isolation layer to the device region. An opening portion, which is smaller than the first region, is formed by using the second mask pattern to allow the first opening to self-align with the second opening. Additionally, the spacer wall on the first opening is used as a mask to form the second opening.

Description

4 I 62pif.doc / 002 A7 B7 V. Description of the invention The invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a dynamic random access memory (DRAM) memory cell in a semiconductor device. It can form a storage node that aligns itself with the contact hole in the lower layer. Capacitance to obtain enough stored charge in a small area is one of the most challenging design issues in the dynamic random access memory (DRAM) technology of ultra large integrated circuit (ULSI). Due to the increased incentive of high-density DRAM, the charge-storage elements of each memory cell must be able to fit into smaller and smaller areas. The reduction of the cell's electrostatic capacity due to shrinking the memory cell area is a serious obstacle to increasing the packing-density of the DRAM. Therefore, the problem of reducing the cell capacitance must be solved to obtain a semiconductor memory element with a high stack density. In order to keep the electrostatic capacity at an acceptable level, many methods have been proposed. For example, one way is to use a high permittivity dielectric material, such as BST, as the dielectric layer of the capacitor. Another approach is to increase the surface area of the capacitor by adding undulating surfaces, such as stacked capacitors. Such stacked capacitors include, for example, double stacked, fin stacked, columnar, spread-stacked, and box structured capacitors. Since the outer and inner surfaces can be used as effective capacitor areas, the columnar structure is most suitable as a three-dimensional stacked capacitor, and it is particularly suitable as an integrated memory cell. Recently, the new technology has been developed by engraving or controlling the nucleation of polycrystalline silicon and the length of 5 papers. The Chinese paper standard (CNS) A4 ^ (210 × 297 mm) ^ ------ ------ «.— (Please read the notes on the back before filling in this page), ΤΓ Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 4I62pif.doc / 002 A7 B7 Printed by the Industrial and Consumer Cooperatives. 5. Description of the invention () The state of the polycrystalline silicon storage electrode is modified, thereby increasing the effective surface area. A layer of hemispherical-grain (HSG) polycrystalline sand is deposited on the storage node to increase the surface area and electrostatic capacity. In recent years, 'lGiga bits and DRAM stacked capacitor cells with more than lGiga bits have attracted more attention. This is because there are many ways to form capacitors and extend from the cell area, so the increased electrostatic capacity does not need to be on the substrate. Add extra area. The manufacturing process of such a stacked structure has become quite complicated, and the required lithography technology will not be consistent with the very small size requirements at present or in the future. Figures 2A to 2C are flowcharts showing the steps of conventionally manufacturing a DRAM cell. It must be noted here that FIG. 1 (layout diagram of a DRAM element according to an embodiment of the present invention) is used to explain a conventional method. Figures 2A to 2C are sectional views taken along line A1-A1 'in Figure 1. Referring to FIG. 1 and FIG. 2A, an element isolation layer 3 is formed on the semiconductor substrate 1 to define storage node contact window regions 2a to 2c and bit line contact window regions (not shown in the figure). As is well known, a plurality of gate structures are formed on the semiconductor substrate 1 (not shown). A first silicon oxide layer 4a is formed on the semiconductor substrate 1 and on the word lines. A plurality of bit lines BL1 to BL4 are formed on the first silicon oxide layer crossing the word line 'through the contact window opening (not shown) in the first sand layer 4a' to contact the bit line. Zone electrical connection. Next, a second silicon oxide layer 4b is formed on the first silicon oxide layer 4a and the bit lines BL1 to BL4. Please refer to Figure 2B, and etch the first silicon oxide layer 4a and the first silicon oxide 6 (Please read the precautions on the back before filling in this page). Order < Γ. This paper size applies Chinese National Standard (CNS) A4 ^ (210X297) Chu A7 B7 4 I 62pif.doc / 002 V. Description of the invention () Layer 4b, forming several storage node contact window openings 6a to 6c, and exposing the storage node contact window areas 2a to 2c. Thereafter, a conductive layer composed of a polycrystalline silicon layer 8 is deposited on the storage node contact window openings 6a to 6c and on the second silicon oxide layer 4b. A photoresist layer (not shown) is deposited on the polycrystalline silicon layer 8 and patterned to define a storage node area. The polycrystalline silicon layer 8 'is then etched by using a photoresist pattern, thereby forming a plurality of storage sections 8a to 8c, as shown in FIG. 2C. Thereafter, a thin dielectric layer (not shown) and an upper electrode material layer (not shown) are deposited on the storage nodes 8a to 8c. In the above method, the polycrystalline silicon layer is usually overetched to electrically isolate each storage node from each other. During this engraving procedure, if an alignment error occurs, a portion of the polycrystalline silicon layer that is embedded in the contact window opening will be etched away, especially around the top edge of the contact window opening. Moreover, in the subsequent cleaning step, a part of the second silicon oxide layer between the storage nodes will be removed (that is, an undercut phenomenon), so the second silicon oxide layer may not be able to support the storage node, and the storage Festival may fall. These problems are exacerbated in extremely high-density components, and these cannot be avoided at lGiga bits or more. Figures 3A to 3C are schematic flowcharts showing a step of manufacturing a DRAM cell capacitor according to another conventional method. In FIGS. 3A to 3C, the same parts as those shown in FIGS. 2A to 2C are assigned the same reference numbers, and their explanations are omitted. Please refer to FIG. 3A. After forming a plurality of contact window openings 6a to 6c, a first conductive layer composed of a polycrystalline silicon layer 10 is deposited in the storage node contact window openings 6a to 6c. CNS A4 Zhuge (210X297mm) (Please read the precautions on the back before filling this page)

Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Printed by the Shellfish Consumer Cooperative of the Central Rubbing Bureau of the Ministry of Economy. 4 I 62pif.doc / 002 Λ 7 B7 _ V. Description of the invention () and formed several contact window plugs l〇 a to 10c. Referring to FIG. 3B, a third silicon oxide layer (not shown) is formed on the second silicon oxide layer 4b and the contact window plugs 10a to 10c. A photoresist pattern (not shown) is deposited on the third silicon oxide layer, and the third silicon oxide layer is etched to form a structure of several storage nodes (not shown in the figure), which will be deposited for the second conductive layer. Office. These structures, the second contact window openings, expose the upper surfaces of the contact window plugs 10a to 10c. These structures are filled with a second conductive layer and planarized. Next, the oxide structure is removed by dry or wet etching, thereby forming several storage sections 12a to 12c, as shown in FIG. 3B. However, this manufacturing process uses two illumination steps to define the storage node, the contact window plug, and the storage node, which all complicate the process. In addition, the step of removing the oxide structure is not easy to control. If it is over-etched, the polycrystalline silicon in the structure may be etched, and bit lines may even be exposed in severe cases. Therefore, during the step of forming the upper electrode layer, the exposed bit lines are susceptible to attack. In order to prevent the bit line from being attacked, an etch stop layer such as a silicon nitride layer 5 may be formed between the second and third silicon oxide layers, as shown in FIG. 3C. Even after the etching stop layer 5 is formed, an undercut phenomenon occurs due to misalignment during the etching and cleaning processes (see 13 in the figure). This will lead to an increase in current leakage and subsequent step coverage of the electrodes on the capacitor. The present invention is directed to the above-mentioned problems, so one of the purposes of the present invention is to apply the Chinese National Standard (CNS) 8 # # 格 (210X297:)) to 8-scale ~ (Please read the precautions on the back before filling this page) • 1— i —1 ·

1. 1T 4l62pif.doc / 002 A7 4l62pif.doc / 002 A7 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, V. Description of the Invention (In the provision of a semiconductor cell manufacturing method for a dram capacitor, it can form a relative The self-aligned storage section of the touch window plug can avoid misalignment between the storage section and the storage section contact window opening. According to the above and other purposes of the present invention, it can be formed on two semiconductor substrates. -Field-effect transistor. This field-effect transistor includes ^-a gate with-an insulating layer and an insulating sidewall interposed thereon, and-a source / drain region near the field-effect structure. On this semiconductor substrate and this field-effect transistor, a "first" insulating layer composed of an oxidized sand layer is formed. A "bit line" is formed on this-insulating layer-the bit line and the source / drain region -Electrical connection. Then 'a second insulating layer is deposited on this first insulating layer and on the bit line, this second insulating layer is composed of an oxide sand layer. H is sequentially formed on this second insulating layer Material layer, the third insulation layer and the fth material layer. When the material layer and the second material layer are -__ with respect to the second and third buttons, and the duty layer is formed of hafnium oxide, the first material layer and the second material layer may be nitrided sand layers or polycrystalline Sand layer. The thickness of the deposited third insulating layer is about the predetermined height of the storage node, and the storage node is directly related to the electrostatic capacity. Sinking on the second material layer-the first-photoresist pattern. Etching the second material layer and the third The insulating layer is used as the first material layer of the etching stop layer to form 1. After removing the first photoresist pattern, a second photoresist pattern having an opening size smaller than that of the first photoresist pattern is continuously formed. The first material H insulation layer and the first insulation layer are engraved to form a second opening, and the second opening exposes another source / drain region. Here, the opening: aligns itself with the first opening . In the first and second openings, and the second and third openings: a number of paper sizes are formed on the material layer to apply the Chinese National Standard (CNS) A4 Zhuge (210 ^ 297 ^. ^ 7 (Please read the note on the back first) $ Item to fill in this page) Order 4 I 62pif.doc / 002 ^ 7 4 I 62pif.doc / 002 ^ 7 The Central Government Bureau of the Ministry of Economic Affairs Printing 5. Description of the invention () A crystalline silicon layer. Then, the conductive layer is planarized by etch-back or chemical mechanical honing method (CMP) until the upper surface of the third insulating layer is exposed. Then, the third insulating layer is removed by wet etching, and thus a storage node is formed that does not resemble a conventional misalignment. Here, if the first material layer is a polycrystalline silicon layer, it needs to be removed to isolate each —Storage section. In another embodiment of the present invention, the second photoresist pattern formed above has an elongated opening and includes at least two storage section contact window regions. In this example, the second material Layer and strip-shaped photoresist pattern—act as an etching mask. Therefore, the 'lithography process can be easily performed and provides good lithography pattern stability. The other process steps are in the same order as the processes described above. & In yet another embodiment of the present invention, the second photoresist pattern is replaced with a conductive sidewall spacer of the second opening. That is, after the first photoresist pattern is removed, a first conductive layer, such as a polycrystalline silicon layer, is deposited in the first opening and on the second material layer. This first conductive layer is etched back to form sidewall spacers in the sidewalls of the openings. The side wall spacer and the second material half-bucket layer are used as a mask 'to etch the first material layer, the second insulation layer and the first insulation layer to form a second opening. Thereafter, a second conductive layer is formed in the first opening and the second opening, and on the second material layer. Then, the second conductive layer is planarized by etchback or mechanical honing, until an upper surface of the third insulating layer is exposed. After that, the third insulating layer is removed by wet etching, and thus a storage node is formed which does not resemble a conventional misalignment. If the first material layer S polycrystalline silicon layer, it needs to be removed. In this embodiment, the advantage is that the number of illumination steps can be reduced, so that the manufacturing process can be simplified and the manufacturing cost can be reduced. This paper size applies the Chinese national standard (CNS > A4 Zhuge (210X297 mm) ---- ^ ------- JM ------ order ------ 1 v .. ' -.. (Please read the notes on the back before filling out this page} 4 1 62pif.doc / 002 A 7 B7 V. Description of the invention () In order to make the above and other objects, features, and advantages of the present invention more obvious and easier Understand that the three preferred embodiments are described in detail below in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings: FIG. 1 shows a layout of a DRAM device according to a preferred embodiment of the present invention. Figures 2A to 2C are schematic cross-sectional views showing the manufacturing process of a conventional DRAM; Figures 3A to 3C are schematic cross-sectional views showing the manufacturing process of another conventional DRAM; Figures 4A to 4 FIG. 4E is a schematic diagram showing a manufacturing process of a DRAM cell capacitor in a semiconductor device according to a first preferred embodiment of the present invention. Another preferred embodiment is a layout diagram of a DRAM structure; and FIG. 6 is a schematic cross-sectional view taken along A2-A2 ′ in FIG. 5. 。 Description of the marks on the drawings: Printed by the Consumer Procurement Cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 1, 100, 200 Semiconductor substrates 2a to 2c Storage section contact window areas 2a to 2d , 202a to 202d Active area 3, 103 Element isolation layer 4a, 104a First oxidized sand layer 4b, 104b Second silicon oxide layer 5 Etching stop layer This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) τ- --- ιΤιιιίίι Ίιΐ ΐι u- + 4 I 62pit'.doc / 002 A7 B7 V. Description of the invention (6a to 6c) Storage section contact window opening (second opening) 8 Polycrystalline silicon layer 8a to 8c, 12a to 12c storage section 10a to 10c Contact window plug 13 Undercut phenomenon 104, 204 First insulating layer 106, 206 First material layer 108, 208 Second insulating layer 110, 210 Second material layer 11 la to 11 lc, 114a to 114c Storage section 112 No. Second mask pattern 114 Conductive layers 211a to 211c First opening 212 Conductive material layer 212 Side wall spacers 213a and 213b Strip-shaped opening portions 213a-1 to 213a-3 Second opening embodiment For the purpose of practicing the present invention, DRAM cell capacitance The manufacturing method of the device will be explained in detail according to the attached drawings. This DRAM cell capacitor can be manufactured on the field effect transistor used to make a dram today. Therefore, only the details of the underlying structure necessary for the present invention will be described. Please refer to Figure 1 and Figures 4A to 4E. 'The following explains that the paper size of the present invention is applicable to the Chinese national standard (CNS > Μ 格格 (2 丨 0X297 mm >) (Please read the precautions on the back before filling in (This page) -s Γ Printed by the Central Sample Rate Bureau Shellfish Consumer Cooperative of the Ministry of Economic Affairs 4 I 62pif.d0c / 002 A7 B7 V. The first preferred embodiment of the invention description (1). A preferred embodiment of the present invention is a layout diagram of a DRAM device. Figures 4A to 4E show a manufacturing process of a DRAM cell capacitor in a semiconductor device according to a first preferred embodiment of the present invention. Schematic cross-section of A1-Al in Fig. 1. Please refer to Fig. 1. In a predetermined area of a semiconductor substrate, several active regions 2a to 2d are defined (not shown in Fig. 1). As is known in the art The active areas 2a to 2d include storage section contact window areas 6a to 6c and bit line contact window areas (the numbers are not shown in the figure). Several word lines WL1 to WL4 cross the active areas 2a to 2d, and several bits The lines BL1 to BL4 are intersected with the word lines WL1 to WL4 and neutralize the semiconductors in the bit line contact window openings. The bit line of the substrate is in contact with the window area (not shown), but in other areas, it is in contact with the semiconductor substrate and the word lines WL1 to WL4 through a thick insulating layer (not shown in Figure 1). Several storage nodes 111a to 111c are in contact with the storage node contact window areas 6a to 6c of the semiconductor substrate, but in other areas, they are in contact with each other through another thick insulating layer (not shown in Fig. 1). The semiconductor substrate, the bit lines BL1 to BL4 and the word lines WL1 to WL4 are isolated. Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). With the element isolation region 103, a plurality of active regions 2a to 2c are defined in the semiconductor substrate 100. The active regions 2a to 2c include the storage node contact window regions 6a to 6c in the first figure, and the bit line contact window regions (Fig. The number is not indicated in the number). As is known in the art, the element isolation region 103 is formed by shallow trench isolation or sand area oxidation (LOCOS). Numbers are formed across the active regions 2a to 2c Gate 13 This paper size applies to Chinese national standards CNS) A4 size (210X297 mm) 4162pif.doc / 002 A7 4162pif.doc / 002 A7 Ministry of Economic Affairs Bureau of the Central rub Mou ®: Engineering consumers' cooperative printed B7 V. description of the invention ()

Pole structure, and adjacent to the storage section contact window areas 6a to 6c, although not shown in Figure 4A. On the semiconductor substrate 100 and the gate structure, a first insulating layer 104 having bit lines BL1 to BL4 is formed. In short, the first silicon oxide layer 104a is formed on the entire semiconductor substrate 100. A plurality of bit lines BL1 to BL4 are formed on the first silicon oxide layer to intersect with the gate structure, and in the bit line contact window opening (not shown in the figure), the bit line contact window of the semiconductor substrate 100 Contact with each other, but in other regions, it is isolated from the semiconductor substrate 100 and the gate structure by the first silicon oxide layer 104a. After the bit lines BL1 to BL4 are formed, a second silicon oxide layer 104b is formed on the bit lines BL1 to BL4 and on the first silicon oxide layer 104a. A first material layer 106, a second insulating layer 108, and a second material layer 110 are sequentially formed on the second silicon oxide layer 104b. Here, we must note that the first material layer 106 and the second material layer 110 have an etching selectivity with respect to the first insulating layer 104 and the second insulating layer 108. If the second insulating layer is a silicon oxide layer, the first material layer 106 and the second material layer 110 are a silicon nitride layer or a polycrystalline silicon layer. The thickness of the first material layer 106 and the second material layer 110 is about 10 nm to 90 nm. The deposited thickness of the second insulating layer is about the expected height of the storage node that determines the electrostatic capacity, about 0.5 μm to 1.5 μm, and preferably about 0.8 μm to 1.2 μm. A first mask pattern (not shown) is formed on the second material layer 110, such as a photoresist layer. Using the first mask pattern, the second material layer 110 and the second insulating layer 108 are etched to form a plurality of first openings Ilia to 111c, which expose the first material layer 106, as shown in FIG. 4B. This paper size applies Chinese National Standard (CNS) A4 Zhuge (210X297 mm) (Please read the precautions on the back before filling this page) I 丨 Prostitute ·

、 TT of the Central Bureau of the Ministry of Economic Affairs of the Central Government Bureau of Shellfish Consumer Cooperatives 4 1 62pif.doc / 002 A7 _ _B7 V. Description of the invention (). Here, the first material layer 106 is used as an etch stop layer, and the second material layer 110 can prevent the size of the first openings 111a to 111c from increasing. Referring to FIG. 4C, a second mask pattern 112 is formed to define the opening of the storage window contact window. Here, we must pay attention to the fact that the opening portion of the second mask pattern 112 is smaller than the first mask pattern. This can be clearly seen by comparing the reference numbers 6a to 6c and 111a to 111c in the first figure. The second mask pattern 112 is used to etch the first material layer 106 and the first insulating layer 104 to form a plurality of second openings 6a to 6c, which are respectively aligned with the first openings Ilia to 111c and exposed. The active areas 2a to 2c (more specifically, the storage section contact window areas 6a to 6c). Here, it should be noted that in order to make the present invention easier to understand, the reference numbers of the second openings 6a to 6c are the same as the storage section contact window area. In FIGS. 2 and 3, the second openings 6a to 6c correspond to the conventional storage node contact window openings. At this time, the first material layer 106 can prevent the size of the second openings 6a to 6c from increasing. After the second mask pattern 112 is removed, a conductive layer Π4, such as a polycrystalline silicon layer, is deposited over the second material layer 110 in the first and second openings. The conductive layer Π4 and the second material layer 110 are planarized from the top to the second insulating layer 108. This planarization process can be implemented by etch-back or chemical mechanical honing (CMP), as shown in Figure 4D. Then, the insulating layer 108 other than the conductive layer is removed by wet etching, thereby forming a plurality of storage sections 114a to 114c aligned with the storage section contact window openings 6a to 6c, as shown in Fig. 4E. In this step, the first material layer 106 is used as a barrier layer and an etch stop layer to prevent undercutting. If the first material layer 106 is polycrystalline silicon, the first must be removed (please read the note on the back before filling this page)

This paper size applies the Chinese national standard (CNS > A4 (210X297 mm)) Printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Lijing 1 62Pif.doc / 002 A 7 ～ _____ ϋ ____ 5. Description of the invention () Material layer Each storage node is electrically isolated. After that, a dielectric layer (not shown in the figure) and an upper electrode layer (not shown in the figure) are deposited, thereby completely forming the entire capacitor. Then, the entire semiconductor substrate is deposited. A third insulating layer (not shown in the figure). Secondly, the contact window metallurgy (not shown in the figure) which is known in the art is used to deposit and define the pattern. Higher-level metallurgy can be formed on the metal layer ( (Not shown in the figure) and passivation to complete the FET and DRAM components. For example, higher-level metallurgical contact windows are necessary for capacitor electrodes. Subsequent manufacturing processes must be performed in accordance with conventional methods. The inner metallurgy and protective layer are connected to complete the integrated circuit of the present invention. A second embodiment of the present invention is described with reference to FIG. 5 which shows a second preferred embodiment according to the present invention. Embodiment 'A layout diagram of a DRAM structure. A significant difference from the foregoing first embodiment is that the novel mask pattern in the second embodiment shown in FIG. 5' is used instead of the one shown in FIG. 4C. The second mask pattern. That is, the formed second mask pattern has elongated opening portions 213a and 213b 'along the character line directions WL1' and WL2 ', WL3' and WL4 ', and Located between the word line directions WL1 'and WL2', and between WL3 'and WL4'. The elongated opening portions 213a and 213b include at least two adjacent storage node contact window regions. The description is made with reference to FIGS. 5 and 6, and FIG. 6 is a schematic cross-sectional view taken along A2-A2 'of the DRAM in FIG. 5. The same process steps as those in the first embodiment will be briefly described. Please refer to FIGS. 5 and 6 to form numbers in the semiconductor substrate 200 (please read the precautions on the back before filling this page)

This paper size applies the Chinese national standard (Liyang> 8 4 private grid (2 丨 0 father 297 mm) 4 I62pif.doc / 002 Printed by the Shellfish Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention ( ) Element isolation regions 103 are used to define a plurality of active regions 202a to 202d. A plurality of gate structures (not shown) are formed on the semiconductor substrate 200. A plurality of bit lines are deposited on the semiconductor substrate 200 The first insulating layers 204 of BL1 'to BL4'. A first material layer 206, a second insulating layer 208, and a second material layer 210 are sequentially formed on the first insulating layer 204. A first cover is used. Curtain pattern (not shown in the figure), a plurality of first openings 211a to 211c are formed in the second material layer 210 and the second insulating layer 208. The process before this step is the same as the conventional method. Please refer to FIG. After the first mask pattern is removed, a novel second mask pattern (not shown in the figure) in this embodiment is formed, which has a plurality of long strips along the direction of the character lines and between the character lines. Opening portions 213a and 213b. As shown in Fig. 5, the elongated opening portion 2 is formed 13a and 213b have a smaller width than the first openings 211a to 211c (which is measured along the bit line direction). Although the elongated openings 213a and 213b expose a part of the second material layer 210, However, the second material layer 210 is used as an etching mask together with the second mask pattern, so that it can prevent contact with the underlying bit lines BL1 'to BL4'. The second mask pattern and the second material layer 210 are used for etching The cover is etched with the first material layer 206 and the first insulating layer 204 to form a plurality of second openings 213a-1 to 213a-3 to the contact region of the storage section of the semiconductor substrate 200 (reference numbers are different), as described in Section 6 As shown in the figure. The subsequent process steps are the same as the first embodiment and their explanations are omitted. From the explanation of the present invention, it is clear that according to the second implementation of the present invention (please read the precautions on the back before filling this page)

This paper size applies to Chinese National Standards (Series 0) Vol. 8 ^ (210 Father 297 mm) Seal of the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives Co., Ltd. A7 B7____ 5. Explanation of the invention () Example, defining the opening of the contact window of the storage section The second mask pattern 'has a larger opening area than the first embodiment, that is, a long opening portion. Therefore, the lithography process can be easily implemented, and it can provide good lithography pattern stability without the "contact window not opening" occurring. In addition, there are advantages of the aforementioned first embodiment. Referring to Fig. 5 and Fig. 6, another embodiment of the present invention will be described further. In the third embodiment, the main difference from the first and second embodiments is that a side wall gap wall is formed on the side wall of the first opening without forming a second mask pattern. In other words, 'this side wall gap serves as a mask forming the second opening. Explanation of the same process steps as those of the first embodiment and the second embodiment is omitted. Referring to FIG. 6, after removing the first mask pattern, a conductive material layer 212, such as a polycrystalline silicon layer, is deposited in a thickness of about 5 nm to 30 nm in the first openings 211a to 211c and on the second material layer 210. It has an etch selectivity with respect to the first and second insulating layers 204 and 208. Then, the polycrystalline silicon layer is etched to form sidewall spacers 212 in the first openings 211a to 211c, respectively. Using the sidewall spacer 212 and the second material layer 210 as an etching mask, the first material layer 206 and the first insulating layer 204 are etched to form a plurality of second openings 213a-1 to 213a-3, which are self-aligned to The first openings 211a to 211c. The subsequent process steps are the same as the first and second embodiments described previously. The present invention has been specifically presented and described with reference to the preferred embodiments. However, those skilled in the art should understand that various changes in form and details can be made without departing from the spirit and scope of the present invention. , 4 1 62pif.doc / 002 (Please read the notes on the back before filling this page)

、-| T This paper size applies Chinese national standard (CNS> A4 Zhuge (210X297mm) 4 I 62pif.doc / 002 A7 B7 V. Description of the invention () Therefore, the scope of protection of the present invention shall be regarded as the attached patent The range is subject to definition. Especially it can be applied to the formation of bonding pads on the openings of contact windows. (Please read the precautions on the back before filling this page) J— · Order the work of the Central Standards Bureau of the Ministry of Economic Affairs The paper size printed by the consumer cooperative is applicable to the Chinese National Standard (CNS) A4 Zhuge (210X297 mm) ~ ~ ·· rriirruitKi

Claims (1)

ABCD 4 I 62pif.doc / 002 VI. Patent application scope · A method for manufacturing a dynamic random access memory memory cell capacitor includes the following steps: Provide a semiconductor substrate having a gate structure on the semiconductor substrate 'and and A source / drain on one side edge of the gate structure is self-aligned, and a first insulating layer including a bit line is formed on the semiconductor substrate including the gate structure, and the bit line is configured On the gate layer and below an upper surface of the first insulating layer; on the second insulating layer, a first material layer, a second insulating layer, and a second material are sequentially formed; Layer, the first material layer and the second material layer have an etch selectivity relative to the first insulating layer and the second insulating layer; forming a first mask pattern on the second material layer; using the first A mask pattern, and a first opening is formed in the second material layer and the second insulation layer to the first material layer; removing the first mask pattern; forming having an opening width smaller than the first First of the curtain pattern Two mask patterns; forming a second opening in the first material layer and the first insulating layer to the source / drain region; removing the second mask pattern; filling the first with a conductive layer An opening and the second opening; planarizing etching the conductive layer and the second material layer until the second insulating layer is exposed; and 20 paper sizes applicable to the Chinese National Standard (CNS) A4 size (210X297 mm) (Please read the precautions on the back before filling this page), tT Γ Printed by the Central Government Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, A8 B8 41 (l2plrd〇C / 〇 ° 2_D8_ VI. Apply for a patent to remove the second insulation Layer, thus forming a storage section. 2. The method for manufacturing a dynamic random access memory memory cell capacitor as described in item 1 of the patent application scope, wherein the thickness of the second insulating layer is about 0.5 μm to 1.5 μm 3. The method for manufacturing a dynamic random access memory memory cell capacitor as described in item 1 of the scope of the patent application, wherein each of the first material layer and the second material layer includes a polycrystalline silicon layer and a silicon nitride layer. 1. 4. According to the method for manufacturing a dynamic random access memory memory cell capacitor according to item 1 of the scope of patent application, the thickness of each of the first material layer and the second material layer is about 10 nm to 90 nm. The method for manufacturing a dynamic random access memory memory cell capacitor described in item 1 of the scope of the patent application, after removing the second insulating layer, further includes removing the first material layer other than the storage section. 6. — A manufacturing method of a dynamic random access memory memory cell capacitor includes the following steps: providing a semiconductor substrate having a gate structure on the semiconductor substrate and a source electrode self-aligned with a side edge of the gate structure; / Drain region; Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) on the semiconductor substrate including the gate structure to form a first An insulating layer, the bit line is disposed above the gate layer and is located below an upper surface of the first insulating layer; and a first material layer is sequentially formed on the second insulating layer, The second insulating layer and a second material layer, the first material layer and the second material layer have an etching option relative to the first insulating layer and the second insulating layer. This paper size uses Chinese National Standards (CNS). A4 specification (210X297 mm) 4l62pif.doc / 002 A8 B8 C8 D8 6. Scope of patent application; forming a first mask pattern on the second material layer; using the first mask pattern, and Two material layers and the second insulating layer into the first material layer to form a first opening; removing the first mask pattern; forming a second mask pattern having a long opening portion, Between the bit lines, the elongated opening portion includes at least two storage node contact window areas, and measured along the direction of the bit lines, the second mask pattern has an opening width larger than The first mask pattern is small; a second opening is formed in the first material layer and the first insulating layer to the source / drain region; the second mask pattern is removed; a conductive layer is used Fill the first opening and the second opening; planarize the etching Conductive layer and the second material layer until the second insulating layer is exposed; and removing the second insulating layer, thereby forming a storage section. 7. The method for manufacturing a dynamic random access memory memory cell capacitor according to item 6 of the scope of the patent application, wherein the thickness of the second insulating layer is about 0.5 μm to 1.5 μm. 8_ The method for manufacturing a dynamic random access memory device described in item 6 of the patent application scope, wherein each of the first material layer and the second material layer includes a polycrystalline silicon layer and silicon nitride One of the layers. 9. The method for manufacturing a dynamic random access memory memory cell capacitor as described in item 6 of the scope of the patent application, wherein each of the first material layer and the 22nd paper size are applicable to China National Standard (CNS) A4 (210X297 mm) C ------ Order ------ 疒, (Please read the notes on the back before filling in this page) The Central Ministry of Economic Affairs, Ministry of Economic Affairs, Bureau of Shellfish Consumer Cooperatives, India, ABCD 4 I 6 2pit.doc / 002 Sixth, the scope of patent application 2 The thickness of the material layer is about 10nm to 90nm. (Please read the precautions on the back before filling out this page) 10. The method for manufacturing a dynamic random access memory memory cell capacitor as described in item 6 of the scope of patent application, after removing the second insulating layer, further includes Remove the first material layer outside the storage node. 11. A method for manufacturing a dynamic random access memory memory cell capacitor in a semiconductor device, comprising the following steps: providing a semiconductor substrate having a gate structure on the semiconductor substrate, and self-aligning with a side edge of the gate structure; A quasi-source / drain region, on the semiconductor substrate including the gate structure, forming a first insulating layer including a bit line, the bit line being disposed on the gate layer, and Is located below an upper surface of the first insulating layer; on the second insulating layer, a first material layer, a second insulating layer and a second material layer are sequentially formed; the first material layer and the first material layer; The two material layers have an etching selectivity with respect to the first insulating layer and the second insulating layer; a first mask pattern is formed on the second material layer; printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The first mask pattern, and forming a first opening in the second material layer and the second insulating layer to the first material layer; removing the first mask pattern; and neutralizing in the first opening The second material layer Depositing a third material layer, etching the third material layer, and forming a gap wall in the sidewall of the first opening; using the second material layer and the gap wall as a mask, and The paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) ABCD 4 1 62pif.doc / 002 6. Application scope of patents-a material layer and the first insulation layer to the source / drain region, forming a A second opening; removing the second mask pattern; filling the first opening and the second opening with a conductive layer; planarizing and etching the conductive layer and the second material layer until the second insulating layer is exposed And removing the second insulating layer, thereby forming a storage node. 12. The method for manufacturing a dynamic random access memory memory cell capacitor in a semiconductor device according to item 11 of the scope of patent application, wherein the thickness of the second insulating layer is about 0.5 μm to 1.5 μm. 13. The method for manufacturing a dynamic random access memory memory cell capacitor in a semiconductor device according to item 11 of the scope of patent application, wherein each of the first material layer and the second material layer includes a polycrystalline silicon layer and a silicon nitride layer. Among them-〇14. The method for manufacturing a dynamic random access memory memory cell capacitor in a semiconductor device as described in item 11 of the scope of the patent application, wherein the thickness of each of the first material layer and the second material layer is approximately 1 Onm to 90 nm. 15. The method for manufacturing a dynamic random access memory memory cell capacitor in a semiconductor device according to item 11 of the scope of patent application, wherein the thickness of the third material layer is about 5 nm to 3 nm. 16. The method for manufacturing a dynamic random access memory memory cell capacitor in a semiconductor device as described in item 11 of the scope of the patent application, wherein the third material layer is provided with respect to each of the first insulating layer and the second insulating layer. An etch selectivity. 24 The scale of this moth applies to the Chinese National Standard for Standards (CNS) A4 (210X297 male f " (Please read the precautions on the back before filling out this page), tr • c Printed by the Central Labor Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative 4 I 62pif.doc / 002 A8 B8 C8 D8 6. Application for patent scope π. The method for manufacturing a dynamic random access memory memory cell capacitor in a semiconductor device as described in item π of the patent scope of application, wherein the gap is formed by Made of the same material as the conductive layer of the storage section. 18. A method for manufacturing a dynamic random access memory memory cell capacitor in a semiconductor device as described in item 17 of the scope of patent application, in which the spacer is formed The material includes a polycrystalline silicon layer. 19. The method for manufacturing a dynamic random access memory memory cell capacitor in a semiconductor device as described in item 11 of the patent application scope, further comprising removing the storage node after removing the second insulating layer. The first material layer other than this. (Please read the notes on the back before filling this page) Associate degree suitable for China's national Qiu (CNS) Α4 size (210X297 mm)