B7 經濟部中央標準局員工消費合作社印製 五、 發明説明 ( ) 1 1 背 景 說 明 1 I 動 態 隨 機 存 取 記 憶 器 (D yn a m i C R an do m Ac c e s S Μ e m or 1 y) 為 般 電 m 常 用 記 憶 器 之 P 其 基 本 單 元 (C el 1) 是 由 —- /«—V 1 I 請 | 個 場 效 電 晶 體 並 串 聯 一 個 電 容 所 組 成 ό 電 容 之 主 要 作 用 是 先 閱 I I • 讀 1 儲 存 信 號 電 荷 (c h a Γ g e), 藉 該 電 容 之 是 否 儲 存 電 荷 Μ 代 表 背 1 I 電 腦 之 "0 ”或” 1 " 信 息 賫 而 積 體 電 路 尚 有 其 他 寄 生 電 容 如 電 之 注 1 晶 體 閘 極 與 汲 極 (或源極） 之 等 效 電 容 或 位 元 線 (b it 1 in e ) 事 項 1 再 1 I 與 矽 基 底 之 等 效 電 容 等 〇 因 此 若 該 DRAM 之 電 容 值 比 其 他 寄 填 1 生 電 容 值 要 小 (尤其是位元線電容， 因- -般而言閘極與 汲 % 本 頁 裝 1 極 /源極電容值較小） > 則 電 容 内 儲 存 電 荷 極 易 自 串 聯 並 等 1 1 通 之 場 效 電 晶 體 流 失 Μ 其 他 寄 生 電 容 t 造 成 儲 存 之 信 號 不 1 I m 及 周 邊 m 取 電 路 所 讀 取 信 息 之 可 靠 度 變 差 〇 故 DRAM 之 電 1 1 訂 1 容 值 應 儘 可 能 增 t 以 提 高 元 件 之 可 靠 度 0 又 基 本 上 參 積 體 電 路 所 使 用 之 電 容 器 係 由 兩 層 複 晶 矽 1 I 做 為 電 極 > 及 中 間 夾 一 ΟΝΟ (Οχ id e - N i tr id e - Ox id e ) 介 電 質1 1 1 層 所 構 成 0 其 電 容 量 與 兩 層 複 晶 矽 之 面 積 成 正 比 > 而 與 0N i 1 〇之厚度成反比。 當0N0 厚 度 薄 到 製 程 之 極 限 時 t 只 好 增 加 線 | 複 晶 矽 之 接 觸 面 積 〇 惟 增 加 複 晶 矽 接 觸 面 積 之 月U 題 條 件 必 1 ί 須 是 不 增 加 元 件 所 佔 晶 片 面 積 $ 習 知 作 法 有 多 種 〇 其 包 括 1 1 埭 溝 (t re n c h) 结 構 > 主 要 係 將 電 容 器 之 第 1 電 極 形 成 類 U 1 I ，'V ”字形， 其 上 再 叠 層 介 電 質 及 第 2 電 極 0 又 為 增 加 複 晶 1 1 矽 之 接 觸 面 積 9 習 知 的 作 法 是 先 沈 積 層 非 晶 矽 (a 10 〇 Γ P Μ 1 1 U S ), 再於高溫氮氣中進行熱處理（an n e a 1 ), 使非晶矽之 1 I 表 面 形 成 複 晶 矽 之 驛 粒 (δ r a i η )狀， 增加表面之粗描度。 1 1 -3 1 1 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 297921 A7 B7 五、發明説明（） 惟該習知技術所形成之表面粗描效果並不明顗，因此遂有 必要提出一種更有效之提高複晶矽粗梭效果，並進而大量 增加表面接觸面積之解決方法。 發明概述： 本發明主要目的係提供一種製裎簡化且可增加電容器 容量之方法。 本發明進一目的係提供一種可增加DARM元件密度之方 法。 本發明主鼙係藉將電容器之複晶矽電極形成在一待殊 製成之雙層晖槠氣化層上，以使複晶矽具有高低起伏之粗 链表面，以增加該電極與介電質層之接觸面積，並進而提 高電容器之電容置。 附圖說明： 圖一為複晶矽沈積在平坦氣化曆之SM圃。 圖二為複晶矽沈損在〇3/TE〇S與PE TEOS構成之雙層粗掩氧 化層之SE Μ圖。 圖三為依據本發明之DRAM元件剖面圖。 詳细說明：B7 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of the invention () 1 1 Background description 1 I Dynamic random access memory (D yn ami CR an do m Ac ces S Μ em or 1 y) The basic unit (C el 1) of the commonly used memory is composed of —- / «— V 1 I please | a field effect transistor and a capacitor in series. The main function of the capacitor is to first read II • read 1 to store the signal Charge (cha Γ ge), by means of whether the capacitor stores charge M represents the " 0 " or “1 " information of the back 1 I computer. The integrated circuit still has other parasitic capacitances such as electricity Note 1 The crystal gate and The equivalent capacitance of the drain (or source) or bit line (bit 1 in e) Item 1 Re 1 I and the equivalent capacitance of the silicon substrate, etc. Therefore, if the capacitance value of the DRAM is larger than other capacitance Value Small (especially the bit line capacitance, because-generally speaking, the gate and sink% are installed on this page 1 pole / source capacitance value is small) > then the stored charge in the capacitor is very easy to connect in series and wait 1 1 pass Field effect transistor loss M Other parasitic capacitance t causes the stored signal to be less than 1 I m and the reliability of the information read by the peripheral m fetch circuit deteriorates. Therefore, the power of the DRAM 1 1 Set 1 The capacitance should be increased as much as possible to improve The reliability of the component is 0. Basically, the capacitor used in the integrated circuit is composed of two layers of polycrystalline silicon 1 I as the electrode > and the middle clamp is ΟΝΟ (Οχ id e-Ni tr id e-Ox id e) The dielectric 1 1 1 layer consists of 0 whose capacitance is proportional to the area of the two layers of polycrystalline silicon> and inversely proportional to the thickness of 0N i 1 〇. When the thickness of 0N0 is thin to the limit of the manufacturing process, t has to increase the line | the contact area of the polycrystalline silicon. However, the contact area of the polycrystalline silicon is increased. The condition must be 1 ί It must not increase the chip area occupied by the device. There are a variety of them, including 1 1 t re nch (t re nch) structure> Mainly, the first electrode of the capacitor is formed into a U 1 I-like, 'V' shape, and then a dielectric and second electrode are stacked on it. Increasing the contact area of polycrystalline 1 1 silicon 9 The conventional method is to first deposit amorphous silicon (a 10 〇Γ P Μ 1 1 US), and then perform heat treatment in high temperature nitrogen (an nea 1) to make the amorphous silicon The surface of No. 1 I is formed with the shape of polycrystalline silicon (δ rai η), increasing the roughness of the surface. 1 1 -3 1 1 1 1 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) Printed 297921 A7 B7 by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention () The effect of rough surface description is not clear, so it is necessary to propose a more effective solution to improve the effect of polycrystalline silicon coarse shuttle, and then to increase the surface contact area by a large amount. Summary of the invention: The main purpose of the present invention is to provide a simplified manufacturing method and A method for increasing the capacity of a capacitor. A further object of the present invention is to provide a method for increasing the density of a DARM device. The main purpose of the present invention is to form a double-layer gasification layer to be made by forming a polycrystalline silicon electrode of a capacitor In order to make the polycrystalline silicon have a rough chain surface with high and low undulations, to increase the contact area of the electrode and the dielectric layer, and thus to increase the capacitance of the capacitor. BRIEF DESCRIPTION: Figure 1 shows the polycrystalline silicon deposited on the flat gas The SM nursery of chemical calendar. Figure 2 is the SE Μ diagram of the double-layer rough mask oxide layer composed of polycrystalline silicon deposited in 〇3 / TE〇S and PE TEOS. Figure 3 is the cross-sectional view of the DRAM device according to the present invention. Detailed instructions:
本發明經由下面實驗，得一有用讓實。即利用〇3/teo S沈積在PECVD(電漿糖助化學氣相沈積〉成長之氧化矽上， 其中03/1日05係代表03氣體與“1^361^£^丫以18116 5丨（0(：21^ )4 (簡稱TEOS)化搴溶液之揮發氣髖混合並分解反應生成之 氧化矽薄膜（本說明軎以下所稱之03/TE0S,或TEOS皆代表 該方法所形成之氧化矽薄膜 然後用SEM友APM踢察在PE -r-4 - 本紙張尺.度適用中國國家標準（CNS ) A4規格（210X297公釐） 1 訂 線 (請先閲請背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明（） TEOS上03/TE0S之表面粗造度。结果發現〇3/TEOS在成長之 初期會形成島狀（Island)结構。因此，若能將電容器之複 晶矽電極沈積在上述〇3/TEOS之島狀结構上，則該複晶砂 薄膜會順著島狀结構成長，使複晶矽薄膜之表面粗描度大 為提高，意即得到非常凹凸不平之平面，故能大量增加複 晶矽與介電質層之有效接觸面積。 為了加Μ驗證，我們以複晶矽長在平坦之氣化矽上， 並加以SEM觀察如圖1所示。接著，再將複晶矽沈積在上述 之〇3/TEOS(請注意其尚有底層PE TEOS),並 WSEM觀察， 其结果如圖2。請比較圖1與圖2(請注意圈1和圖2具有相 同之放大倍率）發現不僅複晶矽（位於圖中最上層）之表面 粗槠度增加，且其底下與TEOS之介面亦非常粗接。 經發現形成具有島狀结構之雙層氧化層除了上述之方 法外，尚适有下列數種。1.0 3/TEOS沈積在熱氧化層上。 2.03/TE0S沈積在TE0S成長之磷玻璃上。3.03/TE0S沈積 在以低壓或電漿輔肋化學氣相沈積法所形成之氮化物上。 上述這些方法皆可使該雙層氧化層之最上層TE0S氧化膜表 面具有島狀结構。同時，OrTEOS成長之最佳條件是溫度 在 3 0 0 - 5 0 0 t：,壓力為 2 0 0 - 7 6 0 T 〇 r r ,及 0 3 與 T E 0 S 之流量 比大於8 。又前述之TE0S成長之磷玻璃，其在下列成長條 件最具有明顯之表面粗糙效果；即壓力為3-16 Tor*r,功 率為300-900瓦（watt),及成長溫度為340-440Ό。 (實施例一） 將上述實驗發現结果運用在DRAM產品上，該DRAM元 -5 _ (請先閱讀背面之注意事項再填寫本頁) .裝· -5 _·線 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X 297公釐） A7 B7 經濟部中央標準局負工消費合作社印製 五 、發明説明 ( ) 1 1 件 之 剖 面 圈 如 圃 3 所 示 〇 該 製 程 之 主 要 步 驟 如 下 於 矽 1 I 基 底 1 上 完 成 堪 效 電 晶 體 (該場效電晶體包括閘極5 源 / 1 1 汲 極 6 等 )後再依序沈積- -磷玻璃PSG及 雙 層 粗 箱 氧 化 層 4 y>—Ν 1 I 請 1 | 〇 又 該 雙 曆 粗 m 氧 化 曆 4 係 採 用 前 述 之 形 成 方 法 % 即 先 形 先 閱 1 I 成 一 氧 化 物 做 為 底 餍 其 上 再 VX 0 3 /TE0S 法 形 成 氧 化 矽 而 讀 背 1 1 I 構 成 具 有 粗 描 表 面 之 雙 層 構 造 0 之 注 1 Ί 接 著 » 經 接 m (C on t a ct)光罩之照相顯影， 並蝕刻 上 意 事 項 1 述 之 雙 層 粗 描 氧 化 層 4 及 絕 緣 磨 PSG 而 形 成 電 容 器 電 極 之 再 填 1 寫 ά I 接 觸 圈 案 〇 再 於 整 個 晶 Η 表 面 VX CVD 方 法 沈 積 作 為 電 容 器 本 頁 第 1 電 極 之 複 晶 矽 及 作 為 介 電 質 層 之 氧 化 物 -氮化物- 氧 化 1 1 物 (0 X i d e -Ν it ride -0 X i d e ) 8 , 如圖3所 示 〇 如 刖 所 述 在 進 1 I 行 複 晶 矽 沈 積 之 前 9 皆 必 須 做 短 時 間 HF蝕 刻 » 如 此 容 易 將 1 1 雙 層 粗 描 氣 化 層 4 之 島 狀 结 構 吃 掉 » 故 可 再 增 加 複 晶 矽 沈 訂 | 積 « 刖 之 退 火 (A η η e a 1) 步 斑 > 以 密 化 (D e η si f y ) 雙 層 粗 檢 氧 1 I 化 層 4 並 藉 此 降 低 HF 之 蝕 刻 速 率 0 然 後 以 具 有 圈 寮 之 光 阻 1 1 做 為 蝕 刻 遮 罩 $ 將 未 被 光 阻 保 護 之 氧 化 物 -氮化物- 氣 化 物 1 | 8 及 複 晶 矽 蝕 刻 掉 » 以 形 成 各 假 記 憶 軍 元 之 電 容 器 第 1 電 I 極 7 0 該 第 1 電 棰 係 作 為 儲 存 m 荷 之 用 〇 1 1 之 後 » 再 沈 植 —· 複 晶 矽 並 經 蝕 刻 形 成 具 有 m % 之 電 容 1 | 器 之 第 2複晶矽霉極9 〇 再 沈 積 —- 絕 緣 層 10如 氧 化 物 等 做 ! I 為 電 性 隔 離 $ 及 烴 独 刻 未 被 光 阻 保 護 之 絕 緣 層 10及 PSG 以 1 1 形 成 位 元 線 接 觸 洞 (C on t a c t h 〇 1 e) 31 〇 然 後 沈 m 複 晶 矽 Η 1 | 做 為 記 懷 單 元 之 位 元 線 3 » 而 完 成 本 發 明 之 DRAM 结 構 〇 1 I 由 於 本 發 明 電 容 器 之 第 1 複 晶 矽 霉 極 7 係 形 成 在 雙 層 1 1 -6 1 1 1 1 本紙張尺適用中國國家揉準（CNS ) A4規格（210X297公釐） B7五、發明説明（） 粗槠氧化層4上，請參閲圈3左邊之微観圖，其中顯示粗槠 為 大 最 度 0 粗 該 费 面 表 之 凸 凹 常 非 有 具 4 層 化 氧 左 埃 右 第 該 此 因 極 電 矽 晶 複 凹。存 常棟儲 非面息 到觸信 得接高 此效提 藉有 可之 亦層 ?質 電 介 與 其 加 增 而 進 可 亦 Μ 容 電息 存信 並儲取 面之讀 表AM和 和 到 得， 下下 度 靠同 可相 之知 習 以明 ，發 加本 增且 而而 因 〇 之 明 發 本 合 適 f 制 控 於 易 之發 格本 規又 同。 相高 在提 故可 ，更業 值度產 容密具 電集極 之積產 1量 之DR度積件單専 平明定面條簡請 不發穗片值程申 凸本之晶容製法 少電明依 更 有 佔 在 可 值 價 用 利 上 爰 利 (請先閱讀背面之注意事項再填寫本頁) •裝· 訂 經濟部4-央標隼局員工消費合作;ip製 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0灸297公釐）The present invention can be useful in the following experiments. That is, using 〇3 / teo S deposited on PECVD (plasma sugar-assisted chemical vapor deposition) grown silicon oxide, where 03/1 day 05 represents 03 gas and "1 ^ 361 ^ £ ^ YA with 18116 5 丨 ( 0 (： 21 ^) 4 (abbreviated as TEOS) The silicon oxide film produced by mixing and decomposing the volatile gas of the caustic solution (hereinafter referred to as 03 / TE0S, or TEOS refers to the silicon oxide formed by this method) The film is then kicked on the PE -r-4-paper ruler with the SEM friend APM. The degree is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) 1 Threading (please read the precautions on the back before filling this page ) A7 B7 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention () Surface roughness of 03 / TE0S on TEOS. It was found that 〇3 / TEOS will form an island structure at the early stage of growth. Therefore If the polycrystalline silicon electrode of the capacitor can be deposited on the island-like structure of 〇3 / TEOS, the polycrystalline sand film will grow along the island-like structure, making the surface roughness of the polycrystalline silicon film large Increase, which means to get a very uneven surface, so it can greatly increase the existence of polycrystalline silicon and dielectric layer Contact area. In order to add M verification, we grow polycrystalline silicon on flat vaporized silicon and observe it with SEM as shown in Figure 1. Then, deposit polycrystalline silicon on the above-mentioned 〇3 / TEOS (please note It still has the bottom layer PE TEOS), and WSEM observation, the results are shown in Figure 2. Please compare Figure 1 and Figure 2 (please note that circle 1 and Figure 2 have the same magnification) found that not only polycrystalline silicon (located in the uppermost layer of the figure ) The surface roughness is increased, and the underlying interface with TEOS is also very coarse. It has been found that in addition to the above methods, the formation of a double-layer oxide layer with an island structure is still suitable for the following types. 1.0 3 / TEOS deposition On the thermal oxide layer. 2.03 / TE0S is deposited on the phosphorous glass grown by TE0S. 3.03 / TE0S is deposited on the nitride formed by low pressure or plasma assisted rib chemical vapor deposition. All of the above methods can make the double The top layer of the TEOS oxide film on the oxide layer has an island-like structure. At the same time, the best condition for OrTEOS growth is a temperature of 3 0 0-5 0 0 t :, a pressure of 2 0 0-7 6 0 T 〇rr, and The flow ratio of 0 3 to TE 0 S is greater than 8. Furthermore, the aforementioned TEOS-grown phosphor glass It has the most obvious surface roughness effect under the following growth conditions; namely, the pressure is 3-16 Tor * r, the power is 300-900 watts (watt), and the growth temperature is 340-440Ό. (Example 1) The above experiment found The result is applied to the DRAM product, the DRAM yuan -5 _ (please read the precautions on the back before filling in this page). Installation · -5 _ · The size of the line paper is applicable to China National Standard (CNS) A4 specification (210X 297 Mm) A7 B7 Printed by the National Bureau of Standards, Ministry of Economic Affairs, Consumer Labor Cooperative V. Description of the invention () 11 The profile circle of 1 piece is shown in the garden 3. The main steps of the process are as follows: on the silicon 1 I substrate 1 Transistor (the field effect transistor includes gate 5 source / 1 1 drain 6 etc.) and then deposited in sequence--Phosphorus glass PSG and double-layer rough box oxide layer 4 y > —Ν 1 I Please 1 | 〇 又The dual-calcium oxide m4 is based on the formation method described above, that is, the first form is read first, 1 is formed as an oxide, and then VX 0 3 / TE0S method is used to form silicon oxide. The back 1 1 I constitutes a double-layer structure with a rough drawing surface. Note 1 Ί Next »Photographic development of a m (C on ta ct) photomask and etching of the double-layer rough drawing oxide layer 4 as described in item 1 And insulating the PSG to form the capacitor electrode and then fill it. 1 Write the contact ring case. Then deposit the polycrystalline silicon as the first electrode of the capacitor on this page and the oxide as the dielectric layer by VX CVD on the entire surface of the crystal. Nitride-Oxide 1 1 (0 X ide -Ν it ride -0 X ide) 8, as shown in FIG. 3 〇Before the I 1 polycrystalline silicon deposition is performed as described in 9 »It is so easy to eat up the island-like structure of the 1 1 double-layer coarse-grained gasification layer 4» Therefore, it is possible to add polycrystalline silicon deposition | Product «刖 的 annealing (A η η ea 1) Steps > to densify (D e η si fy) double-layer coarse oxygen detection layer 1 I 4 to reduce the etching rate of HF 0 and then The photoresist with a circle of laps 1 1 is used as an etching mask. The oxide-nitride-vapor 1 that is not protected by the photoresist 1 | 8 and the polycrystalline silicon are etched away »to form the first capacitor of each dummy memory army. Electric I pole 7 0 The first electric pole is used for storing m charge. After the re-implantation-polysilicon and etched to form a capacitor with m% 1 | the second polysilicon pole of the device 9 〇Re-deposition—the insulating layer 10 is made of oxide and so on! I is the electrical isolation $ and the hydrocarbon alone carved the insulating layer 10 and PSG which are not protected by the photoresist to form a bit line contact hole (C on tacth 〇) with 1 1 1 e) 31 〇Then the polycrystalline silicon Η 1 | as the memory cell bit line 3 »and complete the DRAM structure of the present invention 〇1 I because the capacitor of the present invention is the first polycrystalline silicon 7 electrode formed In the double-layer 1 1 -6 1 1 1 1 paper ruler is suitable for China National Standard (CNS) A4 specification (210X297mm) B7 Fifth, the description of the invention () On the rough oxide layer 4, please refer to the micro-image on the left side of circle 3, which shows that the rough cast is large and the maximum is 0. The roughness of the surface of the surface often does not have 4 layers of oxygen left The right side of the silicon should be concave due to the extremely electric silicon crystal. Cun Changdong stores non-existent information to the contact level, and this effect can be improved. Is it possible to use the same layer? The quality of the dielectric and its increase can be advanced. It can also store information and store the reading AM and He to the surface. Obtained, the next degree is based on the knowledge and practice of the same phase, and the cost is increased and the cost is increased due to the fact that the clear version is suitable for f control and control. It ’s better to mention the reason, and it ’s more worthwhile to produce the product with the capacity of the electric collector. The volume of the product is 1 unit of DR. The single piece of flat noodles is simple. Please do n’t send the wafer. Mingyi is even more valuable in value-for-money (please read the notes on the back before filling out this page) • Binding · Order 4-Ministry of Economic Affairs, the consumer cooperation of the Central Falcon Bureau; the paper size of the ip system is suitable for Chinese countries Standard (CNS) A4 specification (297mm for 2 ~ 0 moxibustion)