TW301022B - - Google Patents

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Publication number
TW301022B
TW301022B TW085102096A TW85102096A TW301022B TW 301022 B TW301022 B TW 301022B TW 085102096 A TW085102096 A TW 085102096A TW 85102096 A TW85102096 A TW 85102096A TW 301022 B TW301022 B TW 301022B
Authority
TW
Taiwan
Prior art keywords
substrate
insulating layer
layer
transition metal
patent application
Prior art date
Application number
TW085102096A
Other languages
English (en)
Chinese (zh)
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW301022B publication Critical patent/TW301022B/zh

Links

Classifications

    • H10W10/00—
    • H10W10/01—
    • H10W10/0148—
    • H10W10/018—
    • H10W10/10—
    • H10W10/17—

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
TW085102096A 1995-02-24 1996-02-24 TW301022B (OSRAM)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950003727A KR100190367B1 (ko) 1995-02-24 1995-02-24 소자분리막형성방법

Publications (1)

Publication Number Publication Date
TW301022B true TW301022B (OSRAM) 1997-03-21

Family

ID=19408771

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085102096A TW301022B (OSRAM) 1995-02-24 1996-02-24

Country Status (5)

Country Link
US (1) US5668043A (OSRAM)
JP (1) JP2788889B2 (OSRAM)
KR (1) KR100190367B1 (OSRAM)
CN (1) CN1048821C (OSRAM)
TW (1) TW301022B (OSRAM)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW365047B (en) * 1996-10-04 1999-07-21 Winbond Electronics Corp Manufacturing method for simultaneously forming trenches of different depths
US6686283B1 (en) * 1999-02-05 2004-02-03 Texas Instruments Incorporated Shallow trench isolation planarization using self aligned isotropic etch
US6306723B1 (en) 2000-03-13 2001-10-23 Chartered Semiconductor Manufacturing Ltd. Method to form shallow trench isolations without a chemical mechanical polish
CN110223916B (zh) * 2019-05-06 2022-03-08 瑞声科技(新加坡)有限公司 一种硅晶片的加工方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5766627A (en) * 1980-10-13 1982-04-22 Toshiba Corp Manufacture of semiconductor device
JPS5893220A (ja) * 1981-11-30 1983-06-02 Toshiba Corp 半導体単結晶膜の製造方法
JPH01321629A (ja) * 1988-06-23 1989-12-27 Nec Corp 薄膜形成方法
US5256591A (en) * 1991-01-07 1993-10-26 Gold Star Electron Co., Ltd. Method for forming isolation region in semiconductor device using trench

Also Published As

Publication number Publication date
JPH08264634A (ja) 1996-10-11
CN1134038A (zh) 1996-10-23
JP2788889B2 (ja) 1998-08-20
KR100190367B1 (ko) 1999-06-01
US5668043A (en) 1997-09-16
KR960032673A (ko) 1996-09-17
CN1048821C (zh) 2000-01-26

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