經濟部中央標準局員工消費合作社印聚 A7 B7 五、發明説明（l ) --- 本發明是有關於-種半導趙製程，且特別是有關於 一種可提供高蝕刻選擇比的自對準接觸結構…^· aligned contact; SAC)，以及應用此結構之自對準接觸製 程。 在提高積體電路的包裝密度和減少晶片尺寸的不 斷努力中，不同圖案層之間的對準誤差是主要的障礙所 在，因此便有許多自我對準（self_aHgned)的結構被提出 來，用以縮減元件之間的距離，增加元件的密集度。例 如自我對準接觸窗的結構，可允許接觸窗與閘極的重 疊，因此提高了元件的密集度，並提供了適當的保護以 防短路。 所謂的”自我對準”，是利用設計中既定的幾何結 構，作為次一製程步驟中意欲形成結構的遮蔽或窗口， 能夠使元件的各組成部份不偏不倚地建構在適當的位 置。在自我對準接觸窗的製程中，藉由場效電晶體上源 極或波極的接觸窗可和相鄰的閘極重疊·，來提供對失去 對準較大的容忍度。這樣的重疊是可允許的，因為自我 對準接觸點是以一種在接觸窗與閘極間提供額外絕緣 的方法所形成，以致可防止短路。 一般用於自對準接觸的結構通常有兩種，以下將配 合第1圖與第2圖分別作一介紹。 首先請參照第1圊，其繪示習知一種自我對準接觸 結構的剖面圖’在一半導體基底1〇上具有一電晶體2〇， 並有一淺溝槽隔離（或場氧化層）12，將此電晶體與其他 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公赛） : 參------、1τ------ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局貝工消費合作杜印製 A7 B7 五、發明説明（2 ) 元件隔離。為簡化圖示’在圖中僅繪出此電晶體之閘極 14 ’例如是由一層複晶矽與一層矽化金屬（如WSi2)所共 同組成的複晶石夕化金屬（polycide)。此種結構是使用以氧 化梦為材質的硬式罩幕16 (hardmask)與側壁層18 (spacer)將閘極14包覆，然後再形成以氮化矽為材質的 襯塾層22 (liner layer)覆蓋在前述結構的表面上。在後 序的SAC製程中，即是利用此襯墊層22作為一蝕刻阻 絕層（etching-stop layer)來保護其下的氧化矽罩幕μ、 氧化矽側壁層18 、及淺溝槽隔離12 (shall〇w trench isolation; STI)。 請繼續參照第1圖，形成襯塾層22之後，再沈積一 層絕緣層24，通常為氧化矽層，並上光阻26，露出指 定要作接觸導接的區域，以進行絕緣層24的钮刻。以此 種結構來進行自我對準接觸（SAC)的蝕刻時，雖然材質 為氮化矽的襯墊層22提供了一個適當的蝕刻阻絕效 果，但是一旦襯墊層22邊角（c〇rner)較薄的部份不幸被 蝕刻穿透的話，底下的氧化矽罩幕16和氧化矽側壁層 18也會跟著遭到蝕刻，再加上未來電晶體之間隙持續縮 小，一般此襯墊層的厚度都不會製作得太厚，更增加了 氧化矽罩幕/側壁層受到触刻攻擊的機會。 請參照第2圖，其繪示習知另一種自我對準接觸結 構的剖面圖。為方面起見，在本圖中與第i圖相同的元 件，則沿用第1圖之標號。如第2圖所示，此種自對準 接觸的結構是使用以氮化矽為材質的罩幕36和側壁 . I------、1T-----„--λ (請先閱讀背面之注意事項再填寫本頁) 3 經濟部中央標準局員工消費合作社印聚 A7 B7 五、發明説明（3 ) 38，同時配合氮化矽襯墊層22來保護底下的STI 12。 這種結構的優點是：即使襯墊層22在SAC的蝕刻過程 中不幸地被穿透，底下的氮化矽罩幕/側壁層36/38也可 作為蝕刻終止的材料，因此不會有前段所述之問題。然 而此種結構也有它的缺點：在稍後要去除氮化矽襯墊層 22，露出接觸區的步驟中，由於罩幕層36與側壁層38 的材質也是氮化石夕，因此也會一併受到姓刻攻擊，其結 果是增加閘極與接觸金屬發生短路的機率。 有鑑於此，本發明的目的就是提供一種具有高度蝕 刻選擇比的自對準接觸結構，以及應用此結構的自對準 接觸製程，以避免在SAC蝕刻或去除襯墊層的過程中， 破壞了閘極的罩幕層或側壁層。 根據上述目的，本發明提供一種自對準接觸結構， 包括：一電晶體，設置於一半導體基底上，且此電晶體 具有一閘極及一源極/汲極區；一罩幕層及一側壁層，分 別設置於該閘極之上方及侧邊；一氮化矽襯墊層，設置 於上述罩幕層及側壁層上方，並延伸至源極/汲極區；以 及一絕緣層，設置於上述結構之上方。而本發明的特徵 在於：使用氮氧化矽（oxy-nitirde ; SiON)材質來作為閘 極的罩幕層與側壁層。 本發明之SiON罩幕層/側壁層結構，不但在主要的 SAC蝕刻步驟擁有良好的蝕刻比，並且在去除氮化矽襯 墊層的步驟時，也不易遭到蝕刻破壞。這表示： 第一、在SAC的氧化矽蝕刻步驟中，SiON對Si02 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 訂 ； (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作杜印聚 A7 B7 五、發明説明（4 ) ' 具有高度的姓刻選擇比； 第一在襯塾層的去除步驟中，S刪對也達 到良好的蝕刻選擇比。 在SAC主要的蚀刻步驟中，依習知的方法使用 C4F8/CH3F作為㈣源’即可達到高度的餘刻選擇比； 至於在襯塾層的㈣步射，本案之發明人則發現利用 ch3f/o2^刻氣體，可以使3_對8邮達到良好的 蝕刻選擇比，來避免si0N罩幕層/側壁層的損失。 因此，本發明更提供一種應用上述結構的自對準接 觸製程’包括下列步称：（a)提供—半導體基底，其上具 有-電晶體’包括極、及源極/没極區，且在閘極的上 方與側邊分別形成有材質為氮氧化矽之罩幕層與側壁 層；（b)形成一材質為氮化矽之襯墊層；（c)形成一絕緣 層，（d)疋義絕緣層，以形成一開口而露出部份之襯墊 層，以及（f)去除露出之襯墊層，以露出源極/汲極區之一 當作接觸區。其中在步驟⑴使用CH3F/〇2的蝕刻氣體， 可使SiON對Si：jN4的蚀刻比達到約2 : 5。 為讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式， 作詳細說明如下： 圖式之簡單說明： 第1圖繪示習知一種自對準接觸結構的剖面圖。 第2囷繪示習知另一種自對準接觸結構的剖面圖。 第3圓繪示本發明之自對準接觸結構的剖面囷。 本紙張尺度適用中國國家標牟（CNS)六4規格（2丨0><297公釐） -----^-----I------、?τ------J (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印聚 Μ Β7 五、發明説明（5 ) 符號說明： 10、5 0〜矽基底；20、60〜電晶體；14、54〜 閘極；53〜閘氧化層；59A/59B〜源極/汲極區； 57A/57B〜輕摻雜源極/汲極區；12、52〜場氧化層（淺 溝槽隔離）；24、64〜絕緣層；22、62〜襯墊層；26、 66〜光阻層；67〜開口； 16/18〜氧化矽罩幕/側壁層； 36/38〜氮化矽罩幕/侧壁層；56/58〜氮氧化矽罩幕/側壁 層。 實施例 本發明之實施例將配合第3圖作一詳細說明如下。 本發明之自對準接觸結構是形成在一半導體基底50 上，而在基底上具有一傳統電晶體60，包括閘極氧化層 53，閘極54，例如是一複晶石夕化金屬（polycide)，輕摻 雜源極/汲極區57A ' 57B，以及源極/汲極區59A、 59B。基底上有一場氧化層或淺溝槽隔離52將此電晶體 與其他元件隔離。 請繼續參照第3圖，在閘極54之上方及側邊分別設 置有SiON罩幕層56及SiON側壁層58。之後，並有一 氮化矽襯墊層62，設置於SiON罩幕層/側壁層56/58上 方，其延伸至源極/汲極區59A、59B以及淺溝槽隔離 52的上表面，以作為SAC蝕刻時的阻絕層。另外，此自 對準接觸結構更包括一絕緣層64，通常為氧化矽層，覆 蓋在前述結構的上方。 本發明之自對準接觸製程，是在完成上述結構後， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------种衣------ΐτ----------A (請先閱讀背面之注意事項再填寫本頁) 經濟部中央橾準局貝工消費合作社印製 A7 ____B7 五、發明説明（6) 先利用微影技術，將一光阻層66在預定形成接觸導接區 域的上方定義出一開口 67，然後沿此開口 67作非等向 性的蝕刻，直到露出襯墊層62的表面為止。此步驟為 SAC主要的蝕刻步驟，其蝕刻氣體對Si〇2的蝕刻速率必 須遠大於對Si3N4與SiON的蝕刻速率，例如可使用 C4F8/CHF3/Ar的混合氣體，當其流量比為c4F8 : CHF3 : Ar=ll : 6 : 50,其蝕刻速率分別為 SiO2=7000A/min ; Si3N4=80〇A/min ; SiON=65〇A/min。由於 SiON 的钱刻 速率甚至比ShN4更慢，因此即使當襯墊層62在過程中 不幸被蝕刻穿透，以SiON為材質的罩幕層/側壁層56/58 也不會被蝕刻破壞。 接下來的步驟，是去除露出的襯塾層，以將作為接 觸區的59B裸露出《在習知的自對準接觸結構中，由於 罩幕層/側壁層與襯墊層的材質都為氮化矽，因此無法作 選擇性的蝕刻’然而本發明所用的氮氧化矽材質，則可 利用CHsF/ 〇2的蝕刻氣體來達到選擇性蝕刻的目的。例 如當流量比為 CH3F : 〇2: Ar=18 : 5 : 50 時，Si3N4 的钮刻速率為1940A /min，而SiON的餘刻速率則只有 800A/min »因此利用此結構在去除shN4襯墊層的步驟 中’可以減少罩幕層與侧壁層因蝕刻所造成的損失，避 免了短路發生的機會。之後的製程更包括：去光阻，以 及形成一導電層填入窗口，藉此與接觸區59B形成電性 連接。 综上所述’本發明之自對準接觸結構具有以下的優 本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐） ϋ—' nn —^1· I 1· n I 士1^1 nn In HI tl^i \ J (請先閲讀背面之注意事項再填寫本頁) A? —_______ B7_ 五、發明説明（7 ) 點： 1_在SAC主要的蝕刻步驟中，由於si〇N對8丨〇2具 有高蝕刻選擇比，因此本發明的Si〇N結構並不會被蝕 刻所破壞，優於習知的Si〇2罩幕/側壁層結構。 2. 在去除襯墊層的步驟中，由於Si〇N的蝕刻速率只 有Si#4的2/5，因此可降低罩幕/側壁層因蝕刻所造成 的損失，優於另一種習知的SUN*罩幕/侧壁層結構。 3. 综合以上兩點，經由本發明之自對準接觸結構， 可以降低閘極與接觸金屬發生短路的機會。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明 之精神和範圍内’當可作各種之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為 準。 1^------,1T------% (請先閱讀背面之注意事項再填寫本頁) 經濟部中央梂準局貝工消費合作社印裝 8 本紙張尺度適用中國國家標準（CNS > Α4規格（2Ι0Χ297公釐）The Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, A7, B7, and V5. Invention Description (l) --- This invention is about a kind of semi-conducting Zhao process, and in particular it is about a self-alignment that can provide a high etching selection ratio Contact structure ... ^ · aligned contact; SAC), and self-aligned contact process using this structure. In the continuous efforts to improve the packaging density of integrated circuits and reduce the size of wafers, the alignment error between different pattern layers is the main obstacle. Therefore, many self_aHgned structures have been proposed for Reduce the distance between components and increase the density of the components. For example, the structure of a self-aligned contact window allows the contact window to overlap with the gate, thereby increasing the density of the components and providing appropriate protection against short circuits. The so-called "self-alignment" is to use the established geometric structure in the design as a mask or window intended to form a structure in the next process step, so that each component of the component can be constructed in an appropriate position without bias. In the process of self-aligning contact windows, the source or wave contact window on the field effect transistor can overlap with the adjacent gate to provide greater tolerance for misalignment. Such overlap is permissible because the self-aligned contacts are formed in a way that provides additional insulation between the contact window and the gate so that short circuits are prevented. There are generally two types of structures used for self-aligned contact. The following descriptions are given in conjunction with Figure 1 and Figure 2. First, please refer to Section 1), which shows a cross-sectional view of a conventional self-aligned contact structure. 'It has a transistor 20 on a semiconductor substrate 10 and a shallow trench isolation (or field oxide layer) 12, Apply this transistor and other paper sizes to the Chinese National Standard (CNS) Α4 specification (210X 297 race): See ------, 1τ ------ (Please read the notes on the back before filling (This page) Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of Invention (2) Isolation of components. In order to simplify the illustration, only the gate 14 of this transistor is drawn in the figure, for example, a polycide composed of a layer of polycrystalline silicon and a layer of silicide metal (such as WSi2). In this structure, the gate 14 is covered with a hard mask 16 and a spacer 18 made of an oxide dream, and then a liner layer 22 made of silicon nitride is formed. Covering the surface of the aforementioned structure. In the subsequent SAC process, the liner layer 22 is used as an etching-stop layer to protect the underlying silicon oxide mask μ, the silicon oxide sidewall layer 18, and the shallow trench isolation 12 (shall〇w trench isolation; STI). Please continue to refer to Figure 1. After forming the lining layer 22, a layer of insulating layer 24, usually a silicon oxide layer, is deposited, and a photoresist 26 is exposed to expose the area designated for contact and conduction for the button of the insulating layer 24. engraved. When performing self-aligned contact (SAC) etching with this structure, although the liner layer 22 made of silicon nitride provides an appropriate etching stop effect, once the liner layer 22 corners (corner) If the thinner part is unfortunately penetrated by etching, the underlying silicon oxide mask 16 and silicon oxide sidewall layer 18 will also be etched. In addition, the gap between the transistors will continue to shrink in the future. Generally, the thickness of this liner layer They will not be made too thick, which increases the chance of the silicon oxide mask / sidewall layer being touched. Please refer to FIG. 2, which is a cross-sectional view showing another conventional self-aligned contact structure. For the sake of brevity, in this figure, the same components as those in figure i will use the reference numerals in figure 1. As shown in Figure 2, this self-aligned contact structure uses a mask 36 and sidewalls made of silicon nitride. I ------, 1T ----- „-λ (Please (Please read the notes on the back before filling this page.) 3 The Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs printed A7 B7. 5. Description of the invention (3) 38. At the same time, the silicon nitride liner 22 is used to protect the STI 12 underneath. The advantage of this structure is that even if the liner layer 22 is unfortunately penetrated during the SAC etching process, the underlying silicon nitride mask / sidewall layer 36/38 can be used as the material for the termination of the etching, so there will be no previous paragraph However, this structure also has its disadvantages: in the step of removing the silicon nitride liner layer 22 later to expose the contact area, since the material of the mask layer 36 and the sidewall layer 38 is also nitride stone, therefore It will also be attacked by the surname, which will increase the probability of a short circuit between the gate and the contact metal. In view of this, the object of the present invention is to provide a self-aligned contact structure with a high etching selectivity, and to apply the structure Self-aligned contact process to avoid etching or removing liners in SAC In the process of the cushion layer, the cover layer or the side wall layer of the gate electrode is damaged. According to the foregoing object, the present invention provides a self-aligned contact structure including: a transistor disposed on a semiconductor substrate, and the transistor has A gate and a source / drain region; a mask layer and a side wall layer respectively disposed above and on the side of the gate; a silicon nitride liner layer disposed on the mask layer and the sidewall layer Above, and extends to the source / drain region; and an insulating layer is disposed above the above structure. The invention is characterized in that it uses oxy-nitirde (SiON) material as the cover of the gate Layer and side wall layer. The SiON mask layer / side wall layer structure of the present invention not only has a good etching ratio in the main SAC etching step, but also is not easily damaged by etching during the step of removing the silicon nitride liner layer. This means: First, in the silicon oxide etching step of SAC, SiON applies the Chinese National Standard (CNS) A4 specification (210X297 mm) to the paper size of Si02; (Please read the precautions on the back before filling this page) Ministry of Economy Standard Bureau Shellfisher Consumer Cooperation Du Yinju A7 B7 V. Description of the Invention (4) 'Has a high selection ratio of surname and engraving; First, in the step of removing the liner layer, the S deletion pair also achieves a good etching selection ratio. In the main etching step of SAC, a conventional method using C4F8 / CH3F as a radon source can achieve a high remaining selection ratio. As for the step shot in the liner layer, the inventor of this case has found that using ch3f / o2 The engraving gas can achieve a good etching selection ratio of 3 to 8 posts to avoid the loss of the si0N mask layer / side wall layer. Therefore, the present invention further provides a self-aligned contact process using the above structure, including the following steps: Weigh: (a) Provide-a semiconductor substrate with -transistors' including electrodes, and source / non-electrode regions, and a mask layer made of silicon oxynitride is formed above and on the sides of the gate, respectively. Sidewall layer; (b) forming a liner layer made of silicon nitride; (c) forming an insulating layer, (d) defining an insulating layer to form an opening and exposing a portion of the liner layer, and (f ) Remove the exposed liner to expose one of the source / drain regions Make contact zone. Wherein, an etching gas of CH3F / 〇2 is used in step (2), so that the etching ratio of SiON to Si: jN4 can reach about 2: 5. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 A cross-sectional view of a conventional self-aligned contact structure is shown. Section 2 shows a cross-sectional view of another conventional self-aligned contact structure. The third circle shows a cross section 囷 of the self-aligned contact structure of the present invention. This paper size is applicable to China National Standards (CNS) 6-4 specifications (2 丨 0 > < 297 mm) ----- ^ ----- I ------,? Τ ---- --J (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Β7 V. Description of the invention (5) Symbol description: 10, 50 0 to silicon substrate; 20, 60 to Transistor; 14, 54 ~ gate; 53 ~ gate oxide; 59A / 59B ~ source / drain region; 57A / 57B ~ lightly doped source / drain region; 12, 52 ~ field oxide layer (shallow Trench isolation); 24, 64 ~ insulation layer; 22, 62 ~ pad layer; 26, 66 ~ photoresist layer; 67 ~ opening; 16/18 ~ silicon oxide mask / sidewall layer; 36/38 ~ nitride Silicon mask / sidewall layer; 56/58 ~ silicon oxide mask / sidewall layer. EXAMPLES Examples of the present invention will be described in detail with reference to FIG. 3 as follows. The self-aligned contact structure of the present invention is formed on a semiconductor substrate 50, and has a conventional transistor 60 on the substrate, including a gate oxide layer 53, and a gate 54, such as a polycide ), Lightly doped source / drain regions 57A ′ 57B, and source / drain regions 59A, 59B. An oxide layer or shallow trench isolation 52 on the substrate isolates this transistor from other components. Continuing to refer to FIG. 3, a SiON mask layer 56 and a SiON sidewall layer 58 are provided above and to the sides of the gate 54, respectively. After that, a silicon nitride liner layer 62 is disposed above the SiON mask layer / sidewall layer 56/58, which extends to the upper surfaces of the source / drain regions 59A, 59B and the shallow trench isolation 52 as the Barrier layer during SAC etching. In addition, the self-aligned contact structure further includes an insulating layer 64, usually a silicon oxide layer, overlying the aforementioned structure. In the self-aligned contact process of the present invention, after the above structure is completed, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) --------- seed coat -------- ΐτ ---------- A (Please read the precautions on the back before filling out this page) Printed by A7 __B7 by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (6) Use of lithography first In the technology, an opening 67 is defined on a photoresist layer 66 above a predetermined contact formation area, and then anisotropic etching is performed along this opening 67 until the surface of the pad layer 62 is exposed. This step is the main etching step of SAC. The etching rate of SiO2 by the etching gas must be much higher than that of Si3N4 and SiON. For example, a mixed gas of C4F8 / CHF3 / Ar can be used. When the flow rate is c4F8: CHF3 : Ar = ll: 6: 50, the etching rates of which are SiO2 = 7000A / min; Si3N4 = 80 ° A / min; SiON = 65 ° A / min. Since the engraving rate of SiON is even slower than ShN4, even when the liner layer 62 is unfortunately etched through in the process, the mask layer / sidewall layer 56/58 made of SiON will not be damaged by etching. The next step is to remove the exposed liner layer to expose 59B as the contact area. "In the conventional self-aligned contact structure, since the material of the cover layer / sidewall layer and the cushion layer is nitrogen, Silicon can not be used for selective etching. However, the silicon oxynitride material used in the present invention can use the etching gas of CHsF / 02 to achieve the purpose of selective etching. For example, when the flow ratio is CH3F: 〇2: Ar = 18: 5: 50, the button rate of Si3N4 is 1940A / min, and the remaining rate of SiON is only 800A / min. »So using this structure to remove the shN4 liner In the step of layering, the loss caused by the mask layer and the sidewall layer due to etching can be reduced, and the chance of short circuit occurrence can be avoided. The subsequent process further includes: removing photoresist, and forming a conductive layer to fill the window, thereby forming an electrical connection with the contact region 59B. To sum up, the self-aligned contact structure of the present invention has the following excellent paper sizes: Applicable to China National Standard (CNS) A4 (210X297 mm) ϋ— 'nn — ^ 1 · I 1 · n I 士 1 ^ 1 nn In HI tl ^ i \ J (Please read the precautions on the back before filling this page) A? —_______ B7_ 5. Description of the invention (7) Points: 1_ In the main etching step of SAC, due to si〇 N pair 8 〇 02 has a high etching selection ratio, so the SiON structure of the present invention is not damaged by etching, which is better than the conventional Si02 mask / sidewall layer structure. 2. In the step of removing the liner layer, since the etching rate of SiON is only 2/5 of that of Si # 4, it can reduce the loss caused by the etching of the mask / sidewall layer, which is better than the other conventional SUN * Curtain / sidewall structure. 3. Based on the above two points, the self-aligned contact structure of the present invention can reduce the chance of a short circuit between the gate and the contact metal. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 1 ^ ------, 1T ------% (Please read the notes on the back before filling out this page) Printed by the Central Laboratories Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives 8 This paper size applies to Chinese national standards (CNS > Α4 size (2Ι0 × 297 mm)