A7 B7 432507 i〇4；ilwr.d〇c/CK)6 i、發明説明（/ ) 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種利用緩衝層的形成，以防止閘極結構之金屬 矽化物產生剝離之閘極結構的製造方法。 夾著高熔點、穩定性及低電阻率等優點，金屬矽化物 .(MetalSiUcide)於積體電路製程上的應用，已愈來愈普遍。 而在線寬、接觸面積及接面深度等逐漸縮小的深次微米積 體電路的技術中，爲了能有效地提高元件的工作品質，降 低電阻並減少電阻及電容（RC)所造成的信號傳遞延遲，在 習知的複晶矽閘極上或源極/汲極區之接面處會再形成一 層金屬矽化物，以達到降低閘極電阻、接面電阻，進而達 到提高整個元件的驅動電流，反應時間或電路的操作速度 之目的。 第1A圖係繪示習知一種將金屬矽化物應用於閘極之 製作的半導體元件的剖面圖。請參照第1A圖，典型的金屬 矽化物層110係形成於複晶矽層106的表面之上，但是， 爲了避免金屬矽化物層110與複晶矽層106產生交互擴 散，習知通常會在形成金屬矽化物層110之前先在基底100 上形成一層阻障層（Barrier Layer)l08。而爲了避免在定義前 述各沉積層的過程中，由於沉積層之反射現象在後續的微 影程序中所造成的干擾，典型的作法則會在金屬矽化物層 110之上再覆蓋一層抗反射層（Anti-Reflection Coating， ARC)116，以減少反射的現象。 此外，在抗反射層116的表面上，以及所形成之閘極 的主體結構120的側壁上，通常會形成一層氮化矽材質之 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂· 經濟部智慧財產局員工消費合作社印黎 43250? 5〇4.>ΐ\νΓ.ίΙοο'Ι){)6 ^ _ Β7 五、發明説明（ι) (請先閲讀背面之注意事項再填寫本頁) 頂蓋層（Cap layer)l 18與間隙壁（Spacer)130，以在後續自動 對準接觸窗開口（Self-aligned Contact Opening) 134 的鈾刻製 程中保護閘極之主體結構120，使其不遭受蝕刻的破壞。 由於氮化矽材質容易造成應力的累積，因此習知的方 .法通常會在間隙壁130與閘極之主體結構120之間增加一 層氧化矽緩衝層122，以減緩間隙壁130之應力。但是，閘 極之主體結構ί20中的頂蓋層118,其所累積的應力則無法 藉由其下方的抗反射層116減少，因而導致所形成之金屬 石夕化物層110發生剝離（Peeling)的現象。 -線. 經濟部智慧財產局員工消費合作社印製 此外，請參照第1B圖，上述之閘極之主體結構120， 在形成接觸窗開口 136與138的過程中，因爲接觸窗136 係裸露出金屬矽化物層110,而接觸窗開口 138則是必須裸 露出基底100的源極/汲極區124，其二者所需蝕刻的深度 並不一致。當深度較淺的接觸窗開口 136形成之後，整個 蝕刻製程並未終止，而必須進行鈾刻介電層132之製程， 以形成深度較深的接觸窗開口 138。但是，當接觸窗開口 136形成之後，即裸露出金屬矽化物層110，因此在後續蝕 刻介電層132以形成接觸窗開口 138的製程中，金屬矽化 物層1丨0亦暴露於蝕刻的環境之下，所以容易造成金屬矽 化物層110的損失，而使整個閘極之主體結構120的阻値 上升，元件的執行效能（Performance)下降。 因此，本發明提出一種閘極結構，包括一閘極氧化層、 一複晶砍層、一金屬砂化物層、一緩衝層（Buffer Layer)以 及一頂蓋層，其中閘極氧化層係覆蓋於基底之上，複晶矽 4 本紙張尺度適用中國國家標準（CNS ) A4規格（2I0X297公釐） 432507 a 7 5043l\vr.doc/006 B7 五、發明説明（2) 層係配置於閘極氧化層上，並且介於金屬矽化物與閘極氧 化層之間，緩衝層係配置於金屬矽化物上，並且介於金屬 矽化物層與頂蓋層之間。 依照本發明實施例所述，上述之閘極結構更包括一第 .一阻障層、一第二阻障層與一抗反射層，其中第一組障層 係配置於複晶矽層與金屬矽化物層之間；第二阻障層係配 置於金屬矽化物層與緩衝層之間；抗反射餍係配置於緩衝 層與頂蓋層之間。 本發明在頂蓋層與金屬矽化物層之間增加一層類似於 複晶矽材質之緩衝層，其可以減緩頂蓋層的應力，並且在 後續形成接觸窗開口的過程中避免金屬矽化物層產生剝離 的現象。 本發明之閘極係具有金屬矽化物者，因此，可以降低 閘極的阻値，以提昇元件之執行效能。 本發明提供一種半導體元件的製造法，此方法係於基 底上形成閘極氧化層與第一層複晶砂層之後，在第一層複 晶矽層上再形成一金屬矽化物層，之後在金屬矽化物層上 形成第二層複晶矽層，再於第二複晶矽層上形成一層頂蓋 層。接著，定義頂蓋層、第二複晶矽層、金屬矽化物層、 第一複晶砂層與閘極氧化層之圖案，以形成一閘極之主體 結構，其後在閘極之主體結構的側壁形成一層緩衝層與間 隙壁，並在基底形成一源極/汲極區，然後，在基底上形成 一層介電層，並定義介電層，以在介電層中形成裸露出閘 極之主體結構的第二複晶矽層與源極/汲極區的接觸窗開 (請先閲讀背面之注意事項再填寫本頁) 訂 線 經濟部智慧財產局員工消費合作社印製 本紙張尺度逍用中國國家標準（CNS ) A4规格（210X297·公釐） A7 B7 43 25 0 7 ii)43iwi；LliK/〇(J6 五、發明説明（令） 口，或是在介電層中形成一自動對準接觸窗開口，以裸露 出基底的源極/汲極區。 依照本發明實施例所述，上述之方法更包括於第一複 晶矽層與該金屬矽化物層之間形成一第一阻障層，於金屬 .矽化物層與第二複晶矽層之間形成一第二阻障層以及於第 二複晶矽層與頂蓋層之間形成一抗反射層之步驟。 本發明在頂蓋層與金屬矽化物層之間增加一層類似於 複晶矽材質之緩衝層，因此其可以減緩頂蓋層的應力，避 免金屬矽化物層在後續形成接觸窗開口的過程中產生剝離 的現象，並且可以避免金屬矽化物遭受蝕刻的侵蝕而損 失。 本發明之閘極之主體結構具有頂蓋層，且其側壁具有 間隙壁，因此，在形成自動對準接觸窗開口的過程中，頂 蓋層與間隙壁均可以保護閘極之主體結構，避免其遭受蝕 刻的破壞，故而可以提昇製程之預度（Process Window)興製 程的容忍度。而且，本發明在頂蓋層與金屬矽化物層之間 增加一層類似於複晶矽材質之緩衝層，因此其可以減緩頂 蓋層的應力，並且在後續形成接觸窗開口的過程中避免燊 屬矽化物層產生剝離的現象。 本發明之閘極係具有金屬矽化物者，因此，可以降低 閘極的阻値，以提昇元件之執行效能。 爲讓本發明之上述和其他目的、特徵、和優點能吏明 顯易懂，下文特舉一較佳實施例並配合所附圖式，作詳 細說明如下： (讀先閱讀背面之注意事項再填I本頁) 訂 終 經濟部智慧射產局員工消費合作社印製 • 61 本紙張尺度適用中國國家標準（CNS ) A4规格（2丨〇><2耵公釐） 經濟部智慧財產局員工消費合作社印製 432507 504jIw1'.U〇c/(J06 A 7 B7 五、發明説明（n 圖式之簡單說明： 第1A圖係繪示習知一種將金屬矽化物應用於閘極之 製作的半導體元件的剖面圖； 第1B圖係繪示習知一種具有具有不同深度之接觸窗之 .半導體元件的剖面圖； 第2A圖至第2C圖係繪示依照本發明一較佳實施例之 一種半導體元件之製造流程的剖面圖；以及 第3圖係繪示在第2B圖所繪示之介電層中形成具有不 同蝕刻深度之接觸窗開口其元件的剖面圖。胃 標記之簡單說明： 100、200 基底 104 ' 204 閘極氧化層 106 ' 206 複晶砂層 108 ' 208 ' 212 阻障層 110' 210 金屬砂化物層 116、216 抗反射層 118、218 頂蓋層 120、220 閘極之主體結構 122 ' 214 > 222 緩衝層 124 源極/汲極區 130 ' 230 間隙壁 132 ' 232 介電層 134 > 234 自動對準接觸窗開口 136 ' 138 ' 236 ' 238 接觸窗開口 -------”----β---„---.—IT------^ j ί/ _ (請先閲讀背面之注意事項再填寫本頁) 432507 烟_B7_ 五、發明说明（έ ) 224 具輕摻雑極汲結構之源極/汲極區 226 輕摻雜源極/汲極區 228 重摻雜源極/汲極區 實施例_ 第2Α圖至第2C圖係繪示依照本發明一較佳實施例之 .一種半導體元件之製造流程的剖面示意圖。 首先，請參照第2Α圖，在所提供的基底200上形成閘 極氧化層204與複晶矽層206。閘極氧化層204的形成方法 例如爲熱氧化法。複晶砂層206的形成方法例如爲化學氣 相沉積法。複晶矽層206具有摻雜，其摻雜係於沉積複晶 矽層的同時進行臨場摻雑而賦予，或是於複晶矽形成之 後，再以離子佈植的方式而使摻雜植入於其中。 之後，請繼續參照第2Α圖，在複晶矽層206上形成一 層金屬矽化物層210。較佳的方法，係在形成金屬矽化物 層210之前先在複晶矽層206的表面上形成一層阻障層 208，以防止金屬矽化物層210與複晶矽層206發生交互擴 散。金屬矽化物層210之材質包括矽化鈦、矽化鈷、矽化 坦等耐熱金屬所形成之金屬矽化物，或是具有相似性質 者’其形成的方法例如爲化學氣相沉積法或濺鍍法。較佳 的金屬矽化物層210例如爲矽化鈦(TiSi〇，其中較佳的〆 値約爲L1至1.8左右。阻障層208之材質例如是氮化鈦、 氮化鉬或具有相似性質者，其形成的方法例如爲化學氣相 沉積法或是濺鍍法。 接著，在金屬矽化物層210上形成一層緩衝層214。較 8 冢ϋ張尺度適用中國國家標準（CNS ) A4规格（2丨0X297公釐) (請先閱讀背面之注意事項再填寫本頁) _飞. 經濟部智慧財產局員工消費合作社印製 432507 ’ itM3l\v l.doc/〇()6 A7 ____ B7__ 五、發明説明（。） 佳的方法係在形成緩衝層214之前，先在金屬矽化物層210 的表面上形成一層阻障層212，以防止金屬矽化物層210 與緩衝層214發生交互擴散。緩衝層2H之材質係可以減 緩後續形成之頂蓋層218之應力，並且可以防止金屬矽化 .物層210在後續的製程中發生剝離者。較佳的緩衝層214 例如是複晶矽或是具有相似性質者。複晶矽緩衝層214的 形成方法例如爲化學氣相沉積法。複晶矽層緩衝層214具 有摻雜（Dopant)，其摻雜係於沉積複晶矽層的同時進行臨場 (In-Sku)摻雜而賦予，或是於複晶矽形成之後，再以離子佈 植的方式而使摻雜植入於其中。阻障層212之材質例如是 氮化鈦、氮化鉬或具有相似性質者，其形成的方法例如爲 化學氣相沉積法或是濺鍍法（Sputtering)。 爲了避免前述之各沉積層在後續的微影製程中，因爲 反射現象造成干擾而使微影的解析度下降，在形成緩衝層 214之後’較佳的方法可以在緩衝層214上先形成一層抗反 射層216，以減少前述各沉積層的反射現象。抗反射層216 之材質包括氮氧化矽，其形成的方法例如爲低壓化學氣相 沉積法（LPCVD)，厚度約爲200埃至300埃左右《 其後，請繼續參照第2 A圖，在抗反射層216的表面上 形成一層頂蓋層218。頂蓋層218之材質係與後續形成之介 電層具有不同之蝕刻率者，其厚度約爲1500埃至2500埃 左右。當介電層之材質爲氧化矽時，較佳的頂蓋層218之 材質例如是氮化矽或是具有相似性質者。氮化矽頂蓋層218 的形成方法例如爲低壓化學氣相沉積法。 9 本紙張尺度適用Γ國國家標準（CNS > A4规核H〇X297公釐） - (請先聞讀背面之注意事項再填寫本頁) 訂 -線、 經濟部智懇財產局員工消費合作社印製 經濟部智慧財產局員Η消費合作社印製 4325 07 A7 5043hv!*.<j〇c/(K)6 ^ B7 五、發明説明（J) 接著，請參照第2B圖，以微影成像與蝕刻程序定義上 述之頂蓋層218、抗反射層216、緩衝層214、阻障層212、 金屬矽化物層210、阻障層208、複晶矽層206與閘極氧化 層204之圖案，以形成一閘極之主體結構220 = 之後，在基底200中形成具有輕摻雜汲極結構(LDD)之 .源極/汲極區224，並在閘極之主體結構220的側壁形成間 隙壁230,較佳的方法係在形成間隙壁230之前先在閘極之 主體結構220的側壁先形成一層緩衝層222，使緩衝層222 介於閘極之主體結構220與間隙壁230之間，以緩和間隙 壁230之應力。然後，再進行輕摻雜汲極結構之源極/汲極 區224其輕摻雜源極/汲極區226之離子植入製程。緩衝層 222之材質例如爲氧化矽，其形成的方法例如是以四乙基 矽酸鹽（TEOS)爲矽源之低壓化學氣相沉積法，先形成一層 共形（Confomal)的緩衝氧化層，然後，以蝕刻製程將頂蓋 層218上所覆蓋的緩衝氧化層去除。當輕摻雜源極/汲極區 226形成之後，再於緩衝層的側壁形成間隙壁230。其後， 再進行輕摻雜汲極結構之源極/汲極區224其重摻雜源極/ 汲極區226之離子植入製程。間隙壁230之材質例如爲氮 化矽’其形成的方法例如是以低壓化學氣相沉積法在基底 200上形成一層氮化矽層，然後，再以等向性回蝕刻的方 式以形成之。 然後’在基底200上形成一層介電層232，介電層232 之材質例如氧化矽、磷矽玻璃(PSG)或棚磷矽玻璃（BpsG)， 形成的方法例如爲化學氣相沉積法。較佳的方法係在形成 ]{) 本紙張尺度適用中國國家標準（CNS ) Α4规格（210x297公釐） (請先閱讀背面之注$項再填寫本頁) -訂A7 B7 432507 i〇4; ilwr.d〇c / CK) 6 i. Description of the invention (/) The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method of using a buffer layer to prevent a gate Method for fabricating gate structure in which metal silicide of electrode structure is peeled off. With the advantages of high melting point, stability, and low resistivity, the application of metal silicide (MetalSiUcide) in integrated circuit manufacturing has become more and more common. In the technology of deep sub-micron integrated circuits with gradually decreasing line width, contact area, and interface depth, in order to effectively improve the working quality of components, reduce resistance and reduce signal transmission delay caused by resistance and capacitance (RC) , A layer of metal silicide will be formed on the conventional polycrystalline silicon gate or the junction of the source / drain region to reduce the gate resistance and junction resistance, and then increase the driving current of the entire component. The purpose of time or operating speed of the circuit. FIG. 1A is a cross-sectional view showing a conventional semiconductor device manufactured by applying a metal silicide to a gate electrode. Referring to FIG. 1A, a typical metal silicide layer 110 is formed on the surface of the polycrystalline silicon layer 106. However, in order to avoid cross diffusion of the metal silicide layer 110 and the polycrystalline silicon layer 106, it is common practice to A barrier layer 108 is formed on the substrate 100 before the metal silicide layer 110 is formed. In order to avoid the interference caused by the reflection phenomenon of the deposited layer in the subsequent lithography process in the process of defining the foregoing deposited layers, a typical method is to cover the metal silicide layer 110 with an anti-reflection layer. (Anti-Reflection Coating, ARC) 116 to reduce the phenomenon of reflection. In addition, a layer of silicon nitride is usually formed on the surface of the anti-reflection layer 116 and the side wall of the main structure 120 of the formed gate. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297). Li) (Please read the notes on the back before filling out this page) Order · Employees' Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs, India Li 43250? 5〇4. ≫ ΐ \ νΓ.ίΙοο'Ι) {) 6 ^ _ Β7 5 2. Description of the invention (ι) (Please read the precautions on the back before filling out this page) Cap layer 18 and Spacer 130 to automatically align the contact window openings in the future (Self-aligned Contact Opening) 134 protects the main structure 120 of the gate electrode from etch during the uranium engraving process. Since the silicon nitride material is apt to cause stress accumulation, the conventional method usually adds a silicon oxide buffer layer 122 between the spacer 130 and the main body structure 120 of the gate to reduce the stress of the spacer 130. However, for the cap layer 118 in the main structure of the gate electrode 20, the accumulated stress of the cap layer 118 cannot be reduced by the anti-reflection layer 116 below the cap layer 118, which results in the peeling of the formed metal oxide layer 110. phenomenon. -Line. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In addition, please refer to Figure 1B. In the process of forming the contact window openings 136 and 138, the main structure 120 of the above gate is exposed because the contact window 136 is exposed metal. The silicide layer 110 and the contact window opening 138 must expose the source / drain regions 124 of the substrate 100, and the depths of the etching required for the two are not the same. After the shallower contact window openings 136 are formed, the entire etching process is not terminated, and the uranium-etched dielectric layer 132 process must be performed to form the deeper contact window openings 138. However, after the contact window opening 136 is formed, the metal silicide layer 110 is exposed. Therefore, during the subsequent process of etching the dielectric layer 132 to form the contact window opening 138, the metal silicide layer 10 is also exposed to the etching environment. Therefore, the loss of the metal silicide layer 110 is easily caused, and the resistance of the main structure 120 of the gate is increased, and the performance of the device is reduced. Therefore, the present invention provides a gate structure, which includes a gate oxide layer, a polycrystalline layer, a metal sand layer, a buffer layer and a cap layer. The gate oxide layer covers the gate oxide layer. On the substrate, polycrystalline silicon 4 This paper is in accordance with Chinese National Standard (CNS) A4 specification (2I0X297 mm) 432507 a 7 5043l \ vr.doc / 006 B7 V. Description of the invention (2) The layer system is configured for gate oxidation And a buffer layer is disposed on the metal silicide and interposed between the metal silicide layer and the cap layer. According to the embodiment of the present invention, the above-mentioned gate structure further includes a first barrier layer, a second barrier layer and an anti-reflection layer, wherein the first group of barrier layers is disposed between the polycrystalline silicon layer and the metal. Between the silicide layers; the second barrier layer is disposed between the metal silicide layer and the buffer layer; the anti-reflection system is disposed between the buffer layer and the cap layer. The invention adds a buffer layer similar to the polycrystalline silicon material between the top cap layer and the metal silicide layer, which can reduce the stress of the top cap layer and avoid the generation of the metal silicide layer in the subsequent process of forming the contact window opening. The phenomenon of peeling. The gate of the present invention is a metal silicide, so the resistance of the gate can be reduced to improve the performance of the device. The invention provides a method for manufacturing a semiconductor device. After the gate oxide layer and the first polycrystalline sand layer are formed on a substrate, a metal silicide layer is formed on the first polycrystalline silicon layer, and then the metal A second polycrystalline silicon layer is formed on the silicide layer, and a cap layer is formed on the second polycrystalline silicon layer. Next, the patterns of the cap layer, the second polycrystalline silicon layer, the metal silicide layer, the first polycrystalline sand layer, and the gate oxide layer are defined to form a gate main structure, and then the main structure of the gate is A buffer layer and a gap wall are formed on the sidewall, and a source / drain region is formed on the substrate. Then, a dielectric layer is formed on the substrate, and a dielectric layer is defined to form an exposed gate electrode in the dielectric layer. The contact window between the second polycrystalline silicon layer of the main structure and the source / drain region opens (please read the precautions on the back before filling out this page). China National Standard (CNS) A4 specification (210X297 · mm) A7 B7 43 25 0 7 ii) 43iwi; LliK / 〇 (J6 V. Description of the invention (order) port, or to form an automatic alignment in the dielectric layer The contact window is opened to expose the source / drain region of the substrate. According to the embodiment of the present invention, the above method further includes forming a first barrier between the first polycrystalline silicon layer and the metal silicide layer. Layer between the metal silicide layer and the second polycrystalline silicon layer Forming a second barrier layer and forming an anti-reflection layer between the second polycrystalline silicon layer and the capping layer. The present invention adds a layer similar to the polycrystalline silicon material between the capping layer and the metal silicide layer. The buffer layer, therefore, can reduce the stress of the cap layer, avoid the metal silicide layer from peeling off during the subsequent formation of the contact window opening, and prevent the metal silicide from being eroded and lost by the etching. The main structure has a cap layer and the side wall has a gap wall. Therefore, in the process of forming the automatic alignment of the contact window opening, both the cap layer and the gap wall can protect the main structure of the gate electrode from being damaged by etching. Therefore, the tolerance of the process window (Process Window) and the manufacturing process can be improved. In addition, the present invention adds a buffer layer similar to the polycrystalline silicon material between the cap layer and the metal silicide layer, so it can slow down the top The stress of the capping layer and avoiding the phenomenon that the metal silicide layer is peeled off during the subsequent formation of the contact window opening. The gate electrode of the present invention has gold Silicides, therefore, can reduce the resistance of the gate to improve the performance of the device. In order to make the above and other objects, features, and advantages of the present invention obvious and understandable, a preferred embodiment is given below and In accordance with the attached drawings, the detailed description is as follows: (Read the precautions on the back and then fill in this page) Printed by the Consumers' Cooperatives of the Ministry of Economic Affairs ’Intelligent Projection Bureau • 61 This paper size applies to Chinese National Standards (CNS) A4 Specifications (2 丨 〇 > < 2 耵 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 432507 504jIw1'.U〇c / (J06 A 7 B7 V. Description of the invention (n Simple description of the diagram: FIG. 1A is a cross-sectional view of a conventional semiconductor device using a metal silicide applied to a gate electrode; FIG. 1B is a cross-sectional view of a semiconductor device having a contact window having different depths; FIGS. 2A to 2C are cross-sectional views showing a manufacturing process of a semiconductor device according to a preferred embodiment of the present invention; and FIG. 3 is a view showing formation of a semiconductor layer in the dielectric layer shown in FIG. 2B. Different etch depth The contact window opening cross section of the element of FIG. Brief description of stomach mark: 100, 200 substrate 104 '204 gate oxide layer 106' 206 polycrystalline sand layer 108 '208' 212 barrier layer 110 '210 metal sand layer 116, 216 anti-reflection layer 118, 218 cap layer 120, 220 main structure of gate 122 '214 > 222 buffer layer 124 source / drain region 130' 230 spacer 132 '232 dielectric layer 134 > 234 automatic alignment of contact window opening 136' 138 '236' 238 Contact window opening ------- "---- β ---„ ---.— IT ------ ^ j ί / _ (Please read the precautions on the back before filling in this page ) 432507 Smoke _B7_ V. Description of the Invention (Hand) 224 Source / Drain Region with Lightly Er-Doped Drain Structure 226 Lightly Doped Source / Drain Region 228 Heavyly Doped Source / Drain Region Example_ 2A to 2C are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to a preferred embodiment of the present invention. First, referring to FIG. 2A, a gate oxide layer 204 and a polycrystalline silicon layer 206 are formed on the provided substrate 200. A method for forming the gate oxide layer 204 is, for example, a thermal oxidation method. The method for forming the polycrystalline sand layer 206 is, for example, a chemical vapor deposition method. The polycrystalline silicon layer 206 has doping, and the doping is imparted by in-situ erbium doping while the polycrystalline silicon layer is deposited, or after the formation of the polycrystalline silicon, the doping is implanted by ion implantation In it. After that, please refer to FIG. 2A to form a metal silicide layer 210 on the polycrystalline silicon layer 206. A preferred method is to form a barrier layer 208 on the surface of the polycrystalline silicon layer 206 before forming the metal silicide layer 210 to prevent the metal silicide layer 210 and the polycrystalline silicon layer 206 from diffusing interactively. The material of the metal silicide layer 210 includes metal silicides formed of heat-resistant metals such as titanium silicide, cobalt silicide, and silicide, or those having similar properties. The formation method thereof is, for example, a chemical vapor deposition method or a sputtering method. The preferred metal silicide layer 210 is, for example, titanium silicide (TiSi0, among which the preferred 〆 値 is about L1 to 1.8. The material of the barrier layer 208 is, for example, titanium nitride, molybdenum nitride, or those having similar properties. A method for forming the same is, for example, a chemical vapor deposition method or a sputtering method. Next, a buffer layer 214 is formed on the metal silicide layer 210. Compared with a standard of 8 mounds, the Chinese National Standard (CNS) A4 specification (2 丨0X297mm) (Please read the notes on the back before filling out this page) _Fei. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 432507 'itM3l \ v l.doc / 〇 () 6 A7 ____ B7__ 5. Description of the invention (.) A good method is to form a barrier layer 212 on the surface of the metal silicide layer 210 before forming the buffer layer 214 to prevent the metal silicide layer 210 and the buffer layer 214 from interdiffusing. The buffer layer 2H The material can reduce the stress of the cap layer 218 formed later, and can prevent the silicidation of the metal. The material layer 210 is peeled off in the subsequent process. The preferred buffer layer 214 is, for example, polycrystalline silicon or a material with similar properties. Polycrystalline silicon buffer layer The formation method of 214 is, for example, a chemical vapor deposition method. The polycrystalline silicon layer buffer layer 214 has a dopant, and the doping is provided by depositing the polycrystalline silicon layer while performing in-sku doping. Or, after the formation of the polycrystalline silicon, doping is implanted therein by ion implantation. The material of the barrier layer 212 is, for example, titanium nitride, molybdenum nitride, or those with similar properties. For example, it is a chemical vapor deposition method or a sputtering method. In order to avoid the aforementioned lithographic processes, the resolution of the lithographic image is reduced due to interference caused by reflection phenomena in the subsequent lithographic process, and a buffer layer 214 is formed. Afterwards, a better method may be to form an anti-reflection layer 216 on the buffer layer 214 first to reduce the reflection phenomenon of each of the aforementioned deposition layers. The material of the anti-reflection layer 216 includes silicon oxynitride, and the formation method thereof is, for example, low-pressure chemical gas Phase deposition (LPCVD), with a thickness of about 200 angstroms to about 300 angstroms. "After that, please refer to FIG. 2A to form a capping layer 218 on the surface of the antireflection layer 216. The material of the capping layer 218 is And the subsequent formation If the electrical layer has a different etching rate, its thickness is about 1500 Angstroms to about 2500 Angstroms. When the material of the dielectric layer is silicon oxide, the preferred material of the cap layer 218 is, for example, silicon nitride or has similar properties. The method for forming the silicon nitride cap layer 218 is, for example, a low-pressure chemical vapor deposition method. 9 This paper size is applicable to the national standard (CNS > A4 Regulation H297Xmm)-(Please read the back first Please fill in this page before ordering) Order-line, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperative, 4325 07 A7 5043hv! *. ^ B7 V. Description of the Invention (J) Next, please refer to Figure 2B, and define the above-mentioned cap layer 218, anti-reflection layer 216, buffer layer 214, barrier layer 212, and metal silicide layer by lithography imaging and etching procedures. 210, the barrier layer 208, the polycrystalline silicon layer 206, and the gate oxide layer 204 are patterned to form a gate body structure 220 = After that, a lightly doped drain structure (LDD) is formed in the substrate 200. A source / drain region 224, and a gap wall 230 is formed on a side wall of the gate main structure 220, A good method is to form a buffer layer 222 on the side wall of the main structure 220 of the gate electrode before forming the gap wall 230, so that the buffer layer 222 is interposed between the main structure 220 of the gate electrode and the gap wall 230 to ease the gap wall. Stress of 230. Then, a lightly doped source / drain region 224 and a lightly doped source / drain region 226 are implanted. The material of the buffer layer 222 is, for example, silicon oxide. A method for forming the buffer layer 222 is, for example, a low-pressure chemical vapor deposition method using tetraethyl silicate (TEOS) as a silicon source. Then, the buffer oxide layer covered on the cap layer 218 is removed by an etching process. After the lightly doped source / drain region 226 is formed, a spacer 230 is formed on the sidewall of the buffer layer. Thereafter, an ion implantation process of the lightly doped source / drain region 224 and the heavily doped source / drain region 226 is performed. The material of the partition wall 230 is, for example, silicon nitride. The method for forming the partition wall 230 is, for example, forming a silicon nitride layer on the substrate 200 by a low-pressure chemical vapor deposition method, and then forming it by an isotropic etch-back method. Then, a dielectric layer 232 is formed on the substrate 200. The material of the dielectric layer 232 is, for example, silicon oxide, phosphosilicate glass (PSG), or greenhouse phosphosilicate glass (BpsG). The better method is to form] {) This paper size is applicable to China National Standard (CNS) Α4 size (210x297 mm) (Please read the note on the back before filling this page)-Order
綵一V A7 B7 432507 5043lwl'.ifoc/f](J6 五、發明説明（y ) — " -— 介電層m之後，進行〜道平坦化製程，以獲得亘有平坦 表醜介電層。平坦化製程的方法例如是以化學機械硏磨 技術(CMP)以執行之。 之後’請雜第2C _第3圖，以微影成像技術與触 刻程序形成裸露出源極/汲極區似之自動對準接觸窗開口 234 ’如第2C1I所τκ ’或是同時製作裸露出關之主體結 構220的接觸窗開口 236與裸露出源極/汲極區似的接觸 窗開口 238，繪示於第3圖。 ▲請參照第2c圖，崎本發明之麵的主雖構22〇的 頂邰與側壁分別爲一層與介電層232具有不同蝕刻率的頂 蓋層218與間隙壁230 »因此裸露出源極/汲極區224的接 觸窗開口 234其形成的方法可以以自動對準接觸窗的方式 形成，閘極之主體結構22〇可藉由頂蓋層218與間隙壁23〇 的保護，而不會遭受蝕刻製程的破壞，因此可以增加製程 的容忍度與製程的預度。 請參照第3圖，本發明在形成具有不同深度的接觸窗 開口 236與接觸窗開口 238的過程中，在触刻劑飽穿介電 層232與閘極之主體結構22〇的頂蓋層218、抗反射層216 而形成接觸窗開口 236時，接觸窗開口 236所裸露的緩衝 層214,可以在繼續形成接觸窗開口 238的蝕刻製程中保護 其下方的金屬矽化物層21Q，避免金屬矽化物層210因爲蝕 刻的破壞而遭受損失，因此，本發明之方法可以維持閘極 之主體結構的阻値，避免習知方法中因爲金屬矽化物層在 倉虫刻製程中損失，造成元件阻値的上升，執行效能下降等Caiyi V A7 B7 432507 5043lwl'.ifoc / f] (J6 V. Invention Description (y) — " -— After the dielectric layer m, a ~ planarization process is performed to obtain a flat surface with a ugly dielectric layer The method of the planarization process is performed by, for example, chemical mechanical honing technology (CMP). After that, 'please mix 2C_3, and form exposed source / drain regions by lithography and touch lithography. It is similar to automatically aligning the contact window opening 234 'as described in 2C1I τκ' or simultaneously making the contact window opening 236 of the exposed main structure 220 and the contact window opening 238 similar to the exposed source / drain region. In Figure 3. ▲ Please refer to Figure 2c. The top and side walls of the main structure 22 of the surface of the present invention are respectively a top cover layer 218 and a spacer 230 with different etch rates from the dielectric layer 232 » Therefore, the method of forming the contact window opening 234 exposing the source / drain region 224 can be formed by automatically aligning the contact window. The main structure of the gate 22 can be formed by the cap layer 218 and the spacer 23. Protects against damage from the etch process, thus increasing process tolerance Please refer to FIG. 3. In the process of forming the contact window opening 236 and the contact window opening 238 with different depths, the present invention penetrates the dielectric layer 232 and the main body structure 22 of the gate electrode when the contact agent is saturated. 〇 When the contact window opening 236 is formed by the top cover layer 218 and the anti-reflection layer 216, the exposed buffer layer 214 of the contact window opening 236 can protect the metal silicide layer underneath during the etching process of forming the contact window opening 238. 21Q, to prevent the metal silicide layer 210 from being lost due to the damage of the etching. Therefore, the method of the present invention can maintain the resistance of the main structure of the gate electrode, and avoid the loss of the metal silicide layer in the worm process in the conventional method , Resulting in an increase in component resistance and a decrease in execution performance, etc.
II 本紙張尺度適.用中國國家標準（CNS )八4規格（2!〇χ297公釐） (請先閱讀背面之注意事項再填窝4頁} 訂- 線 經濟部智慧財產局員工消費合作社印製 A7 B7 432507 五、發明説明（/i?) 問題。 (請先閱讀背面之注意事項再填寫本頁) 此外，本發明在金屬矽化物層210與頂蓋層218之間 所增加的緩衝層214,可以減緩頂蓋層218其材質所造成的 應力，因此本發明之方法可以進一步防止金屬矽化物層210 .發生剝離的現象，以提昇元卿可靠度。 7 綜合以上所述本發明至g辑下列優點： 1/ 1.本發明在頂蓋層與金物層之間增加的緩衝層II The size of this paper is suitable. Use Chinese National Standard (CNS) 8-4 specification (2! 〇χ297 mm) (Please read the precautions on the back before filling the 4 pages) Order-Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System A7 B7 432507 V. Explanation of the invention (/ i?) (Please read the precautions on the back before filling this page) In addition, the buffer layer added between the metal silicide layer 210 and the cap layer 218 of the present invention 214, it can slow down the stress caused by the material of the top cover layer 218, so the method of the present invention can further prevent the metal silicide layer 210 from peeling off to improve the reliability of the Yuan Qing. 7 According to the above-mentioned invention to g The following advantages are provided: 1 / 1. The buffer layer added between the cap layer and the gold layer according to the present invention
可以緩衝頂蓋層之應金屬矽化物層產生剝離 的現象。 G 2. 本發明在頂蓋層與金屬係化物層之間增加的緩衝層 可以避免金屬矽化物層在形成接觸窗的過程中發生 減損的現象。 3. 本發明之閘極具有低阻値之金屬矽化物可以提昇元 件的執行效能。 4. 本發明可以用於自動對準接觸窗之製程，以製程的預 度與成的容忍度。 經濟部智慧財產局員工消費合作社印製 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準° 12 本紙張尺度適用中國國家標準（CNS ) M規格（21〇><297公釐It can buffer the peeling phenomenon of the top metal silicide layer. G 2. The buffer layer added between the cap layer and the metal-based compound layer of the present invention can prevent the metal silicide layer from being damaged during the process of forming the contact window. 3. The metal silicide with low-resistance gate in the gate of the present invention can improve the performance of the device. 4. The present invention can be used for the process of automatically aligning the contact window, in order to predict the process and the tolerance of the process. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit and scope of the present invention. Various modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application ° 12 This paper size applies the Chinese National Standard (CNS) M specification (21〇 > < 297) Centimeter