3660TWF.DOC/002 A7 l \ B7 五、發明説明（丨） 本發明是有關於—種積體電路之製造方法，且特別 是有關於一種同時形成導體閘極層與局部內連線（local interconnect)之半導體兀件的製造方法。 當積體電路的積集度增加’使得晶片的表面無法提供 足夠的面積來製作所需的內連線時，爲了配合電晶體縮小 後，所增加的內連線需求’兩層以上的金屬層設計，便逐 漸的成爲許多積體電路所必須採用的方式。 局部內連線是一種將金氧半電晶體電路之閘極與源 極/汲極局部連接的內連線製程。由於以局部內連線來製 作內連線可用來改善元件的積集度，因此，是一種在深次 微米製程中常採用的方式。 第1A至1D圖係繪示習知之一種局部內連線之製造 流程剖面示意圖。 首先，請參照第1A圖’提供一基底1 〇，並於此基底 1〇中形成隔離區11，以定義出元件之主動區。接著，在 基底10的元件主動區上依序分別形成閘極氧化（gate oxide)層12a與12b、圖案化的複晶矽閘極層13a與圖案 化的複晶矽閘極層13b。其後，再分別於複晶矽閘極層13a 與複晶矽閘極層13b其二側的基底10中分別形成源極/汲 極區14a與源極/汲極區14b，以及覆蓋於複晶矽閘極層13a 與複晶砂閘極層1 3b之側壁的間隙壁（spacer) 1 5a、1 5b。 然後，請參照第1B圖，進行自動對準金屬矽化物製 程（self-align suicide)，以分別在源極/汲極區14a、14b以 及複晶矽閘極層13a、複晶矽閘極層13b形成金屬矽化物 3 本紙張尺度適用中國國$系準（€；>1$)八4規格（210父297公釐） ' -------------裝------訂------ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 3660TWF.DOC/002 經濟部中央標隼局員工消費合作社印製 ——aaΜ:; A7 B7 五、發明説明（>) 層16a、16b以及l7a、nb。由於矽化鈦具備著低阻値以 及製程上較佳的可控制性等優點，因此，是目前最常被使 用的金屬矽化物材半斗。 其後’請參照第1C圖，在基底10上覆蓋一層氮化鈦 層（titanium nitride ; TiN)18。然後，再於氮化鈦層18上 覆蓋一層圖案化的光阻層19,以定義局部內連線之區域。 然後’請參照第1D圖，蝕刻去除未被圖案化之光阻 層I9所覆蓋的氮化鈦層18，然後，再去除圖案化之光阻 層19 ’使留下之氮化鈦層1 8a可以透過金屬矽化物層1 6b 與17b ’而形成連接源極/汲極區13b與複晶矽閘極層13b 之局部內連線。 在上述的方法中，係先藉由自動對準矽化物製程以在 複晶矽閘極以及源極/汲極區形成可以降低片電阻的金屬 矽化物’然後，再透過氮化鈦層18a的形成，而達到連接 源極/汲極區13b與複晶矽閘極層13b之目的。 然而’隨著積體電路日益的小型化，閘極線寬尺寸亦 必須相對縮小，方能提昇元件的積集度。但隨著閘極線幅 的縮小化，一般發現砍化鈦將會產生微細線幅效應（narrow linewidth)，使得複晶矽閘極層上所形成的矽化鈦其片電 阻隨著尺寸的減小而增加，導致原先由於砍化鈦具備較低 電阻率而能提供較低之閘極片電阻的優勢不再。 有鑑於此，本發明的目的就是在提供一種金氧半導體 的製造方法，可以適用於高度積集化之積體電路的製程 中，以降低閘極以及源極/汲極區之片電阻。 4 (請先閲讀背面之注意事項再填寫本頁)3660TWF.DOC / 002 A7 l \ B7 V. INTRODUCTION TO THE INVENTION (丨) The present invention relates to a method for manufacturing integrated circuits, and in particular, to a method of forming a conductor gate layer and a local interconnect at the same time (local interconnect) ) Manufacturing method of semiconductor element. When the integration degree of integrated circuits increases, so that the surface of the wafer cannot provide enough area to make the required interconnects, in order to match the transistor shrink, the increased interconnect requirements require two or more metal layers. Design has gradually become the way that many integrated circuits must adopt. The local interconnect is an interconnect process that locally connects the gate of the metal-oxide semiconductor transistor circuit to the source / drain. Because local interconnects are used to improve the integration of components, it is a method often used in deep sub-micron processes. Figures 1A to 1D are schematic cross-sectional views showing a conventional manufacturing process of a local interconnect. First, referring to FIG. 1A, a substrate 10 is provided, and an isolation region 11 is formed in the substrate 10 to define an active region of the device. Next, gate oxide layers 12a and 12b, a patterned polycrystalline silicon gate layer 13a, and a patterned polycrystalline silicon gate layer 13b are sequentially formed on the element active region of the substrate 10 in this order. Thereafter, a source / drain region 14a and a source / drain region 14b are formed in the substrate 10 on the two sides of the complex silicon gate layer 13a and the complex silicon gate layer 13b, respectively, and covered with the complex The spacers 15a and 15b on the side walls of the crystalline silicon gate layer 13a and the complex crystal sand gate layer 13b. Then, referring to FIG. 1B, a self-align suicide process is performed to separate the source / drain regions 14a, 14b, the polycrystalline silicon gate layer 13a, and the polycrystalline silicon gate layer, respectively. 13b forms metal silicide 3 This paper size is applicable to China's national standard (€; > 1 $) 8 4 specifications (210 father 297 mm) '------------- pack- ---- Order ------ (Please read the notes on the back before filling out this page) Printed by the Consumers 'Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 3660TWF.DOC / 002 Printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs ——AaM :; A7 B7 V. Description of the invention (>) Layers 16a, 16b and 17a, nb. Because titanium silicide has the advantages of low resistance and better controllability in the process, it is currently the most commonly used metal silicide half-bucket. Thereafter, please refer to FIG. 1C, and cover the substrate 10 with a titanium nitride (TiN) 18 layer. Then, a patterned photoresist layer 19 is overlaid on the titanium nitride layer 18 to define a region of a local interconnect. Then 'Please refer to FIG. 1D, remove the titanium nitride layer 18 not covered by the patterned photoresist layer I9 by etching, and then remove the patterned photoresist layer 19' so that the remaining titanium nitride layer 18a Local interconnections connecting the source / drain regions 13b and the polycrystalline silicon gate layer 13b can be formed through the metal silicide layers 16b and 17b '. In the above method, a metal silicide that can reduce the sheet resistance is formed in the polycrystalline silicon gate and the source / drain region by an auto-aligned silicide process. Then, it passes through the titanium nitride layer 18a. It is formed to achieve the purpose of connecting the source / drain region 13b and the polycrystalline silicon gate layer 13b. However, with the increasing miniaturization of integrated circuits, the size of the gate line width must also be relatively reduced in order to increase the degree of component integration. However, with the reduction of the gate line amplitude, it is generally found that cutting titanium will produce a narrow linewidth effect, so that the sheet resistance of the titanium silicide formed on the polycrystalline silicon gate layer decreases with size. The increase leads to the fact that the advantage of providing lower gate sheet resistance due to the lower resistivity of titanium oxide is no longer available. In view of this, the object of the present invention is to provide a method for manufacturing a metal-oxide semiconductor, which can be applied to the process of a highly integrated integrated circuit to reduce the sheet resistance of the gate and source / drain regions. 4 (Please read the notes on the back before filling this page)
本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） A7 B7 3660TWF.DOC/002 五、發明説明（，） 本發明的另一目的是提供一種局部內連線的製造方 法’以符合高度積集化之積體電路元件之需求。 依照本發明之一較佳實施例，提出一種半導體元件的 製造方法，其簡述如下：在所提供的基底形成隔離區之 後’在隔離區所定義的第一主動區與第二主動區上分別形 成第一閘極體與第二閘極體。其後，於第一閘極體之側壁 形成第一間隙壁，並於第二閘極體之側壁形成第二間隙 壁。接著，於第一主動區形成第一源極/汲極區，於第二 主動區形成第二源極/汲極區。之後，於基底上形成一平 坦化之介電層，此平坦化之介電層裸露出第一閘極體之第 一頂蓋層與第二閘極體之第二頂蓋層。然後，去除部份介 電層與閘極體之一側的第二間隙壁，以形成一第一開口， 此第一開口裸露出該閘極體之一側與第二源極/汲極區。 ，接著，去除第一頂蓋層，以形成第二開口，並去除第二頂 盡層，使第一開口轉爲一局部內連線開口。其後，在基底 上形成一層導體層，並以化學機械硏磨製程進行平坦化， 以在第二開口中形成導體閘極層，同時在局部內連線開口 中形成局部內連線。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第1A至1D圖係繪示習知局部內連線之製造流程剖 面示意圖；以及 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 :Ϊ III I II - I In —I— I 1^^ ^—Ύ - - HI an— - j - I --- - i -- HI I I Kt I - I-----1 - 3660TWF.DOC/002 A7 B7 五、發明説明（（p ) 第2A至2F圖係繪示依照本發明之一較佳實施例 種半導體元件之製造流程剖面示意圖。 圖式標記說明= 10、 200 :基底 11、 202 :隔離區 12a 、 12b 、 208 、 210 閘極氧化層 複晶矽閘極層 源極/汲極區 間隙壁 金屬矽化物 經濟部中央標準局員工消費合作社印製 13a、13b、212、214 14a 、 14b 、 224 、 226 15a 、 15b 、 220 、 222 16a 、 16b 、 17a 、 17b 18、18a :氮化鈦層 19 :光阻層 204、206 :閘極體 2 1 6、2 1 8 :頂蓋層 228、246 :介電層 230 :側壁 232、234 :開口 2 3 6 :局部內連線開口 238、238a、238b :阻障層/黏著層 240、240a、240b :導體層 242 :導體閘極層 244 :局部內連線 248 :終止層 250 :接觸窗開口 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 3660TWF.DOC/002 五、發明説明（>) 260、270 :主動區 實施例 第2A至2F圖係繪示依照本發明之一較佳實施例，一 種半導體元件之製造流程剖面示意圖。 首先’請參照第2A圖，提供一基底200，並於此基 底200中形成隔離區202，以定義出元件之主動區260與 主動區270。較佳的隔離區202可以採用淺溝渠隔離 (shallow trench isolation，STI)的方式，其方法先在基底 200中形成溝渠之後，再利用化學氣相沈積法將塡充物質 塡入於溝渠之中的方式以形成之。接著，在基底200的主 動區260上形成閘極體204、在基底200的主動區270上 形成閘極體206。閘極體204係由閘極氧化層208、複晶 矽閘極層212、頂蓋層216所組成，而閘極體206係由閘 極氧化層210、複晶矽閘極層214、頂蓋層218所組成。 典型的方法，係先熱氧化法在基底200上形成一層厚度約 爲40A〜150A左右的氧化層。其後，再以化學氣相沈積法 在氧化層上形成一層厚度約爲1000A〜2000A左右的複晶 矽層。接著，在複晶矽層上形成一層絕緣層，此絕緣層之 材質與複晶矽以及後續形成之介電層具有不同的蝕刻率 與硏磨速率，其較佳的材質例如爲化學氣相沈積法所形成 之氮化矽，厚度約爲1000A〜3000A左右。在絕緣層形成 之後，再以微影、蝕刻的方式將氧化層、複晶矽層以及絕 緣層圖案化，而形成如圖所示之閘極氧化層2 0 8、21 0、複 晶矽閘極層212、214、以及頂蓋層216、218。 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） n il - ΙΊ - - I -— (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7 3660TWF.DOC / 002 V. Description of the invention (,) Another object of the present invention is to provide a manufacturing method of local interconnects to comply with Demand for highly integrated integrated circuit components. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor device is provided, which is briefly described as follows: after the provided substrate forms an isolation region, 'on the first active region and the second active region defined by the isolation region, respectively A first gate body and a second gate body are formed. Thereafter, a first gap wall is formed on the side wall of the first gate body, and a second gap wall is formed on the side wall of the second gate body. Then, a first source / drain region is formed in the first active region, and a second source / drain region is formed in the second active region. After that, a planarized dielectric layer is formed on the substrate, and the planarized dielectric layer exposes the first capping layer of the first gate body and the second capping layer of the second gate body. Then, a portion of the dielectric layer and the second gap wall on one side of the gate body is removed to form a first opening, and the first opening exposes one side of the gate body and the second source / drain region. . Then, the first cap layer is removed to form a second opening, and the second top exhaust layer is removed, so that the first opening is turned into a partial interconnecting opening. Thereafter, a conductive layer is formed on the substrate and planarized by a chemical mechanical honing process to form a conductive gate layer in the second opening and a local interconnect in the local interconnect opening. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: Figures 1A to 1D It is a schematic drawing showing the manufacturing process of a local internal connection; and this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) Printed by the Consumer Affairs Cooperative of the Municipal Bureau: Ϊ III I II-I In —I— I 1 ^^ ^ —Ύ--HI an—-j-I ----i-HI II Kt I-I --- --1-3660TWF.DOC / 002 A7 B7 V. Description of the Invention ((p) Figures 2A to 2F are schematic cross-sectional views showing the manufacturing process of a semiconductor device according to a preferred embodiment of the present invention. 10, 200: Substrate 11, 202: Isolation areas 12a, 12b, 208, 210 Gate oxide layer, polycrystalline silicon gate layer source / drain region, gap wall metal silicide, Central Consumer Bureau, Ministry of Economic Affairs, Employee Consumer Cooperative, printed 13a , 13b, 212, 214 14a, 14b, 224, 226 15a, 15b, 220, 222 16 a, 16b, 17a, 17b 18, 18a: titanium nitride layer 19: photoresist layer 204, 206: gate body 2 1 6, 2 1 8: cap layer 228, 246: dielectric layer 230: sidewall 232, 234: openings 2 3 6: local interconnect openings 238, 238a, 238b: barrier / adhesive layers 240, 240a, 240b: conductor layer 242: conductor gate layer 244: local interconnect 248: termination layer 250: Contact window opening (please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7 3660TWF.DOC / 002 5. Description of the invention (>) 260, 270: Active Area Embodiments 2A to 2F are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to a preferred embodiment of the present invention. First, please refer to FIG. 2A to provide a substrate 200, and the substrate 200 An isolation region 202 is formed in 200 to define an active region 260 and an active region 270 of the device. A preferred isolation region 202 may adopt a shallow trench isolation (STI) method. The method first forms a trench in the substrate 200 Afterwards, chemical vapor deposition is used to inject the filling material In a manner to form the trench. Next, a gate body 204 is formed on the active region 260 of the substrate 200, and a gate body 206 is formed on the active region 270 of the substrate 200. The gate body 204 is composed of a gate oxide layer 208, a polycrystalline silicon gate layer 212, and a cap layer 216, and the gate body 206 is composed of a gate oxide layer 210, a polycrystalline silicon gate layer 214, and a cap Consists of layers 218. A typical method is to first form an oxide layer on the substrate 200 with a thickness of about 40A to 150A by thermal oxidation. Thereafter, a crystalline silicon layer having a thickness of about 1000A to 2000A was formed on the oxide layer by a chemical vapor deposition method. Next, an insulating layer is formed on the polycrystalline silicon layer. The material of the insulating layer is different from that of the polycrystalline silicon and the subsequent dielectric layer. The preferred material is, for example, chemical vapor deposition. The thickness of silicon nitride formed by the method is about 1000A to 3000A. After the insulating layer is formed, the oxide layer, the polycrystalline silicon layer, and the insulating layer are patterned by lithography and etching to form the gate oxide layers 208, 21 0, and the polycrystalline silicon gate as shown in the figure. The electrode layers 212, 214, and the cap layers 216, 218. 7 This paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm) n il-ΙΊ--I -— (Please read the precautions on the back before filling this page) Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs system
I 經濟部中央標準局員工消費合作社印製 A7 , 1 3660TWF.DOC/002 B7 五、發明説明（έ7 ) 接著，請繼續參照第2A圖，在閘極體204與閘極體 206之側壁分別形成間隙壁220與間隙壁222，並在基底 200的主動區260與主動區270中分別形成源極/汲極區 224與源極/汲極區226。其中，較佳的間隙壁220與間隙 壁222之材質係與頂蓋層 216、218具有不同鈾刻率者， 其包括絕緣材料，較佳的例如是氧化矽、氮化矽或氮氧化 矽；而較佳的源極/汲極區224與源極/汲極區226係具有 輕摻雜汲極結構(LDD)者。典型的方法係先以閘極體204 與閘極體2〇6爲植入罩幕，進行離子植入製程，以在基底 2〇〇中形成輕摻雜源極/汲極區。之後，再於基底200上形 成一層絕緣層，其後，再經由非等向性回蝕刻的方式，使 留下的絕緣層在閘極體204與閘極體206之側壁分別形成 間隙壁22〇與間隙壁222。最後，再以閘極體204、閘極 .體206、間隙壁220與間隙壁222爲植入罩幕，進行離子 植入步驟’以在基底200中形成重摻雜源極/汲極區，完 成源極/汲極區224與226之製作。接著，在基底200上 形成一層介電層2Z8，此介電層228之材質例如爲氧化 矽、硼磷矽玻璃（BPSG)等具有高介電常數者，其形成的方 法例如爲化學氣相沈積法，所沈積的厚度約爲 4000A〜8000A 左右。 • 接著’請參照第2B圖，將介電層228平坦化，直到 裸露出頂蓋層216與218。較佳的，係以與介電層228亘 有不同硏磨速率之頂蓋層216與頂蓋層218爲硏磨終止 層，透過化學機械硏磨製程，以使介電層228平坦化，並 8 本紙張尺度適用中國國家標準（CNS ) A4規格（2I0X297公釐） "一"--—- 1 ^- n J— m —-1 - -- (請先閲讀背面之注意事項再填寫本頁) -訂 iot A7 B7 3660TWF.DOC/002 五、發明説明（) 裸露出頂蓋層216與頂蓋層218之表面。更加的，可以過 度硏磨介電層2M，或以回蝕刻的方式，以爲確保頂蓋層 216與頂蓋層218之表面可以裸露出來。 其後’請參照第2C圖，定義並去除部份的介電層 228 ’以及閘極體206其側壁23〇之間隙壁222,以形成開 口 232 ’此開口 232裸露出源極/汲極區226以及閘極體 206之側壁230，其包括部份的閘極氧化層210、複晶矽閘 極層214與頂蓋層218。典型的方法，可以在基底2〇〇上 形成圖案化的光阻層’以覆蓋欲形成局部內連線以外的區 域，其後，再以濕式蝕刻法去除未被光阻層覆蓋、欲形成 局部內連線區域之介電層228，接著，再將光阻層剝除， 並以濕式蝕刻法去除閘極體206其側壁230之間隙壁 222，而形成裸露出源極/汲極區2%以及閘極體206之側 壁230的開口 232。當間隙壁222與介電層228具有相同 之蝕刻率時，則可在去除介電層230的同時去除間隙壁 112。 然後，請參照第2D圖’去除頂蓋層216與頂蓋層 218，以形成裸露出複晶矽閘極層212之開口 234，並使開 口 232轉爲裸露出複晶矽閘極層214之表面與側壁、閘極 氧化層210之側壁以及裸露出源極/汲極區226的局部內 連線開口 236。當頂蓋層216、218與介電層228具有不同 蝕刻率時，較佳的可以採用濕式飩刻的方式，例如以熱磷 酸爲蝕刻劑以去除之。其後’在基底200上形成一層導體 層240，以塡滿開口 234與局部內連線開口 236。導體層 9 本紙張尺度適用中國國家標準（CNS ) A4規格（2!〇X297公® ) - ^ (請先閲請背面之注意事項再填寫本頁) 、一一9I Printed by A7, 1 3660TWF.DOC / 002 B7 of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention The partition wall 220 and the partition wall 222 form a source / drain region 224 and a source / drain region 226 in the active region 260 and the active region 270 of the substrate 200, respectively. Among them, the preferred materials for the spacers 220 and 222 have different uranium engraving rates from the capping layers 216 and 218, and they include insulating materials, preferably silicon oxide, silicon nitride, or silicon oxynitride; The preferred source / drain regions 224 and 226 have a lightly doped drain structure (LDD). A typical method is to first use the gate body 204 and the gate body 206 as implant masks, and perform an ion implantation process to form a lightly doped source / drain region in the substrate 200. After that, an insulating layer is formed on the substrate 200, and then the remaining insulating layers are formed into gap walls 22 on the side walls of the gate body 204 and the gate body 206 through anisotropic etchback. With a spacer 222. Finally, the gate body 204, the gate body 206, the spacer 220 and the spacer 222 are used as implant masks, and an ion implantation step is performed to form a heavily doped source / drain region in the substrate 200. The production of the source / drain regions 224 and 226 is completed. Next, a dielectric layer 2Z8 is formed on the substrate 200. The material of the dielectric layer 228 is, for example, silicon oxide, borophosphosilicate glass (BPSG), etc., which has a high dielectric constant. The formation method is, for example, chemical vapor deposition. Method, the deposited thickness is about 4000A ~ 8000A. • Next, please refer to FIG. 2B to planarize the dielectric layer 228 until the top cap layers 216 and 218 are exposed. Preferably, the capping layer 216 and the capping layer 218 having different honing rates from the dielectric layer 228 are used as honing termination layers, and the dielectric layer 228 is flattened by a chemical mechanical honing process, and 8 This paper size applies to China National Standard (CNS) A4 specification (2I0X297 mm) " 一 " ----- 1 ^-n J— m —-1--(Please read the notes on the back before filling (This page)-Order iot A7 B7 3660TWF.DOC / 002 V. Description of the invention () Exposed the surfaces of the top cover layer 216 and the top cover layer 218. Furthermore, the dielectric layer 2M may be over-honed or etched back to ensure that the surfaces of the capping layer 216 and the capping layer 218 can be exposed. Thereafter, please refer to FIG. 2C to define and remove a part of the dielectric layer 228 and the spacer 222 of the side wall 23 of the gate body 206 to form an opening 232. This opening 232 exposes the source / drain region. 226 and the side wall 230 of the gate body 206 include a portion of the gate oxide layer 210, a polycrystalline silicon gate layer 214, and a cap layer 218. In a typical method, a patterned photoresist layer 'can be formed on the substrate 200 to cover the area other than the local interconnects to be formed, and then, wet etching is used to remove the photoresist layer that is not covered by the photoresist layer and is to be formed. The dielectric layer 228 in the local interconnect region is then stripped off, and the spacer 222 of the side wall 230 of the gate body 206 is removed by wet etching to form an exposed source / drain region. 2% and the opening 232 of the side wall 230 of the gate body 206. When the spacer 222 and the dielectric layer 228 have the same etching rate, the spacer 112 can be removed at the same time as the dielectric layer 230 is removed. Then, please refer to FIG. 2D 'remove the top cap layer 216 and the top cap layer 218 to form an opening 234 exposing the polycrystalline silicon gate layer 212, and turn the opening 232 into exposing the polycrystalline silicon gate layer 214. The surface and the sidewalls, the sidewalls of the gate oxide layer 210, and the local interconnect openings 236 exposing the source / drain regions 226 are exposed. When the capping layers 216, 218 and the dielectric layer 228 have different etch rates, it is preferable to use wet etching, for example, using hot phosphoric acid as an etchant to remove them. Thereafter, a conductive layer 240 is formed on the substrate 200 to fill the openings 234 and the partial interconnect openings 236. Conductor layer 9 This paper size applies Chinese National Standard (CNS) A4 specification (2! 〇X297 公 ®)-^ (Please read the precautions on the back before filling this page), 1-9
T 經濟部中央標準局員工消費合作社印製T Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economy
I A7 B7 3660TWF.DOC/002 五、發明説明（？） 240之材質包括金屬，較佳的材質例如爲金屬鎢或金屬 銅’其形成方法可以採用化學氣相沈積法、濺鍍法或電鍍 法。當導體層240爲金屬材質時，較佳的，在形成導體餍 240之· ’可以在基底2〇〇上先形成一層黏著層/阻障層 238 ’以避免金屬材質的導電層240與複晶矽閘極層212 或214產生交互擴散作用，並可增加其彼此之間的附著 性。典型的阻障層/黏著層238係選自於鈦、氮化鈦、氮化 鎢、氮矽化鎢、鉅以及氮化組所組成之族群。當導電層240 之材質爲鎢金屬時，較佳的阻障層/黏著層238包括鈦、氮 化鈦、氮化鎢與氮矽化鎢所組成之族群。當導電層240之 材質爲銅金屬時，較佳的阻障層/黏著層238則包括鉬以及 氮化鉅所組成之族群。 之後「請參照第2E圖，進行平坦化製程，以去除覆 蓋於介電層228上方之導電層240與阻障層/黏著層238, 使留在開口 234之導體層240a與阻障層/黏著層238a形成 與複晶矽閘極層2U電性耦接的導體閘極層242 ;並使得 留在局部內連線開口 236的導體層240b與阻障層/黏著層 238b形成電性耦接複晶矽閘極層214與源極/汲極區226 的局部內連線244。較佳的平坦化製程係以化學機械硏磨 法，硏磨導體層24〇，直到裸露出阻障層/黏著層238之表 面，其後，再以濕式蝕刻法以去除覆蓋於介電層2M上方 之阻障層/黏著層238。 由於本發明之導體閘極層242與局部內連線244均可 以採用金屬材質以形成之，因此，可以增加閘極與局部內 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 *> I _ - - _ - - I ^^1、一"§J- - - I - - 1^1 1^1 I- -I I--- -i -- I - - I n - 1^1 n 經濟部中央標準局員Η消費合作社印製 ί:,'§ηΜΤ~~[ 3660TWF.DOC/002 D. D / 五、發明説明（?） 連線之導電性’而提昇元件之執行效能。而且，由於導體 閘極層242與局部內連線244係在基底200上形成一層導 體層240之後，再經由化學機械平坦化以同時形成者，因 此，可以避免在前期製程，因蝕刻金屬層對酸槽所造成之 污染。 其後，請繼續參照第2E圖，在基底200上形成另一層 介電層246，並於介電層246上形成一層終止層248。介電 層246之材質例如爲氧化矽、硼磷矽玻璃等具有高介電常 數者，其形成的方法例如爲化學氣相沈積法，所沈積的厚 度約爲4000A〜8000A左右。而終止層248之材質係與介 電層具有不同蝕刻率、且可以作爲微影之抗反射層（anti-reflectionlayer)者，其較佳的材質例如爲氮化矽或氮氧化 矽，形成的方法例如爲化學氣相沈積法。 繼之，請參照第2F圖，定義介電層246與介電層228， 以形成裸露出源極/汲極區224之接觸窗開口 250。典型的 方法係以終止層248爲抗反射層，在基底200上先形成一 層圖案化的光阻層，其後，再以光阻層爲罩幕’鈾刻抗反 射層248、介電層246與介電層228，以形成裸露出源極/ 汲極區224之接觸窗開口 250。其後，再進行後續之製程。 由於後續之製程爲熟習此技藝者所熟知，且非關本發明之 特徵，於此不再贅述。 綜上所述，本發明的特徵在於本發明之半導體元件的 製造方法，係在基底上形成導體層之後’再經由化學機械 平坦化製程，以使閘極導體層與局部內連線在同一步驟完 本紙張尺度適用中國國家標準（CNS ) Α4規格（2l〇X297公釐） (請先閲讀背面之注意事項再填寫本頁) -m nn (UK ml • 1^1 i HI 1^1 n n^i 1^1 -- 1· I - - ml-'·1 -- · i^— A7 B7 3660丁 WF.DOC/002 五、發明説明（P) 成。此方法可以避免在前期製程，因蝕刻金屬層對酸槽所 造成之污染。而且可以提高閘極之導電性、增加執行之效 能，並可避免習知爲減少源極/汲極區以及閘極之片電 阻，採用自動對準矽化物製程，在積體電路高度積集化之 後所造成的限制。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填寫本頁) •裝· 訂 .丨〕 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）I A7 B7 3660TWF.DOC / 002 V. Description of the invention (?) The material of 240 includes metal. The preferred material is, for example, metal tungsten or metal copper. Its formation method can be chemical vapor deposition, sputtering or electroplating. . When the conductive layer 240 is made of a metal material, it is preferable to form a conductive layer 240 on the substrate 2000. 'An adhesive layer / barrier layer 238 can be formed on the substrate 2000' to avoid the conductive layer 240 and the polycrystalline material made of metal. The silicon gate layers 212 or 214 generate an interdiffusion effect and increase their adhesion to each other. A typical barrier layer / adhesive layer 238 is selected from the group consisting of titanium, titanium nitride, tungsten nitride, tungsten silicide, giant, and nitride. When the material of the conductive layer 240 is tungsten metal, the preferred barrier layer / adhesive layer 238 includes a group consisting of titanium, titanium nitride, tungsten nitride, and tungsten silicide. When the material of the conductive layer 240 is copper metal, the preferred barrier layer / adhesive layer 238 includes molybdenum and a nitride group. After that, please refer to FIG. 2E to perform a planarization process to remove the conductive layer 240 and the barrier layer / adhesive layer 238 covering the dielectric layer 228, so that the conductor layer 240a and the barrier layer / adhesion layer that remain in the opening 234 The layer 238a forms a conductive gate layer 242 electrically coupled to the polycrystalline silicon gate layer 2U; and the conductive layer 240b and the barrier layer / adhesive layer 238b remaining in the local interconnect openings 236 form an electrically coupled layer The crystalline silicon gate layer 214 and the local interconnects 244 of the source / drain regions 226. A preferred planarization process is a chemical mechanical honing method, which hones the conductive layer 24 until the barrier layer / adhesion is exposed. The surface of the layer 238 is then wet-etched to remove the barrier layer / adhesive layer 238 overlying the dielectric layer 2M. As the conductive gate layer 242 and local interconnects 244 of the present invention can be used The metal material is used to form it. Therefore, the gate electrode and the local paper size can be increased. The Chinese paper standard (CNS) A4 (210X297 mm) is applicable. (Please read the precautions on the back before filling this page.) Central Bureau of Standards, Ministry of Economic Affairs Printed by Employee Consumer Cooperatives * > I _--_--I ^^ 1 " §J---I--1 ^ 1 1 ^ 1 I- -I I --- -i-I--I n-1 ^ 1 n Printed by a member of the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives: , '§ΗΜΤ ~~ [3660TWF.DOC / 002 D. D / V. Description of the invention (?) Conductivity of the connection' to improve the performance of the component. Moreover, because the conductor gate layer 242 and the local interconnects 244 After a conductive layer 240 is formed on the substrate 200, it is simultaneously formed by chemical mechanical planarization. Therefore, it is possible to avoid contamination caused by the etching of the metal layer to the acid tank in the previous process. After that, please continue to refer to In FIG. 2E, another dielectric layer 246 is formed on the substrate 200, and a termination layer 248 is formed on the dielectric layer 246. The material of the dielectric layer 246 is, for example, silicon oxide, borophosphosilicate glass, or the like having a high dielectric constant. The formation method is, for example, a chemical vapor deposition method, and the deposited thickness is about 4000A to 8000A. The material of the termination layer 248 is different from that of the dielectric layer, and can be used as an anti-reflection layer of lithography ( anti-reflectionlayer), the preferred material is, for example, silicon nitride or silicon oxynitride. The method is, for example, a chemical vapor deposition method. Next, referring to FIG. 2F, the dielectric layer 246 and the dielectric layer 228 are defined to form a contact window opening 250 that exposes the source / drain regions 224. A typical method is With the stop layer 248 as the anti-reflection layer, a patterned photoresist layer is first formed on the substrate 200, and then the photoresist layer is used as a mask. The uranium-etched anti-reflection layer 248, the dielectric layer 246, and the dielectric layer 228 to form a contact window opening 250 that exposes the source / drain regions 224. After that, the subsequent processes are performed. Since subsequent processes are well known to those skilled in the art and are not related to the features of the present invention, they will not be repeated here. To sum up, the present invention is characterized in that the method for manufacturing a semiconductor device of the present invention is to form a conductive layer on a substrate, and then go through a chemical mechanical planarization process so that the gate conductive layer and the local interconnects are in the same step. At the end of this paper, the Chinese National Standard (CNS) Α4 size (2l0 × 297mm) is applicable (please read the precautions on the back before filling this page) -m nn (UK ml • 1 ^ 1 i HI 1 ^ 1 nn ^ i 1 ^ 1-1 · I--ml- '· 1-· i ^ — A7 B7 3660 D WF.DOC / 002 5. Description of the invention (P). This method can avoid the early process due to etching Pollution caused by the metal layer on the acid tank. It can improve the conductivity of the gate and increase the performance of the implementation, and can avoid the conventional use of self-aligned silicide to reduce the source / drain region and the gate resistance of the gate. The limitation of the manufacturing process after the integration of the integrated circuit is highly. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the present invention. Within the spirit and scope, it can be modified and retouched Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the notes on the back before filling out this page) • Binding and binding. 丨] Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X297 mm)