經濟部智慧財產局員工消费合作社印製 ’η，41她、3 7 6 Α7 Ά./ 6260twf.doc/008 β7 五、發明說明（I > 本發明是有關於一種靜電放電（Electro-Static Discharge : ESD)保護電路的製造方法，且特別是有關於一 種可應用自行對準金屬矽化物（Self-Aligned Silicide ; Salicide)製程之靜電放電保護電路的製造方法。 在積體電路（1C)的製造過程中或是晶片完成後，靜電 放電事件常是導致積體電路損壞的主要原因。例如行動的 人體，於相對濕度（RH)較高的情況下可檢測出約帶有幾百 至幾千伏的靜態電壓，然而於相對濕度較低的情況下則可 檢測出約帶有一萬伏以上的靜態電壓。當這些帶電體接觸 到晶片時，將會向晶片放電，結果有可能造成晶片失效。 於是，爲了避免靜電放電損傷晶片，各種防制靜電放電的 方法便因應而生。最常見的習知作法是利用硬體防制靜電 放電，也就是在內部電路（Internal Circuit)與每一焊墊（Pad) 間，均設計一靜電放電保護電路以保護其內部電路。 一般在靜電放電保護元件的製程上，若是要應用自動 金屬矽化物的製程時，習知利用包覆設計(SaHcide block 方式，以避免在包覆端上形成金屬矽化物，而包 覆^|^>方式例如爲僅包覆（Block)汲極端，或包覆汲極與 閘極端，'或將汲極、源極與閘極端均包覆住。 請參照第1A圖至第1D圖，其所繪示的爲習知一種靜電 放電保護電路的製造流程剖面示意圖。 請參照第1A圖，提供一基底100，在基底100上形 成淺溝渠隔離結構102以定義出元件主動區與保護電 路區106，且因前段製程之多次蝕刻步驟，使得此淺溝渠 參紙張尺度遶用中Η國家標準（CNS)A4规格（210 X 297公釐> ------------Θ裝--------訂---------線〕. (請先Μ讀f面之注意事項再填寫本頁) 4 44 6 6260twf.doc/008 A7 B7 五、發明說明（ —— — — — — — — II — — I— · I I (請先《讀背面之注意事項再填寫本頁) 隔離結構102之頂端邊角處（top corner)產生有邊緣凹陷 (recess) 102a。並且在元件主動區丨〇4與保護電路區106 分別形成有第一金氧半電晶體與第二金氧半電晶體。第一 金氧半電晶體包括閘極氧化層112、閘極114、間隙壁116 以及源極/汲極區118、120(包括N+離子摻雜區與N-離子 摻雜區）。第二金氧半電晶體包括閘極氧化層122、閘極 124、間隙壁126以及源極/汲極區128、130(包括N+離子 摻雜區與N-離子摻雜區）。 請參照第1B圖’在基底1〇〇上形成一層厚度約爲 100-1000埃的氧化物層132，覆蓋元件主動區104與保護 電路區106。接著’在氧化層132上形成一圖案化之光阻 層134，而圖案化之光阻層134覆蓋住保護電路區106之 閘極124、汲極區130上之氧化層132，而暴露出保護電 路區106之源極區128上方以及元件主動區104的氧化物 層 132。 练· 經濟部智慧財產局員工消费合作杜印製 請參照第1C圖，以光阻層134爲罩幕，非等向性蝕 刻氧化層132 ’直至暴露出基底100爲止，並繼續進行過 度蝕刻（Over Etching)步驟，以去除殘餘之氧化層132， 而此過蝕刻步驟會加深淺溝渠隔離結構102之頂端邊角處 的邊緣凹陷102a現象。然後去除光阻層134。 請參照第1D圖，進行一自行對準金屬矽化物製程， 使得沉積的金屬層（未繪示於圖中）與暴露出的矽材反應， 而在元件主動區104的閘極114、源極區118與汲極區120 以及保護電路區106之源極區128上分別形成一層矽化金 4 本紙張尺度適用中國S家標準（CNS)A4蜒格（210 X 297公»〉 經濟部智慧財產局員工消費合作社印製 、444376 A7 6260twf. doc/008 R7 五、發明說明（勹） 屬層136、138 ' 140、142。由於源極區118上之矽化金屬 層138與源極區128上的矽化金屬層142會沿著淺溝渠隔 離結構的邊緣凹陷處l〇2a之基底100表面形成，使得矽 化金屬層〗38、142分別與源極區118、128下方之基底100 相距很近，易產生接面漏電(junction leakage)現象。 在上述自行對準金屬矽化物製程中，矽化金屬層會形 成在淺溝渠隔離結構的邊緣凹陷處之基底表面，因而易發 生接面漏電現象。 因此本發明提供一種靜電放電保護電路的製造方法， 避免在淺溝渠隔離結構的邊緣凹陷處形成矽化金屬層，以 改善習知的接面漏電問題。 根據本發明之上述及其他目的，提出一種靜電放電保 護電路的製造方法。首先，提供一基底，此基底上形成有 淺溝渠隔離結構，以定義出元件主動區與保護電路區，且 因前段製程之多次蝕刻步驟，使得此淺溝渠隔離結構之頂 端邊角處產生有邊緣凹陷。此元件主動區與保護電路區中 分別形成有第一金氧半電晶體與第二金氧半電晶體，而此 第一金氧半電晶體具有第一閘極、第一源極區與第一汲極 區，此第二閘極具有第二閘極、第二源極區與第二汲極區。 然後在基底i形成一層厚的絕緣層，再平坦化此絕緣層。 接者，在基底上形成圖案化之光阻層，此光阻層暴露出部 份保護電路區以及元件主動區上的絕緣層，且此光阻層至 少覆蓋住第二汲極區上的絕緣層。其次，以此光阻層爲罩 幕，去除暴露出之部份保護電路區以及元件主動區上的絕 5 本紙張尺度適用中困國家標準（CNS)A4规格（210 χ 297公釐} (請先閱讀背面之注意事項再填寫本頁) 訂. 444376 A7 6260twf.doc/Q08_B7_ 五、發明說明（0 ) (請先閲讀背面之注意事項再填寫本頁) 緣層，直至裸露出基底爲止。然後去除此光阻層，再進行 自行對準金屬矽化物製程，以在第一金氧半電晶體的第一 閘極、第一源極區與第一汲極區上各自形成矽化金屬層， 並在暴露出之部份保護電路區的第二金氧半電晶體上形成 自行對準矽化金屬層。 依照本發明所提出之一種靜電放電保護電路的製造方 法，其係在基底上形成一層厚的絕緣層，以塡滿淺溝渠隔 離結構頂端邊角處的邊緣凹陷，再平坦化此絕緣層，而此 時淺溝渠隔離結構之頂端邊角處的邊緣凹陷已塡滿，因而 在後續之自行對準金屬矽化物製程中矽化金屬層僅形成在 基底上，可降低接面漏電現象。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖至第1D圖所繪示爲習知靜電放電保護電路的 製造流程剖面示意圖；以及 經濟部智慧財產局員工消費合作社印製 第2A圖至第2D圖所繪示爲依照本發明之較佳實施 例，一種靜電放電保護電路的製造流程剖面示意圖。 圖式之標記說明： 100、200 :基底 102、202 :淺溝渠隔離結構 104、204 :元件主動區 106 ' 206 :保護電路區 6 本紙張尺度適用中困國家標準（CNS)A4规格（210 X 297公釐）""' 經濟部智慧財產局貝工消费合作社印製 444376 A7 6260twf.doc/008_β7_ 五、發明說明（6 ) 1 12、122 ' 212、222 :閘極氧化層 114、124、214、224 :閘極 116、126、216、226 :間隙壁 118、128、218、228 :源極區 120、130、220、230 :汲極區 132、232 :絕緣層 134、234 :圖案化之光阻層 136、138、140、142、236、238、240、242 :矽化金 屬層 官施例 請參照第2A圖至第2D圖，其所繪示的即是依照本發 明之較佳實施例，一種靜電放電保護電路的製造流程剖面 示意圖。 請參照第2A圖，提供一基底200，在基底200上形 成有淺溝渠隔離結構202以定義出元件主動區204與保護 電路區206，且因前段製程之多次蝕刻步驟，使得此淺溝 渠隔離結構202之頂端邊角處產生了邊緣凹陷處202a。並 且在元件主動區204與保護電路區206分別形成有第一金 氧半電晶體與第二金氧半電晶體。第一金氧半電晶體包括 閘氧化層212、閘極214、間隙壁216以及源極/汲極區218、 220 (包括N+離子摻雜區與N-離子摻雜區）。第二金氧半電 晶體206包括閘氧化層222、閘極224、間隙壁226以及 源極/汲極區228、230(包括N+離子摻雜區與N-離子摻雜 區）。 7 本紙張尺度適用中困國家標準<CNS>A4_规格（210 * 297公釐) -- - ---------)裝- - ------訂---------線〕· {請先閱讀背面之注意事項再填窝本頁) 4443 7 b A7 6260twf.doc/008 _ β7_ 五、發明說明（“） <請先閱讀背面之注$項再填寫本頁> 請參照第2B圖’在基底200上形成一層絕緣層232。 絕緣層232較佳的是氧化層，例如未摻雜之二氧化矽層 (undoped Si02)，其形成之方法例如爲化學氣相沈積法，其 沉積的較佳厚度約爲5000-10000埃之間。絕緣層232覆蓋 元件主動區204以及保護電路區206。接者，平坦化此絕 緣層232，而其平坦之方法例如爲化學機械硏磨法。在絕 緣層232上形成一圖案化之光阻層234，此圖案化之光阻 層234覆蓋住保護電路區206之閘極224、汲極區230上 之絕緣層232，而暴露出保護電路區206之源極區228上 方以及元件主動區204上方的絕緣層232 » 請參照第2C圖，以光阻層234爲罩幕，去除絕緣層 232，直至暴露出基底200爲止，並繼續進行過度飽刻步 驟，以去除殘餘之絕緣層232，而淺溝渠隔離結構202頂 端邊角處邊緣凹陷202a已塡滿絕緣層232。其中去除絕緣 層232之方法例如爲反應性離子蝕刻法，且絕緣層232之 蝕刻速率遠大於間隙壁216、226之蝕刻速率。然後去除 光阻層234，而去除之方法例如以氧電漿灰化法（〇2 plasma ashing)搭配溶劑移除法（solvent removal)。Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs '41, 41, 3 7 6 Α7 Ά. / 6260twf.doc / 008 β7 V. Description of the Invention (I > The present invention relates to an electrostatic discharge (Electro-Static Discharge : ESD) protection circuit manufacturing method, and more particularly, it relates to a method for manufacturing an electrostatic discharge protection circuit capable of applying self-aligned silicide (Salicide) process. Manufacturing in integrated circuit (1C) During or after the wafer is completed, electrostatic discharge events are often the main cause of damage to integrated circuits. For example, a human body that moves can detect a few hundred to several thousand volts under relatively high relative humidity (RH). The static voltage can be detected under the condition of relatively low relative humidity. When the charged body contacts the wafer, it will discharge to the wafer, which may cause the wafer to fail. Therefore, in order to prevent the electrostatic discharge from damaging the wafer, various methods for preventing electrostatic discharge have been developed. The most common practice is to use hardware to prevent electrostatic discharge. That is, an electrostatic discharge protection circuit is designed between the internal circuit and each pad to protect its internal circuit. Generally, in the process of electrostatic discharge protection components, if an automatic metal silicide process is to be applied In the past, it is known to use a cladding design (SaHcide block method to avoid the formation of metal silicide on the cladding end, and the cladding method ^ | ^ > is, for example, only covering the (Block) drain terminal or covering the drain terminal With the gate terminal, or cover the drain, source, and gate terminals. Please refer to Figures 1A to 1D, which are cross-sectional schematic diagrams showing the manufacturing process of a conventional electrostatic discharge protection circuit. Please Referring to FIG. 1A, a substrate 100 is provided, and a shallow trench isolation structure 102 is formed on the substrate 100 to define an element active area and a protection circuit area 106. Due to the multiple etching steps of the previous process, the shallow trench is referenced to a paper scale. Use the China National Standard (CNS) A4 specification (210 X 297 mm > ------------ Θ equipment -------- order --------- (Line). (Please read the notes on f before filling in this page) 4 44 6 6260twf.doc / 008 A7 B7 Instructions (—— — — — — — — — II — — I — · II (please read the “Notes on the back side before filling out this page”) There is a recess in the top corner of the isolation structure 102 102a. A first metal-oxide-semiconductor and a second metal-oxide-semiconductor are formed in the element active region 104 and the protection circuit region 106, respectively. The first metal-oxide semiconductor includes a gate oxide layer 112, a gate 114, a spacer 116, and source / drain regions 118 and 120 (including N + ion-doped regions and N-ion-doped regions). The second metal-oxide semiconductor includes a gate oxide layer 122, a gate 124, a spacer 126, and source / drain regions 128 and 130 (including N + ion-doped regions and N-ion-doped regions). Referring to FIG. 1B ', an oxide layer 132 having a thickness of about 100-1000 Angstroms is formed on the substrate 100 to cover the active region 104 and the protective circuit region 106 of the device. Next, a patterned photoresist layer 134 is formed on the oxide layer 132, and the patterned photoresist layer 134 covers the gate 124 of the protection circuit region 106 and the oxide layer 132 on the drain region 130 to expose protection. An oxide layer 132 above the source region 128 of the circuit region 106 and the active region 104 of the device. The consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs, Du printed, please refer to Figure 1C, using the photoresist layer 134 as a mask, and anisotropically etch the oxide layer 132 'until the substrate 100 is exposed, and continue to over-etch ( Over Etching) step to remove the residual oxide layer 132, and this over-etching step will deepen the edge depression 102a phenomenon at the top corners of the shallow trench isolation structure 102. The photoresist layer 134 is then removed. Referring to FIG. 1D, a self-aligned metal silicide process is performed, so that the deposited metal layer (not shown in the figure) reacts with the exposed silicon material, and the gate 114 and the source of the active area 104 of the device A layer of silicided gold is formed on the region 118, the drain region 120, and the source region 128 of the protection circuit region 106. The paper size is applicable to China Standards (CNS) A4 Zigzag (210 X 297) »> Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative, 444376 A7 6260twf. Doc / 008 R7 V. Description of the invention (勹) The metal layers 136, 138 '140, 142. Due to the silicided metal layer 138 on the source region 118 and the silicide on the source region 128 The metal layer 142 will be formed along the surface of the substrate 100 at the edge recess of the shallow trench isolation structure 102a, so that the silicided metal layer 38 and 142 are close to the substrate 100 below the source regions 118 and 128, respectively, and it is easy to make contact. Surface leakage (junction leakage) phenomenon. In the above self-aligned metal silicide process, a silicided metal layer will be formed on the substrate surface of the edge depression of the shallow trench isolation structure, so junction leakage is prone to occur. Therefore, the present invention provides A method for manufacturing an electrostatic discharge protection circuit avoids the formation of a silicided metal layer at the edge recess of a shallow trench isolation structure to improve the conventional junction leakage problem. According to the above and other objectives of the present invention, an electrostatic discharge protection circuit is proposed. Manufacturing method. First, a substrate is provided, and a shallow trench isolation structure is formed on the substrate to define an active area of a component and a protection circuit area. The top corners of the shallow trench isolation structure are caused by multiple etching steps in the previous process. There are edge recesses. A first metal-oxide semiconductor and a second metal-oxide semiconductor are formed in the active area and the protection circuit area of the device, respectively. The first metal-oxide semiconductor has a first gate electrode, a first A source region and a first drain region, and the second gate has a second gate, a second source region, and a second drain region. Then, a thick insulating layer is formed on the substrate i, and the insulation is planarized. Then, a patterned photoresist layer is formed on the substrate, and the photoresist layer exposes a part of the protection circuit area and the insulating layer on the active area of the component, and the photoresist layer at least covers The insulating layer on the second drain region is used. Secondly, the photoresist layer is used as a mask to remove the exposed part of the protection circuit area and the insulation on the active area of the component. A4 specification (210 χ 297 mm) (Please read the notes on the back before filling this page) Order. 444376 A7 6260twf.doc / Q08_B7_ V. Description of the invention (0) (Please read the notes on the back before filling this page ) Edge layer until the substrate is exposed. Then remove the photoresist layer and then perform a self-aligned metal silicide process to place the first gate, first source region and first A silicide metal layer is formed on each of the drain regions, and a self-aligned silicide metal layer is formed on the exposed second metal-oxide-semiconductor crystal of the protection circuit region. According to a method for manufacturing an electrostatic discharge protection circuit according to the present invention, a thick insulating layer is formed on a substrate, so that edges at the top corners of a shallow trench isolation structure are recessed, and then the insulating layer is planarized, and At this time, the edge recesses at the top corners of the shallow trench isolation structure are full, so the silicide metal layer is only formed on the substrate in the subsequent self-aligned metal silicide process, which can reduce the leakage of the junction. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A to Figure 1D shows a schematic cross-sectional schematic diagram of the manufacturing process of a conventional electrostatic discharge protection circuit; and Figures 2A to 2D printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs show the preferred embodiments according to the present invention. A schematic sectional view of a manufacturing process of an electrostatic discharge protection circuit. Description of drawing symbols: 100, 200: substrate 102, 202: shallow trench isolation structure 104, 204: component active area 106 '206: protection circuit area 6 This paper standard applies to the National Standard for Difficulties (CNS) A4 (210 X 297 mm) " " 'Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 444376 A7 6260twf.doc / 008_β7_ V. Description of the invention (6) 1 12, 122' 212, 222: Gate oxide layers 114, 124 , 214, 224: Gates 116, 126, 216, 226: Spacers 118, 128, 218, 228: Source regions 120, 130, 220, 230: Drain regions 132, 232: Insulating layers 134, 234: Patterns Chemical photoresist layers 136, 138, 140, 142, 236, 238, 240, 242: For examples of silicided metal layers, please refer to Figures 2A to 2D, which are shown in accordance with the present invention. The embodiment is a schematic sectional view of a manufacturing process of an electrostatic discharge protection circuit. Referring to FIG. 2A, a substrate 200 is provided. A shallow trench isolation structure 202 is formed on the substrate 200 to define an active region 204 and a protection circuit region 206 of the element. The shallow trench is isolated due to multiple etching steps in the previous process. An edge depression 202 a is generated at the top corner of the structure 202. A first metal-oxide-semiconductor and a second metal-oxide-semiconductor are formed in the element active region 204 and the protection circuit region 206, respectively. The first metal-oxide semiconductor includes a gate oxide layer 212, a gate electrode 214, a spacer 216, and source / drain regions 218, 220 (including N + ion-doped regions and N-ion-doped regions). The second metal-oxide semiconductor 206 includes a gate oxide layer 222, a gate electrode 224, a spacer 226, and source / drain regions 228, 230 (including N + ion-doped regions and N-ion-doped regions). 7 This paper size is applicable to the national standard of medium and low < CNS > A4_ specifications (210 * 297 mm)-----------) installed------- order ---- ----- Line] · {Please read the notes on the back before filling in this page) 4443 7 b A7 6260twf.doc / 008 _ β7_ 5. Description of the invention (“) < Please read the note on the back first Fill in this page again> Please refer to FIG. 2B to form an insulating layer 232 on the substrate 200. The insulating layer 232 is preferably an oxide layer, such as an undoped silicon dioxide layer (undoped Si02), and a method for forming the same For example, the chemical vapor deposition method has a preferable thickness of about 5000-10000 angstroms. The insulating layer 232 covers the active region 204 and the protection circuit region 206 of the device. Then, the insulating layer 232 is planarized, and the planarization is flat. The method is, for example, a chemical mechanical honing method. A patterned photoresist layer 234 is formed on the insulating layer 232, and the patterned photoresist layer 234 covers the gate 224 and the drain region 230 on the protection circuit region 206. The insulating layer 232 exposes the insulating layer 232 above the source region 228 of the protection circuit region 206 and above the device active region 204 »Please refer to FIG. 2C for the photoresist layer 234 For the mask, the insulating layer 232 is removed until the substrate 200 is exposed, and the oversaturation step is continued to remove the remaining insulating layer 232. The edge recesses 202a at the top corners of the shallow trench isolation structure 202 have been filled with the insulating layer. 232. The method for removing the insulating layer 232 is, for example, a reactive ion etching method, and the etching rate of the insulating layer 232 is much higher than that of the spacers 216 and 226. Then, the photoresist layer 234 is removed, and the removal method is, for example, oxygen electricity The 02 ashing method is combined with a solvent removal method.
經濟部智慧財產局貝工消费合作杜印M 請參照第2D圖，在基底200上沉積一層金屬層（未 繪示於圖中），而金屬層之材質例如爲鈦，再進行快速加 熱製程(rapid thermal processing)，使得沉積的金屬層與暴 露出的矽材反應，而在元件主動區204的閘極2〗4、源極 區218與汲極區220以及保護電路區206之源極區228上 分別形成自行對準矽化金屬層236，238、240、242。自行 8 本紙張尺度適用中困困家櫟準（CNS>A4慧格（210 X 297公釐） 4443 76 6260twf.d〇c/〇〇8 五、發明說明（1) {靖先閱讀背面之注f項再填寫本頁) 對準矽化金屬層236 ' 238、240、242之材質例如爲矽化 鈦。然後去除未參與反應或反應後所剩餘的的金屬鈦、氮 化鈦與氧化鈦。去除之方法例如爲使用氫氧化銨(NH4OH)、 過氧化氫出2〇2)以及熱去離子水（hot de-ionization water, HDIW)等成份組成的RCA溶液爲蝕刻劑之濕式蝕刻法。 在本發明之較佳實施例中，絕緣層包覆住保護電路區 之汲極區與閘極。然而，本發明並不限於此，絕緣層可僅 包覆住保護電路區之汲極區，或完全包覆住保護電路區之 金氧半電晶體的源極區、汲極區與閘極。 經濟部智慧財產局貝工消费合作社印製 由上述本發明較佳實施例可知，本發明係在基底上形 成一層厚的絕緣層，以塡滿淺溝渠隔離結構頂端邊角的邊 緣凹陷處’再平坦化此絕緣層》之後，進行微影蝕刻製程， 以形成圖案化之絕緣層，而此圓案化之絕緣層包覆汲極區 與閘極’或僅包覆保護電路區之汲極區，或同時包覆保護 電路區之汲極區、源極區與閘極。然後在暴露出之金氧半 電晶體上形成自行對準金屬矽化物。本發明之靜電放電保 護電路製程可減輕淺溝渠隔離結構頂端邊角處之邊緣凹陷 現象，而可加大在後續之自行對準金屬矽化物製程中形成 在源極/汲極區上之矽化金屬層與源極/汲極區下方之基 底的距離，而改善接面漏電現象。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍內’當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準^ 9 本紙張尺度適用4Μ8Ϊ家梯準（CNS>A4規格（210 X 297公着) "Du Yin M, Shellfish Consumer Cooperation, Intellectual Property Bureau, Ministry of Economic Affairs Please refer to Figure 2D. A metal layer (not shown) is deposited on the substrate 200, and the material of the metal layer is, for example, titanium, and then a rapid heating process is performed ( rapid thermal processing), so that the deposited metal layer reacts with the exposed silicon material, and the gate 2 in the active region 204 of the device, the source region 218 and the drain region 220, and the source region 228 of the protection circuit region 206 Self-aligned silicide metal layers 236, 238, 240, and 242 are formed thereon. 8 This paper is suitable for the standard of the hard-to-find oak (CNS > A4 Huige (210 X 297 mm)) 4443 76 6260twf.d〇c / 〇〇8 V. Description of the invention (1) {Jing Xian read the note on the back (F-item, please fill in this page again) The material of the alignment silicide metal layer 236 '238, 240, 242 is, for example, titanium silicide. Then the metal titanium, titanium nitride and titanium oxide remaining after not participating in the reaction or after the reaction are removed. The removal method is, for example, a wet etching method using an RCA solution composed of ammonium hydroxide (NH4OH), hydrogen peroxide (202), and hot de-ionization water (HDIW) as an etchant. In a preferred embodiment of the present invention, the insulating layer covers the drain region and the gate of the protection circuit region. However, the present invention is not limited to this. The insulating layer may cover only the drain region of the protection circuit region, or completely cover the source region, the drain region, and the gate of the metal-oxide semiconductor transistor in the protection circuit region. Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. According to the above-mentioned preferred embodiments of the present invention, it is known that the present invention forms a thick insulating layer on the substrate to fill the edge depressions of the top corners of the shallow trench isolation structure After planarizing this insulating layer, a lithographic etching process is performed to form a patterned insulating layer, and the rounded insulating layer covers the drain region and the gate 'or only the drain region of the protection circuit region , Or cover the drain region, source region, and gate of the protection circuit region at the same time. A self-aligned metal silicide is then formed on the exposed gold-oxide semiconductor. The electrostatic discharge protection circuit manufacturing process of the present invention can reduce the edge sag phenomenon at the top corners of the shallow trench isolation structure, and can increase the silicide metal formed on the source / drain region in the subsequent self-aligned metal silicide process. The distance between the layer and the substrate below the source / drain region improves the junction leakage phenomenon. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. 'Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is subject to the definition of the scope of patent application attached hereafter. 9 This paper size is applicable to 4M8 standard (CNS > A4 specification (210 X 297)) "