TW290729B - - Google Patents

Info

Publication number
TW290729B
TW290729B TW084107112A TW84107112A TW290729B TW 290729 B TW290729 B TW 290729B TW 084107112 A TW084107112 A TW 084107112A TW 84107112 A TW84107112 A TW 84107112A TW 290729 B TW290729 B TW 290729B
Authority
TW
Taiwan
Application number
TW084107112A
Other languages
Chinese (zh)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW290729B publication Critical patent/TW290729B/zh

Links

Classifications

    • H10P95/00
    • H10W90/00
    • H10W70/60
    • H10W72/834
    • H10W90/20
    • H10W90/297
TW084107112A 1994-09-06 1995-07-10 TW290729B (OSRAM)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/301,290 US5596226A (en) 1994-09-06 1994-09-06 Semiconductor chip having a chip metal layer and a transfer metal and corresponding electronic module

Publications (1)

Publication Number Publication Date
TW290729B true TW290729B (OSRAM) 1996-11-11

Family

ID=23162741

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084107112A TW290729B (OSRAM) 1994-09-06 1995-07-10

Country Status (5)

Country Link
US (4) US5596226A (OSRAM)
EP (1) EP0701284A1 (OSRAM)
JP (1) JP3137565B2 (OSRAM)
KR (1) KR100187872B1 (OSRAM)
TW (1) TW290729B (OSRAM)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
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WO1998019337A1 (en) 1996-10-29 1998-05-07 Trusi Technologies, Llc Integrated circuits and methods for their fabrication
US6498074B2 (en) 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
US6882030B2 (en) * 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
US5793103A (en) * 1997-05-08 1998-08-11 International Business Machines Corporation Insulated cube with exposed wire lead
US6188062B1 (en) * 1998-04-08 2001-02-13 Hoetron, Inc. Laser/detector hybrid with integrated mirror and diffracted returned beam
US6211050B1 (en) * 1999-03-03 2001-04-03 Chartered Semiconductor Manufacturing Ltd. Fill pattern in kerf areas to prevent localized non-uniformities of insulating layers at die corners on semiconductor substrates
US6419554B2 (en) * 1999-06-24 2002-07-16 Micron Technology, Inc. Fixed abrasive chemical-mechanical planarization of titanium nitride
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6350625B1 (en) * 2000-12-28 2002-02-26 International Business Machines Corporation Optoelectronic packaging submount arrangement providing 90 degree electrical conductor turns and method of forming thereof
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US20030183943A1 (en) * 2002-03-28 2003-10-02 Swan Johanna M. Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6908845B2 (en) * 2002-03-28 2005-06-21 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6848177B2 (en) * 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6951801B2 (en) * 2003-01-27 2005-10-04 Freescale Semiconductor, Inc. Metal reduction in wafer scribe area
DE10324502B3 (de) * 2003-05-26 2005-04-21 Infineon Technologies Ag Photomaske, sowie Verfahren zur Herstellung von Halbleiter-Bauelementen
US7115997B2 (en) * 2003-11-19 2006-10-03 International Business Machines Corporation Seedless wirebond pad plating
ATE445231T1 (de) * 2004-07-26 2009-10-15 Nxp Bv Wafer mit verbesserten leitenden schleifen im ritzrahmen
DE102004058411B3 (de) * 2004-12-03 2006-08-17 Infineon Technologies Ag Halbleiterwafer mit einer Teststruktur und Verfahren
JP4934053B2 (ja) * 2005-12-09 2012-05-16 スパンション エルエルシー 半導体装置およびその製造方法
JP5675338B2 (ja) * 2007-04-04 2015-02-25 ネットバイオ・インコーポレーテッドNetBio, Inc. ターゲット核酸を急速に多重増幅するための方法
JP4815623B2 (ja) * 2007-09-07 2011-11-16 三菱電機株式会社 高周波受動素子およびその製造方法
US7964976B2 (en) * 2008-08-20 2011-06-21 Headway Technologies, Inc. Layered chip package and method of manufacturing same
WO2010147654A2 (en) 2009-06-15 2010-12-23 Netbio Inc. Improved methods for forensic dna quantitation
US8457920B2 (en) * 2010-05-28 2013-06-04 International Business Machines Corporation Performance improvement for a multi-chip system via kerf area interconnect
US9484316B2 (en) * 2013-11-01 2016-11-01 Infineon Technologies Ag Semiconductor devices and methods of forming thereof
US9583410B2 (en) 2014-03-21 2017-02-28 International Business Machines Corporation Volumetric integrated circuit and volumetric integrated circuit manufacturing method
US11183765B2 (en) 2020-02-05 2021-11-23 Samsung Electro-Mechanics Co., Ltd. Chip radio frequency package and radio frequency module
US11101840B1 (en) 2020-02-05 2021-08-24 Samsung Electro-Mechanics Co., Ltd. Chip radio frequency package and radio frequency module

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DE1212279B (de) * 1961-05-19 1966-03-10 Terrapin Overseas Ltd Gebaeude mit Platten, die zwischen Stuetzen verlaufende Waende bilden
DE1591105A1 (de) * 1967-12-06 1970-09-24 Itt Ind Gmbh Deutsche Verfahren zum Herstellen von Festkoerperschaltungen
US3859127A (en) * 1972-01-24 1975-01-07 Motorola Inc Method and material for passivating the junctions of mesa type semiconductor devices
JPS57154838A (en) * 1981-03-20 1982-09-24 Internatl Rectifier Corp Japan Ltd Chemical etching liquid for semiconductor silicon wafer
US4500905A (en) * 1981-09-30 1985-02-19 Tokyo Shibaura Denki Kabushiki Kaisha Stacked semiconductor device with sloping sides
JPS61288455A (ja) * 1985-06-17 1986-12-18 Fujitsu Ltd 多層半導体装置の製造方法
US5196378A (en) * 1987-12-17 1993-03-23 Texas Instruments Incorporated Method of fabricating an integrated circuit having active regions near a die edge
EP0393635B1 (en) * 1989-04-21 1997-09-03 Nec Corporation Semiconductor device having multi-level wirings
US5104820A (en) * 1989-07-07 1992-04-14 Irvine Sensors Corporation Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
JP2515408B2 (ja) * 1989-10-31 1996-07-10 株式会社東芝 バイポ−ラ型半導体装置
US5126231A (en) * 1990-02-26 1992-06-30 Applied Materials, Inc. Process for multi-layer photoresist etching with minimal feature undercut and unchanging photoresist load during etch
JP2978533B2 (ja) * 1990-06-15 1999-11-15 株式会社日立製作所 半導体集積回路装置
US5397916A (en) * 1991-12-10 1995-03-14 Normington; Peter J. C. Semiconductor device including stacked die
US5266833A (en) * 1992-03-30 1993-11-30 Capps David F Integrated circuit bus structure
US5259925A (en) * 1992-06-05 1993-11-09 Mcdonnell Douglas Corporation Method of cleaning a plurality of semiconductor devices
US5324687A (en) * 1992-10-16 1994-06-28 General Electric Company Method for thinning of integrated circuit chips for lightweight packaged electronic systems
US5249728A (en) * 1993-03-10 1993-10-05 Atmel Corporation Bumpless bonding process having multilayer metallization
US5532174A (en) * 1994-04-22 1996-07-02 Lsi Logic Corporation Wafer level integrated circuit testing with a sacrificial metal layer

Also Published As

Publication number Publication date
US5670428A (en) 1997-09-23
EP0701284A1 (en) 1996-03-13
KR960012334A (ko) 1996-04-20
US5804464A (en) 1998-09-08
JPH0883888A (ja) 1996-03-26
US5596226A (en) 1997-01-21
JP3137565B2 (ja) 2001-02-26
US5644162A (en) 1997-07-01
KR100187872B1 (ko) 1999-06-01

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