ATE445231T1 - Wafer mit verbesserten leitenden schleifen im ritzrahmen - Google Patents

Wafer mit verbesserten leitenden schleifen im ritzrahmen

Info

Publication number
ATE445231T1
ATE445231T1 AT05772266T AT05772266T ATE445231T1 AT E445231 T1 ATE445231 T1 AT E445231T1 AT 05772266 T AT05772266 T AT 05772266T AT 05772266 T AT05772266 T AT 05772266T AT E445231 T1 ATE445231 T1 AT E445231T1
Authority
AT
Austria
Prior art keywords
wafer
ritting
frame
protecting
conductive loop
Prior art date
Application number
AT05772266T
Other languages
English (en)
Inventor
Heimo Scheucher
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE445231T1 publication Critical patent/ATE445231T1/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
AT05772266T 2004-07-26 2005-07-20 Wafer mit verbesserten leitenden schleifen im ritzrahmen ATE445231T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04103570 2004-07-26
PCT/IB2005/052428 WO2006013508A2 (en) 2004-07-26 2005-07-20 Wafer with improved conductive loops in the dicing lines

Publications (1)

Publication Number Publication Date
ATE445231T1 true ATE445231T1 (de) 2009-10-15

Family

ID=35583335

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05772266T ATE445231T1 (de) 2004-07-26 2005-07-20 Wafer mit verbesserten leitenden schleifen im ritzrahmen

Country Status (8)

Country Link
US (1) US7576412B2 (de)
EP (1) EP1774587B1 (de)
JP (1) JP2008507852A (de)
KR (1) KR20070038549A (de)
CN (1) CN101006578B (de)
AT (1) ATE445231T1 (de)
DE (1) DE602005017045D1 (de)
WO (1) WO2006013508A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101689541B (zh) 2007-07-12 2012-01-25 Nxp股份有限公司 晶片上的集成电路和制造集成电路的方法
US10896878B2 (en) * 2019-06-18 2021-01-19 Nxp B.V. Integrated circuit saw bow break point

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5596226A (en) * 1994-09-06 1997-01-21 International Business Machines Corporation Semiconductor chip having a chip metal layer and a transfer metal and corresponding electronic module
EP0843476A1 (de) 1996-11-19 1998-05-20 Deutsche Thomson-Brandt Gmbh Verfahren und Dekoder zur Datenverarbeitung in Teletextseiten
JPH10163522A (ja) * 1996-11-29 1998-06-19 Kyocera Corp Ledアレイの製造方法
JP3410371B2 (ja) * 1998-08-18 2003-05-26 リンテック株式会社 ウエハ裏面研削時の表面保護シートおよびその利用方法
CN1322574C (zh) * 1999-07-30 2007-06-20 日本板硝子株式会社 在切割区中设置的槽的结构及其应用
JP3339485B2 (ja) * 2000-01-24 2002-10-28 日本電気株式会社 半導体装置
ATE334479T1 (de) * 2000-07-21 2006-08-15 Koninkl Philips Electronics Nv VERFAHREN ZUR HERSTELLUNG INTEGRIERTER SCHALTUNGEN MIT VERBESSERTEN LEITERBAHNEN IN SOGENANNTER ßSÄGEBÜGELß-FORM
US6492247B1 (en) * 2000-11-21 2002-12-10 International Business Machines Corporation Method for eliminating crack damage induced by delaminating gate conductor interfaces in integrated circuits
JP4405719B2 (ja) * 2002-10-17 2010-01-27 株式会社ルネサステクノロジ 半導体ウエハ

Also Published As

Publication number Publication date
EP1774587B1 (de) 2009-10-07
US7576412B2 (en) 2009-08-18
JP2008507852A (ja) 2008-03-13
CN101006578A (zh) 2007-07-25
EP1774587A2 (de) 2007-04-18
DE602005017045D1 (de) 2009-11-19
CN101006578B (zh) 2010-06-23
WO2006013508A3 (en) 2006-04-06
US20080001259A1 (en) 2008-01-03
KR20070038549A (ko) 2007-04-10
WO2006013508A2 (en) 2006-02-09

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties