TW258830B - - Google Patents

Download PDF

Info

Publication number
TW258830B
TW258830B TW084100551A TW84100551A TW258830B TW 258830 B TW258830 B TW 258830B TW 084100551 A TW084100551 A TW 084100551A TW 84100551 A TW84100551 A TW 84100551A TW 258830 B TW258830 B TW 258830B
Authority
TW
Taiwan
Prior art keywords
layer
drain
source
patent application
gate electrode
Prior art date
Application number
TW084100551A
Other languages
English (en)
Chinese (zh)
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of TW258830B publication Critical patent/TW258830B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
    • H10D84/406—Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
TW084100551A 1993-12-03 1995-01-23 TW258830B (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/161,960 US5441903A (en) 1993-12-03 1993-12-03 BiCMOS process for supporting merged devices

Publications (1)

Publication Number Publication Date
TW258830B true TW258830B (enExample) 1995-10-01

Family

ID=22583555

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084100551A TW258830B (enExample) 1993-12-03 1995-01-23

Country Status (6)

Country Link
US (2) US5441903A (enExample)
EP (1) EP0656660B1 (enExample)
JP (1) JP3594346B2 (enExample)
KR (1) KR100360640B1 (enExample)
DE (1) DE69433638T2 (enExample)
TW (1) TW258830B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07335773A (ja) * 1994-06-10 1995-12-22 Hitachi Ltd 半導体集積回路装置の製造方法
US5620908A (en) * 1994-09-19 1997-04-15 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device comprising BiCMOS transistor
KR100223600B1 (ko) * 1997-01-23 1999-10-15 김덕중 반도체 장치 및 그 제조 방법
GB2340243A (en) * 1998-07-30 2000-02-16 P Shaw Trailer apparatus for measuring ground density
JP4003438B2 (ja) * 2001-11-07 2007-11-07 株式会社デンソー 半導体装置の製造方法および半導体装置
JP4342579B2 (ja) * 2006-08-31 2009-10-14 三洋電機株式会社 半導体装置
SE537230C2 (sv) * 2013-05-16 2015-03-10 Klas Håkan Eklund Med K Eklund Innovation F Bipolär transistorförstärkarkrets med isolerad gate
US11094806B2 (en) * 2017-12-29 2021-08-17 Texas Instruments Incorporated Fabricating transistors with implanting dopants at first and second dosages in the collector region to form the base region

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855244A (en) * 1987-07-02 1989-08-08 Texas Instruments Incorporated Method of making vertical PNP transistor in merged bipolar/CMOS technology
SE461428B (sv) * 1988-06-16 1990-02-12 Ericsson Telefon Ab L M Foerfarande foer att paa ett underlag av halvledarmaterial framstaella en bipolaer transistor eller en bipolaer transistor och en faelteffekttransistor eller en bipolaer transistor och en faelteffekttransistor med en komplementaer faelteffekttransistor och anordningar framstaellda enligt foerfarandena
JPH02101747A (ja) * 1988-10-11 1990-04-13 Toshiba Corp 半導体集積回路とその製造方法
US4868135A (en) * 1988-12-21 1989-09-19 International Business Machines Corporation Method for manufacturing a Bi-CMOS device
US5281544A (en) * 1990-07-23 1994-01-25 Seiko Epson Corporation Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors
US5101257A (en) * 1991-07-01 1992-03-31 Motorola, Inc. Semiconductor device having merged bipolar and MOS transistors and process for making the same
US5334549A (en) * 1993-08-13 1994-08-02 Texas Instruments Incorporated BiCMOS process that supports merged devices

Also Published As

Publication number Publication date
JPH07321240A (ja) 1995-12-08
EP0656660B1 (en) 2004-03-24
DE69433638D1 (de) 2004-04-29
JP3594346B2 (ja) 2004-11-24
KR950021503A (ko) 1995-07-26
KR100360640B1 (ko) 2003-01-10
US5811860A (en) 1998-09-22
US5441903A (en) 1995-08-15
DE69433638T2 (de) 2004-08-05
EP0656660A3 (en) 1998-01-07
EP0656660A2 (en) 1995-06-07

Similar Documents

Publication Publication Date Title
TW550811B (en) CMOS vertical replacement gate (VRG) transistors
US7482243B2 (en) Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US6888198B1 (en) Straddled gate FDSOI device
US20070228473A1 (en) ULTRA-THIN Si MOSFET DEVICE STRUCTURE AND METHOD OF MANUFACTURE
CN100576473C (zh) 用于制造具有硅化栅电极的半导体器件的方法以及用于制造包含该半导体器件的集成电路的方法
US6136674A (en) Mosfet with gate plug using differential oxide growth
EP0452720A2 (en) A semiconductor structure and method of its manufacture
TW200425519A (en) Self-aligned isolation double-gate FET
JP2003060076A (ja) 半導体装置及びその製造方法
US5506158A (en) BiCMOS process with surface channel PMOS transistor
EP0450375A1 (en) Interconnect and method of manufacture for semiconductor devices
US7648880B2 (en) Nitride-encapsulated FET (NNCFET)
TW258830B (enExample)
JP2006128427A (ja) 半導体装置の製造方法及び半導体装置
US5334549A (en) BiCMOS process that supports merged devices
US6727133B1 (en) Integrated circuit resistors in a high performance CMOS process
US6376293B1 (en) Shallow drain extenders for CMOS transistors using replacement gate design
US6638829B1 (en) Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture
US20040175907A1 (en) Method of fabricating a salicided device using a dummy dielectric layer between the source/drain and the gate electrode
JPH01765A (ja) 半導体装置
KR970000463B1 (ko) 트랜치를 이용한 mosfet 및 그 제조방법
TW527690B (en) Method for combining TCS-SiN barrier with dual gate CMOS device
JP2000124458A (ja) 半導体装置の製造方法
JP2003332460A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees