TW527690B - Method for combining TCS-SiN barrier with dual gate CMOS device - Google Patents

Abstract

A formation method of diffusion barrier layer in a semiconductor device is provided. First, a high dielectric constant gate dielectric layer is formed on the substrate. Then, a chemical vapor deposition process using reaction of tetrachlorosilane and ammonia is performed to form a silicon nitride barrier layer on top of the high dielectric constant gate dielectric layer. The silicon nitride barrier greatly reduces the impurity diffusion from the upper gate layer. The semiconductor device that consists of the silicon nitride barrier layer and its manufacturing method are also introduced.

Description

527690 V. Description of the invention (1) Field of the invention: The present invention relates to the manufacture of a metal-oxide-semiconductor field-effect transistor (MOSFET) device. In particular, it relates to the formation of a diffusion barrier layer, which is suitable for dual-gate complementary metal-oxide. Semiconductor (CM0s) devices that require boron-doped gate electrodes in the pMos portion. Relevant technical description: Complementary metal-oxide-semiconductor circuits are integrated circuits that are familiar with nMOS and pMOS devices. In traditional CMOS devices, the gate electrode is doped with phosphorous to form the n + gates of both nMOS and pMOS. For short channel lengths, that is, 0. 25 microns (# m) or less, it must be at pM. The part of 0s uses P + doped complex crystalline silicon gate formed by boron to minimize the short channel effect. Therefore, a CMOS device including a p-channel M0S transistor with a p-type gate electrode and an n-channel M0S transistor with an n-type gate electrode is called a dual-gate CMOS. High-k dielectrics such as Zr02, Hf 02,

A I? 〇3 etc. have been proposed as potential gate dielectrics to solve the problem of traditional thermal oxidation of gate dielectrics down to 70 nanometers (nm) generation. One of the two-gate CM 0 S devices with 咼 dielectric constant dielectric is difficult to penetrate. In the pMOS part, it was found that boron diffused into the channel region from the gate electrode through the high-dielectric constant dielectric during the heat treatment. The penetration of boron into the channel caused a reduction in low-field hole mobility (l0w — field hole mobility) and a decrease in initial voltage (V t). In view of this, the present invention is to obtain a double-gate CMOS device using a high-dielectric-gate dielectric without boron infiltration. Summary of the invention:

0593-6998TWF (n); 90071; SPIN.ptd page 4 527690 V. Description of the invention (2) Purpose of the present invention A method for dispersing a barrier layer Another method of the present invention to increase the force. A diffusion is combined in the stack of the present invention. The present invention achieves the above or other impurity self-braking by placing a layer of tetrachoros. It does not form a diffusion barrier based on the above during the south temperature process during the dichloros i 1 a layer. A high-k chemical vapor-deposited silicon nitride barrier layer is formed and diffused. According to one of the above-mentioned semiconductor devices, it is provided to form a diffusion in the semiconductor device to prevent boron infiltration. An object is to provide a fabrication A semiconductor device has a resistance to a decrease in starting voltage and electric mobility in a low field. The purpose is to provide a semiconductor device that disperses a barrier layer in a gate to prevent impurities from the gate electrode from spreading on the gate electrode and high dielectric constant. Silicon nitride formed by silane between gate dielectrics

llane-based silicon nitride, TCS-SiN and other purposes. This TCS-SiN layer is used to suppress the diffusion of the boron electrode into the substrate. In addition, the tCS-SiN layer ne-based silicon nitride (DCS-SiN) formed by two gas silanes will decompose hydrogen significantly. Purpose, the present invention provides a method for forming a semiconductor device, which includes the following steps: a square gate dielectric layer on a substrate; and using tetragas silane and ammonia to react over a high dielectric constant gate dielectric layer The second purpose is to form a second layer to block impurities from the gate layer formed later. The present invention provides a method for activating on a substrate, including the following steps: a square on a substrate =

0593-6998TWF (n); 90071; SPIN.ptd 527690 V. Description of the invention (3) A high-dielectric constant gate dielectric layer; Chemistry: 1 ,: 22: Γ into a silicon nitride barrier layer; & silicon resistor r above the silicon nitride barrier layer; and ί :: layer; patterned high dielectric constant gate dielectric layer, nitride Implanted to connect the structure in the substrate; and the purpose of the present invention is to provide a semiconductor device, including fossils " 1 r / ί electrode and a high dielectric constant gate dielectric between the dielectric The chemical vapor deposition vehicle using tetrachloroxanthane and ammonia reaction: a second barrier layer to prevent the impurity diffusion of the gate electrode. Ji Bijiabe ’s example of banging: π a day: the embodiment is to make a detailed description of the M0S part of a double-gate CM0S device. The second person who is familiar with this art also understands that the transistor can also be-double two. Develop your nMOS part, and change it by doping impurities of opposite polarity or conductivity. Please refer to FIG. 1, which illustrates a partial cross-sectional view of a semiconductor substrate 10. The substrate 10 includes a single crystal doped with n-type impurities. Tempering is optionally performed in an atmosphere of NH3 or oxidizing gas (NO) to form a thin nitride layer 2 on the substrate 0 with a thickness of 3 to 10 angstroms. The nitride layer 1 2 is generally silicon nitride or silicon oxynitride. Thereafter, a gate dielectric layer 14 having a thickness of 20 to 200 angstroms is formed by depositing a high dielectric constant (k) dielectric material on the nitride layer 12. The k value of this high dielectric constant layer 14 is in the range of 8 to 1,000 and can be formed using a metal oxide silicate material. Metal oxides include Zr02, Hf02, Aij, T02, and Taj3. The silicate contains ZrSiO4 and HfSiO4. This high-dielectric 2 often 3 pages 6 059-6998 TWF (n); 90071; SPIN.ptd 527690 V. Description of the invention (4) ^ -------- Layer 14 is also made of low-pressure chemical vapor It is formed by deposition (CVD), metal organic CVD, jet vapor deposition (jet vapor deposition), sputtering deposition, and other techniques. In the towel of this embodiment, this layer 14 is formed by depositing a metal film and tempering it in an oxygen-containing environment. With the formation of the gate dielectric layer 14, please refer to FIG. 2, before depositing the gate dielectric layer 14, a thin silicon nitride layer 16 is deposited to a thickness of 5 to 20 angstroms. The silicon nitride layer 16 serves as a barrier layer, which greatly inhibits dopants (such as y boron, phosphorus, or arsenic) from penetrating into the substrate. According to an important feature of the present invention, a silicon nitride (hereinafter referred to as "TCS-") is deposited using a chemical vapor deposition process in which tetrach silane lane (SM) is reacted with ammonia (NI). SiN "). Compared with the known method (hereinafter referred to as " DCS-Si N ',), the butyl cs-SiN has better thermal stability than the known method using dichlorosiUne (SiH2Cl2) and ammonia (NH3). . As shown in Figures 6 and 7, the Si-H bond contained in DCS-SiN decomposes hydrogen at high temperatures to promote butterfly penetration. In contrast, the N—η bond contained in TCS_SiN is stable up to 1050 ° C. Therefore, TCS_SiN does not decompose hydrogen during subsequent high-temperature processes. In this embodiment, the TCS_SiN layer 16 is formed by a low temperature chemical vapor deposition (LpCVD) process in a temperature range of 72 5 ° C to 825 ° C. Referring to FIG. 3, a conductive layer 18 is formed above the SiN layer 16 to serve as a gate electrode of a MOS transistor. This layer 18 may also be various conductive materials and is preferably polycrystalline silicon. Conventional techniques for forming polycrystalline silicon, such as CVD, can also be used to deposit this layer. In this embodiment, the polycrystalline silicon is deposited at a temperature above 625 ° C and has a thickness of about 750 to 180 angstroms. Source / drain

〇593-6998TWF (n); 90071; SPIN.ptd page 7 527690 V. Description of the invention (5) The polar region implantation will make this layer 18 conductive. The gate electrode structure is defined by patterning these layers by etching “two active etching, such as reactive ion etching, chemical electro-water etching,” or other non-unidirectional etching techniques. 8, 16, 6, 1, 4, and 2 〇. In FIG. 5, an arrow 21 indicates ion implantation, which is used to form a source and a drain region 22. At the same time, the gate electrode layer 8 becomes conductive. In this embodiment, a p-type dopant, such as boron or boron difluoride, is implanted to form a -pM0s transistor. If an nMOS transistor is desired, an n-type dopant such as arsenic or phosphorus can also be implanted. The gate structure 20 is used as a covering mask for the 10 part of the lower substrate. The laterally separated source / drain regions 22 define a channel region 24 below the gate structure 20. A suitable implant is in the range of 5 X 1 014 to 5 X 1 0 ″ at 0 ms / cm2, and the implantation energy is in the range of 2 to 80 keV. One or more different high-temperature steps are performed simultaneously, usually with a metallization process. However, if required, the source / drain regions 22 can also be tempered at this stage. For example, this tempering It is a rapid thermal annealing (RTA), with a temperature of about 900 t: to ι075 × χ, a time of about 30 to 60 seconds, and an inert gas atmosphere of argon, helium or nitrogen.

During the above-mentioned soaking step, dopants in the gate electrode 8 such as boron or other impurities may diffuse into the channel region 24 through the high-dielectric constant gate dielectric layer 4. However, the TCS-S i N layer 16 located between the gate electrode 8 and the high-k gate dielectric layer 14 greatly blocks the diffusion path so that the dopant cannot enter the substrate 10.

0593-6998TWF (n); 90071; SPIN.ptd page 8 527690

The steps according to the above embodiments produce a gate with high dielectric and high dielectric constant which does not allow boron to penetrate. Therefore, a pMOS transistor that requires dielectrics requires a boron-doped gate electrode, which is helpful for manufacturing the PMOS transistor. Gate ^, a double-gate CMOS device. Brother 8 can't draw the component phase shown by the double-gate CMOS device shown in this layer, showing the exhaustion of the X-ray barrier. The number of components is shown in the figure :: value J; The embodiments shown in Figures 1 to 5 are described. This CMOS device 2 is formed with gates and will not be repeated here. ^ ^ ^ ^ ^ T „. Λ t θθ0 ^ # ιμ ^ π ic φ ^ ®

These P-well regions 4 and 0-well regions 6 of different conductive properties are the so-called tWin tub active regions. It is noted that the construction of the well area is not limited to that described in the embodiment. A trench isolation 8 is formed at the interface between the two transistor regions to separate the transistor regions. In this double-gate CMOS device 2, the gate electrode of the MOS transistor is the same type as the channel. Therefore, the gate electrode 18 in the pMos part is doped with p-type impurities or other p-type impurities. The gate electrode of the nMOS part is replaced with doped phosphorus, arsenic, or other n-type impurities. The TCS-SiN layer Y / in the gate stack 20 prevents impurities from penetrating into the channel region, especially boron.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

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527690 Brief description of the drawings In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following exemplifies the preferred embodiments, and in conjunction with the attached drawings, the detailed description is as follows: Figures 1 to 5 are drawings Fig. 6 is a schematic cross-sectional view of a step of manufacturing a pM0S transistor according to an embodiment of the present invention; Fig. 6 is a graph showing the relationship between the SiH bond concentration of DCS-SiN film and the tempering temperature; Fig. 7 is a graph showing TCS-SiN The relationship between the film's NH bond concentration and the tempering temperature; Figure 8 is a schematic diagram of a dual-gate CMOS device incorporating a TCS-SiN barrier layer in a gate stack. [Symbol description] 2 ~ CMOS device; 4 ~ p—well area; 6 ~ η—well area; 8 ~ trench isolation; 10 ~ semiconductor substrate; 1 ~ 2 nitride layer; 14 ~ high dielectric constant dielectric layer 16 to TCS-SiN layer; 18 to gate electrode layer; 20 to gate structure; 21 to ion implantation; 2 to source / drain region.

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Claims (1)

527690 VI. Scope of patent application 1. A method for forming a diffusion barrier layer in a semiconductor device, including the following steps: A substrate formed by using a four-gas silicon gate dielectric as in the application of a special barrier layer at 8 To the range of 1 if applying for the barrier layer. For example, if you apply for a special barrier layer to learn the vapor deposition, as in the application for a special barrier layer, in this kind of basic electric constant since the follow-up 2. a diffusion electric constant 3. a diffusion from the lower 4. a diffusion 2 0 5. A diffusion low voltage before a diffusion electrical layer 7. Steps: forming a high dielectric constant gate dielectric layer on the side; and a chemical vapor deposition process in which alkane and ammonia react to form a layer over the high dielectric layer The nitride stone barrier layer is used to block the diffusion of impurities from the gate layer. The method for forming a semiconductor device according to item 1, wherein the high-k gate dielectric layer has a dielectric range of 0 0 0. The method for forming a semiconductor device as described in the first item of the invention, wherein the high-dielectric-constant gate dielectric layer is selected from the group consisting of metal oxides and oxalates. The method for forming a semiconductor device according to claim 1, wherein the thickness of the silicon nitride barrier layer is 5 to 5. The method for forming a semiconductor device according to claim 1, wherein at 7 2 5 ° C The silicon nitride barrier layer is formed by a build-up process at a temperature of 8 2 5 ° C. The method for forming a semiconductor device described in item 1 further includes the step of forming a nitride layer over the high-dielectric-constant gate substrate. A method for manufacturing a semiconductor device on the bottom includes the following steps: forming a high dielectric constant gate dielectric layer over a substrate; 0593-6998TWF (n); 90071; SPIN.ptd Page 11 527690 6. Scope of patent application: A silicon nitride barrier layer is formed by a chemical vapor deposition process using tetragas silane and ammonia reaction; the silicon nitride barrier Forming a gate electrode layer above the layer; patterning the high dielectric constant gate dielectric layer, the silicon nitride barrier layer, and the gate electrode layer to form a gate structure; and ion implantation to A source / drain region is formed in the substrate. 8. The method for manufacturing a semi-conductor device on a substrate as described in item 7 of the scope of the patent application, wherein the dielectric constant of the high-dielectric-constant gate dielectric layer is in the range of 8 to 100. 9. The method for manufacturing a semiconductor device on a substrate as described in item 7 of the scope of patent application, wherein the high-dielectric-constant gate dielectric layer is selected from one of the following groups: metal oxides and oxalic acid Salt. I 0. The method for manufacturing a semi-conductive device on a substrate as described in item 7 of the scope of the patent application, wherein the thickness of the silicon nitride barrier layer is in a range of 5 to 20 angstroms. II. The method for manufacturing a semiconductor device on a substrate as described in item 7 of the patent application scope, wherein the silicon nitride barrier layer is formed by a low pressure chemical vapor deposition process at a temperature of 725 ° C to 825 ° C . 1 2. The method for manufacturing a semiconductor device on a substrate as described in item 7 of the scope of patent application, further comprising the step of forming a nitride layer over the substrate before forming the high-k gate dielectric layer. . 1 3. The method for manufacturing a half-conductor device on a substrate as described in item 7 of the scope of patent application, wherein the semiconductor device is a pMOS transistor having a P-type gate electrode. 0593 -6998TWF (η); 90071; SPIN.ptd Page 12 W7690 VI Application scope of patents Conductor 1 Zhuang 4 Department # # 1115 Item 13 households & n a half of the sub-fabric :. '4' wherein the ex vivo device is implemented by implanting gadolinium or boron difluoride. 5: Fang V " / Scope Item 7 Manufacturing on a Substrate-Semiconductor < nM0S Transistor ,, Middle-side semiconductor device system-has n-type gate electrode conductors, 1 device and 6 items are manufactured on the bottom-half planting. / 、 The straw is implanted with arsenic or & to apply the ion cloth device to the device. Φ dry circumference / The thirst for manufacturing half of the conducting electrode on the substrate as described in item 7 4 The semiconductor device includes one With P-gate MOS transistor; c: s mounted crystal and-with η-type idle dielectric current age ϋ, body-mounted equipment 'includes-between an electrode and a high Shi Xixue blood-: The barrier layer of nitrided nitride between dielectric materials is applied to the semiconductor device using tetrachlorodielectric H to apply for the 18th month of the patent scope, wherein the height is 20 4 W; the dielectric constant of the dielectric layer is 8 The range is from 1 to 0 0 0. Dielectric constant: " Λ 电 ^ is selected from 1 8: of " ^ and oxalates. One of the following groups: metal oxide 2 1 · If a patent is applied for The 18th ^ conductor device with a thickness of 5 to 20 矣 of the fossil evening barrier layer, in which the milk 0591-6998TWF (n); 90071; SPIN.ptd No. 13 527690 6. Application for patent scope 22 2. For example, the semiconductor device under the scope of patent application No. 18, wherein the nitride barrier layer is formed by a low-pressure chemical vapor deposition process at a temperature of 725 ° C to 8 2 5 ° C. One half of the half of the half of the half. If the semiconductor device conductor device of the patent application item 18 is a pMOS transistor with a P-type gate electrode 24. The semiconductor device conductor device of the patent application item 18 It is an nMOS transistor with n-type gate electrode 25. The semiconductor device conductor device such as the scope of application for patent No. 18 includes a P-channel M0S transistor with a p-type gate electrode and an n-type transistor. Gate electrode η —CMOS device of channel M0S transistor. _ 0593-6998TWF (n); 90071; SPIN.ptd Page 14