TW258830B - - Google Patents
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- TW258830B TW258830B TW084100551A TW84100551A TW258830B TW 258830 B TW258830 B TW 258830B TW 084100551 A TW084100551 A TW 084100551A TW 84100551 A TW84100551 A TW 84100551A TW 258830 B TW258830 B TW 258830B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims description 12
- 239000003870 refractory metal Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 8
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 8
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 241000270295 Serpentes Species 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 230000002079 cooperative effect Effects 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 2
- 210000003625 skull Anatomy 0.000 claims 3
- 241001597062 Channa argus Species 0.000 claims 2
- 238000009434 installation Methods 0.000 claims 2
- 206010061218 Inflammation Diseases 0.000 claims 1
- 238000002513 implantation Methods 0.000 claims 1
- 230000004054 inflammatory process Effects 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 241000209140 Triticum Species 0.000 description 1
- 235000021307 Triticum Nutrition 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012886 linear function Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
- H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/009—Bi-MOS
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
A7 B7 <5^830 五、發明説明（l ) 相關申請案之相互參照 下列共同讓渡之專利申請案經予參考併入本案： 申請素號 申請曰期 TI案號 08/106,458 1993年8月 13日 TI-17015 發明之領域 本發明係概括關於半導艚處理，尤指BiCM〇s處理。 發明之背景 人們很希望將M0SFET結構及雙極電晶體集成在單一基片 上。如此項技藝上所熟知，數位及線性功能常藉積體電路 使用雙極或金屬氧化物半導體 (metal-oxide semiconductor,簡稱M〇S>技術完成。雙極積體電路較之 M0S電路，特别是與互補式M〇S ( compiementary M〇s ,簡 稱CMOS)電路比較，當然以較高功率耗散爲代價，提供較 高速度操作及較大驅動電流。製造技術上之進步已允許雙 極及CMOS電晶體使用於同一積體電路（通稱爲BiCM〇s元件 )。雙極電晶體一般爲使用一壕溝部位供雙極電晶體之基 極，摻雜之多晶矽供射極，及凹穴部位供集電極所構成。 然後使用另外諸壕溝部位形成PM0S電晶體之源極/漏極部 位。進一步利用雙極電晶體之高電流驅動能力，對於獲得 雙極或合併雙極CMOS集成之更高電平，具有重要性。 發明之概述 本發明揭示一種包含一雙極電晶體及一pM〇s電晶體位於 同一凹穴部位之BiCMOS元件。雙極電晶體有一包含—層多 晶石夕及一層轉發化物之射極電極。該元件可藉首先在一半 表紙張尺度適用中國國家榡率（CNS ) A4規格（210X297公釐 I I I I - I I —^农| - II__—訂 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央榡準局貝工消費合作社印製 經濟部中央搮準扃員工消費合作社印製 A7 B7 五、發明説明（2 ) 導體主體之表面形成一絶緣體層而構成。然後在凹穴部位 之第一部份植入一基極部位。然後蝕刻第一绝緣體層，使 基極部位之一部份露出。在半導體主體之表面形成一掺雜 之導電層，並將一鎮發化物層敷著於捧雜之導電層。其次 ’蚀刻鎢矽化物層及摻雜之導電層，以形成射極電極。最 後，形成許多PMOS電晶體，其中至少一 pjjos電晶鱧有一第 ―源極/漏極部位形成於凹穴部位，並與該基極部位相接 觸〇 本發明之一項優點爲提供一種形成合併之BiCMOS元件之 簡化方法。 本發明之另一優點爲提供一種合併之雙極/pM0S結構， 其包含一WSi 2層，防止p+S/D植入物由於自射極多晶矽將 P+S/D植入物阻斷，而改變雙極電晶體增益。 本發明之另一優點爲提供一種有一射極電極加蓋層之 BiCMOS元件，其可經得起高溫氧化物增長。 精於此項技藝者配合附圖參照詳細説明，將會明白此等 及其他諸多優點。 附圈之簡要説明 在附圖中 圈1爲本發明較佳實施例之剖面圖；以及 圖2a_j爲剖面圈，示製造本發明較佳實施例之各階段。 除非另外指明，對應之數字及符號在不同之諸圈中指對 應之部份。 較佳實施例之詳細説明 本紙張尺度適用中國國家橾準（CNS ) M规格（210χ297公釐） — (請先閱讀背面之注意事項再填寫本頁) -* S5S830 A7 經濟部中央標準局員工消费合作社印製 B7 五、發明説明（3 ) 本發明之較佳實施例在本案係説明爲結合於一種有一雙 極電晶體及一PMOS電晶體合併於同一凹穴部位之BiCM〇s結 構。 圈1以剖面圈例示雙極電晶體60以及P溝道電晶髏64及 68。該結構形成至一基片12,其在此實施例爲p型矽。雙 電極電晶鱧60上之埋入n+部位14以習知方式用作次集電極 ，而以n+部位25對其提供表面接觸。N部位18a用作雙極電 晶鱧60上之集電極部位及作爲供p溝道電晶體64之凹穴部 位。N部位18b爲供P溝道電晶體68之凹穴部位。本徵基 極26爲配置於η部位18a-b内之p型部位。射極電極3〇可 爲滲雜之多晶矽層，其穿過絶緣體層24上之開口至本微基 極部位26。鎢矽化物層32覆蓋射極電極3〇。p+部位52&兼 用作雙極電晶體60之本徵部位及作爲供p溝道電晶髏 64之源極/漏極部位之一。p+部位52用作供p溝道電晶鱧 64及68之其餘源極/漏極部位。捧雜之多晶石夕可用以形成 電晶體64及68之閘極40。閘氧化物36配置在閘極扣輿!！部 位18之間。埋入部位16位於部位20下面。場絶緣部位22使 本徵極部位26與集電極觸點25隔離，及使P溝道電晶禮 64及68彼此隔離◊閘極40可任選予以矽化，以形成^以2 層56。雹晶體64及68下面之諸N+部位14藉埋入之p部位16 予以隔開，並且η部位18a-b在不同之電勢。 圈2a例示在n+埋入層14，p埋入層16，η型部位i8a_b ，P型部位20，場絶緣部位22，及絶緣體層24上形成後之 結構〗〇。形成諸埋入層之方法説明於1990年9月18日所授 本紙張尺度通用中國國家榡準（CNS ) A4規格（210X297公釐） ^^1 In «^^1 In 1^1 >^^1 ml I m· In 一 (锖先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 ?5883〇 A7 _________ B7 五、發明説明（4 ) 予並讓渡予Texas Instruments Incorporated之美國專利 4,958,213號。形成場絶緣部位22之方法説明於1985年9月 17曰所授予並讓渡予Texas Instruments Incorporated之 美國專利4，541,167號。絶緣體層24可爲一經由一種抗Kooi 氧化作用，随後去釉至厚度小於20埃，繼之熱氧化至厚度 約300埃所形成之假閘氧化物。現將説明根據本發明之合併 之BiCMOS元件形成爲圈2a之結構。 結構10之表面作成圈案，並用一種η型摻雜劑植入，以 如圖2b中所示，形成一穿過η部位18接觸次集電極，η+部 位14之深η型部位（集電極觸點25)。其次，可進行Vt調 整植入物：一供NM0S電晶體（未示）及一供PM0S電晶體64 及68。仍請參照圈2b，基極部位26作成圈案，並以一種p 型掺雜物植入（例如硼7.0E13 cm在lOKev)。 請參照圈2c，掩蔽層27用以使假氧化物層24露出。然後 蝕刻露出之氧化物，使基極部位26之一部份露出。然後除 去掩蔽層27並進行去釉（例如10% HF 10秒），以使介面 氧化物減至最少。請參照圈2d，敷著一層導電材料，諸如 多晶矽層29至厚度约爲2500埃。其次，多晶矽層29可爲經 由離子植入之摻雜η型。多晶矽可代之爲於敷著時在現場 掺雜。將一層鎢矽化物WSi 2 32敷著於多晶矽層29上。 WSi 2 32可爲厚度約500埃或更大。其次，WSi 2層32予以 退火。多晶矽層29及WSi 2 32然後如闽2e中所示作成圖案 及蝕刻，以形成射極電極30。WSi 2層32在随後之處理步 驟防止射極電極30之氧化作用。 本紙張尺度逋用中國國家橾準（CNS ) Α4規格（2丨0'〆297公釐） (請先閱讀背面之注意事項再填寫本頁) 衣
、1T 經濟部中央標準局員工消費合作社印製 ?5883〇 A7 ----- B7 五、發明説明（5 ) 請麥照圈2f，然後用去釉劑除去假氧化物層24之露出部 份，並以绝緣體層諸如閘氧化物層36替代。閘氧化物層36 可藉熱氧化作用形成，厚度約爲〗00埃。閘氧化物層25增 長時’如圈2f中所示，氧化物37將會形成在射極電極3〇之 垂直邊緣，並且二氧化矽層35將會形成在WSi 2 32。可在 足夠高溫度進行熱氧化作用，以也用作射極退火。在較佳 實施例，使用溫度約900。。如圖2f中所示，在結構10之 表面藉LPCVD敷著第二層導電材料，諸如多晶矽層39。多 晶矽層39之厚度約爲3500埃。多晶矽層39然後可經由離子 植入予以摻雜。多晶矽層39可代之爲如此項技藝上所熟知 ’藉其他手段藉在現場掺雜或氣相摻雜（例如用P0C1 3 ) 予以摻雜）。如圖2g中所示，多晶矽層39予以作成圖案及 蝕刻以形成閘極40。矽氧化物層35將在多晶矽閘極蝕刻時 用作蝕刻阻擋層。 請參照圈2h，在表面上敷著一層tetraethoxysylane (TE0S)42。然後使用習知技術植入輕度掺雜之漏極（light doped drain，簡稱LDD)44,以形成侧壁隔片48,及形成源 極/漏極部位52。請予察知，LDD 44爲選用而無需形成。可 敷著一電介質層並各向異位蝕刻電介質層而藉以形成側壁 隔片48。側壁隔片48較佳爲包含氮化矽。不過可代之爲使 用氧化物或可清除之多晶矽。在側壁隔片48形成後，植入 源極/漏極部位52並予退火。因爲掺雜之射極電極先前在 形成氧化物層36時曾已"退火"，故源極/漏極部位52可在較 本紙張尺度適用中國國家橾準（CNS ) Μ规格（210X297公嫠） (請先閲讀背面之注意事項再填寫本頁) 衣- 訂 A7 B7 558830 五、發明説明（6 ) 低溫度退火（約爲8501c )，藉以減低短溝道效應。然後 如圈2i中所示除去TEOS層42及二氧化矽層35。 其次，閘極40以及源極/漏極部位52及52a可予以矽化 。在結構10之表面敷著一層耐火金屬（未示〉。使用快速 退火，可代之爲在含氮環境之壚退火，使該結構退火。這 導致該層耐火金屬與任何露出之矽發生反應而形成矽化物 。請參照圈2j，在閘極40及源極/漏極部位52及52a上形 成矽化物層56。在别處則形成一層耐火金屬氮化物及（或） 未起反應之金屬（未示）。然後除去該層耐火金屬氮化物。 在完成上述方法後，然後形成互相連接之鍍著金屬，以 供作成接觸至圈1之諸作用部位。形成此等互相連接之方 法在此項技藝上爲熟知者。然後使諸個别電路輿基片12之諸 部份分開，並如此項技術上所熟知，藉引線接合，直接凸 起接合等，對其作成外部連接。然後可將諸個别電路包装 於雙列直插式包裝，晶片載體，或另一型式之包裝。1985 年1月22日所授予並讓渡予Texas Instruments Incorporated之美國專利4,495,376號中便説明此種包裝 之一例。 雖然本發明業經參照例證性實施例予以説明，但此項説 明不意爲以限制性意義予以解釋。精於此項技藝者參照該 説明將會明白例證性實施例之各種修改及組合，以及本發 明之其他實施例。因此後附之申請專利範团意爲包括任何 此等修改或實施例。 本紙張尺度適用中國国家標準（CNS ) A4規格（210X297公釐） --------^丨-<:取丨^-----訂 一请先閱讀背在之注意事項存填寫本頁) 經濟部中央標準局員工消費合作社印袋
Claims (1)
- ?5$93〇 A8 B8 C8 D8 經濟部中央標準局貝工消费合作社印製 申請專利範圍 1. 一種形成半導嫌元件之方法，包含下列步嫌： a.在一有第一凹穴部位之半導體主髏之表面形成第一 绝緣體層； 在該第一凹穴部位之第一部份植入一基極部位； 蝕刻第一絶緣體層，以使基極部位之一部份露出； 在半導體主鱧之表面形成第一掺雜之導電層； 在第一導電層敷著鎢矽化物層；及 蚀刻鎢矽化物層及第一绝緣髏層，以形成一射極電 極，並使第一絶緣體層之一部份霧出；以及 g.形成許多PMOS電晶雅，其中至少諸PMOS電晶禮之一 有第一源極/漏極部位形成於第一凹穴部份，炎與基極 部位接觸。 2. 根據申請專利範圍第】項之方法，其中形成上述許多 PMOS電晶體之步驟包含下列步驟： a. 除去第一絶緣體層之未被射極電極覆蓋之部份； b. 在半導鱧主礅之表面及鎢矽化物層增長第二绝緣艘 層； c. 在第二絶緣體層形成許多閘極，其中至少一閘電極 形成於第一凹穴部位； d. 在半導體主體之表面形成許多源極/漏極部位，其 中許多源極/漏極部位包括第一源極/漏極部位，第一 源極/漏極部位形成於至少一閘電極與射極電極之間。 3. 根據申請專利範園第2項之方法，其中形成閘電極之步 驟包含下列步驟： t请先閱讀背面之注意事項存填寫本X) 丨裝· 訂 ί 線 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） 經濟部中央梂準局貝工消费合作社印製 ?5δ83〇 J88 ___g8s 、申請專'—~ a. 在半導鱧主體之表面形成第二摻雜導電層；以及 b. 蝕刻第二摻雜導電層以形成許多閘電極，其中蝕刻 在鴿矽化物層上之第二絶緣髏層停止。 4·根據申請專利範固第2項之方法，其中在溫度高於85〇 t!增長第二絶緣體層。 5. 根據申請專利範園第2項之方法，另包含下列步驟： a. 在上述形成閘電極之步驟後，在每一閘電極之相反 兩侧植入輕度摻雜之漏極；以及 b. 靠近每一閘電極及射極電極形成側壁隔片。 6. 根據申請夺利範固第2項之方法，另包含使閉電極，及 源極/漏極部位發化之步嫌。 7. 根據申請專利範園第6項之方法，其中使上述閘重極及 源極/漏極部位矽化之步驟包含下列步驟： a. 在半導體主鱧之表面敷著一層耐火金屬； b. 在含氮環境使該層耐火金屬退火，以在閘電極及源 極/漏極部位形成一層矽化物，及在别處形成一由耐火 金屬氮化物，未反應金屬，或其组合所構成之未砍化層 ;以及 c. 蝕刻上述来矽化層。 8. 根據申請專利範園第1項之方法，其中形成上述源極/漏 極部位之步驟包含下列步驟： a. 植入源極/漏極部位；以及 b, 在溫度低於900TC使源極/漏極部位退火。 9. 根據申請專利範团第1項之方法，其中上述第一绝緣體 本紙張尺度逋用中國國家梯準（CNS)A4規格（210x297公釐） (靖先閑讀背面之注意事項再填寫本頁) -裝. -訂 」 經濟部中央標半扃負工消费合作社印装 • 258830 -------D8 穴、申請專---- 層包3厚約300埃之氧化物，並且上述第二絶緣雜層包 含厚約100埃之氧化物。 1〇. 一種形成BiCMOS元件之方法包含下列步驟： a.在一有第一凹穴部位之半導髏主體之表面形成許多 場絶緣部位； b，在半導體主體之表面形成厚氧化物層； c.通過厚氧化物層在第一凹穴部位之靠近一第一場絶 緣部位之第一部位植入一基極部位； d‘蝕刻厚氧化物層，使基極部位之一部份露出； e •在厚氧化物層及基極部位之露出部份敷著第一層多 晶矽； f•在第一多晶矽層敷著一層鎢矽化物； g. 蝕刻鎢矽化物層及第一多晶矽層，以在基極部位形 成射極電極/並使厚氧化物層之一部份露出； h. 除去厚氧化物層之露出部份； L在半導體主體之表面增長一閘氧化物層； j .在閘氧化物層敷著第二層多晶矽； k.蚀刻第二多晶矽層以形成許多閘電極，其中至少閘 電極之—形成於第一凹穴部位； L靠近閘電極及射極電極形成側壁隔片； m·在半導體主體之表面，在每一閘電極之相反兩側植 入源極/漏極部位；以及 n.在溫度低於900¾使源極/漏極部位退火。 11·根據申請專利範園第10項之方法，另包含使閘電極及 -11 - 本紙張尺度適用中國國家樣準（CNS ) A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝_ 訂 J ®S883〇經济部中央標準局貝工消費合作社印裝 源極/漏極部位矽化之步驟。 12.根據申請專利範面第11项之方法，其中使上述閘電極 及源極/漏極部位矽化之步驟包含下列步驟： a. 在半導體主體之表面敷著一層耐火金屬； b. 在含氮環境使該層耐火金屬退火，以在閘電極及源 極/漏極部位形成一層矽化物，及在别處形成一由耐火 金屬氮化物，未起反應金屬，或其组合所構成之未矽化 層；以及 c •蝕刻該未矽化層。 —種BiCMOS元件包含： a. —凹穴部位； b. —有射極電極之雙極電晶雅，包含位於該凹穴部位 之一層多晶及一層媒石夕化物；以及 c‘一 PM0S電晶體位於上述凹穴部位。 14. 根據申請專利範固第13項之BiCM〇s元件，其中上述 PM0S電晶體有一源極//漏極部位與雙極電晶體之基極部 位相接觸。 15. 根據申請專利範固第13項之BiCM〇s元件，其中上述雙 極電晶體包含一基極部位，一集電極部位，一射極電極 ，及一位於射極電極與基極部位間之厚氧化物部位。 16. 根據申請專利範固第15項之BiCM〇s元件，其中上迷 PM0S電晶鱧包含一閘氧化物，該閘氧化物較上述厚氧化 物部位爲薄。 17. 根據申請專利範囷第13項之BiCOM〇s元件，其中上 PM0S包含一石夕化閘。 -12 - 本紙張纽A用中國國家揉準T^NS ) Mg ( 21GX297公ϋ ~— ------ (請先閲讀背面之注意事項再填寫本頁) -裝·
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/161,960 US5441903A (en) | 1993-12-03 | 1993-12-03 | BiCMOS process for supporting merged devices |
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| TW258830B true TW258830B (zh) | 1995-10-01 |
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| EP (1) | EP0656660B1 (zh) |
| JP (1) | JP3594346B2 (zh) |
| KR (1) | KR100360640B1 (zh) |
| DE (1) | DE69433638T2 (zh) |
| TW (1) | TW258830B (zh) |
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| JPH07335773A (ja) * | 1994-06-10 | 1995-12-22 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
| US5620908A (en) * | 1994-09-19 | 1997-04-15 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device comprising BiCMOS transistor |
| KR100223600B1 (ko) * | 1997-01-23 | 1999-10-15 | 김덕중 | 반도체 장치 및 그 제조 방법 |
| GB2340243A (en) * | 1998-07-30 | 2000-02-16 | P Shaw | Trailer apparatus for measuring ground density |
| JP4003438B2 (ja) * | 2001-11-07 | 2007-11-07 | 株式会社デンソー | 半導体装置の製造方法および半導体装置 |
| JP4342579B2 (ja) * | 2006-08-31 | 2009-10-14 | 三洋電機株式会社 | 半導体装置 |
| SE537230C2 (sv) * | 2013-05-16 | 2015-03-10 | Klas Håkan Eklund Med K Eklund Innovation F | Bipolär transistorförstärkarkrets med isolerad gate |
| US11094806B2 (en) | 2017-12-29 | 2021-08-17 | Texas Instruments Incorporated | Fabricating transistors with implanting dopants at first and second dosages in the collector region to form the base region |
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| US4855244A (en) * | 1987-07-02 | 1989-08-08 | Texas Instruments Incorporated | Method of making vertical PNP transistor in merged bipolar/CMOS technology |
| SE461428B (sv) * | 1988-06-16 | 1990-02-12 | Ericsson Telefon Ab L M | Foerfarande foer att paa ett underlag av halvledarmaterial framstaella en bipolaer transistor eller en bipolaer transistor och en faelteffekttransistor eller en bipolaer transistor och en faelteffekttransistor med en komplementaer faelteffekttransistor och anordningar framstaellda enligt foerfarandena |
| JPH02101747A (ja) * | 1988-10-11 | 1990-04-13 | Toshiba Corp | 半導体集積回路とその製造方法 |
| US4868135A (en) * | 1988-12-21 | 1989-09-19 | International Business Machines Corporation | Method for manufacturing a Bi-CMOS device |
| US5281544A (en) * | 1990-07-23 | 1994-01-25 | Seiko Epson Corporation | Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors |
| US5101257A (en) * | 1991-07-01 | 1992-03-31 | Motorola, Inc. | Semiconductor device having merged bipolar and MOS transistors and process for making the same |
| US5334549A (en) * | 1993-08-13 | 1994-08-02 | Texas Instruments Incorporated | BiCMOS process that supports merged devices |
-
1993
- 1993-12-03 US US08/161,960 patent/US5441903A/en not_active Expired - Fee Related
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1994
- 1994-12-02 EP EP94119036A patent/EP0656660B1/en not_active Expired - Lifetime
- 1994-12-02 DE DE69433638T patent/DE69433638T2/de not_active Expired - Lifetime
- 1994-12-03 KR KR1019940032689A patent/KR100360640B1/ko not_active IP Right Cessation
- 1994-12-05 JP JP33322294A patent/JP3594346B2/ja not_active Expired - Fee Related
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1995
- 1995-01-23 TW TW084100551A patent/TW258830B/zh not_active IP Right Cessation
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| Publication number | Publication date |
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| JPH07321240A (ja) | 1995-12-08 |
| DE69433638T2 (de) | 2004-08-05 |
| US5441903A (en) | 1995-08-15 |
| KR950021503A (ko) | 1995-07-26 |
| JP3594346B2 (ja) | 2004-11-24 |
| KR100360640B1 (ko) | 2003-01-10 |
| EP0656660B1 (en) | 2004-03-24 |
| US5811860A (en) | 1998-09-22 |
| EP0656660A2 (en) | 1995-06-07 |
| DE69433638D1 (de) | 2004-04-29 |
| EP0656660A3 (en) | 1998-01-07 |
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