TW236060B - - Google Patents

Info

Publication number
TW236060B
TW236060B TW082107058A TW82107058A TW236060B TW 236060 B TW236060 B TW 236060B TW 082107058 A TW082107058 A TW 082107058A TW 82107058 A TW82107058 A TW 82107058A TW 236060 B TW236060 B TW 236060B
Authority
TW
Taiwan
Application number
TW082107058A
Other languages
Chinese (zh)
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of TW236060B publication Critical patent/TW236060B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
TW082107058A 1993-02-24 1993-08-31 TW236060B (enEXAMPLES)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/021,924 US5400370A (en) 1993-02-24 1993-02-24 All digital high speed algorithmic data recovery method and apparatus using locally generated compensated broad band time rulers and data edge position averaging

Publications (1)

Publication Number Publication Date
TW236060B true TW236060B (enEXAMPLES) 1994-12-11

Family

ID=21806879

Family Applications (1)

Application Number Title Priority Date Filing Date
TW082107058A TW236060B (enEXAMPLES) 1993-02-24 1993-08-31

Country Status (6)

Country Link
US (1) US5400370A (enEXAMPLES)
EP (1) EP0614281B1 (enEXAMPLES)
JP (1) JPH06303224A (enEXAMPLES)
KR (1) KR940020698A (enEXAMPLES)
DE (1) DE69326882D1 (enEXAMPLES)
TW (1) TW236060B (enEXAMPLES)

Families Citing this family (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570944B2 (en) * 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
US6081561A (en) * 1994-02-25 2000-06-27 Texas Instruments Incorporated Method and apparatus for receiving and reconstituting a data signal employing oversampling and selection of a sampled data signal remote from transitions in the data signal
US5513377A (en) * 1994-06-17 1996-04-30 International Business Machines Corporation Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus
US5796673A (en) * 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
FR2726277B1 (fr) * 1994-10-28 1996-12-27 Bio Merieux Oligonucleotide utilisable comme amorce dans une methode d'amplification basee sur une replication avec deplacement de brin
US5671258A (en) * 1994-12-20 1997-09-23 3Com Corporation Clock recovery circuit and receiver using same
KR0141724B1 (ko) * 1995-01-07 1998-07-15 이헌조 브이씨알의 서보 제어장치
US5903605A (en) * 1995-03-30 1999-05-11 Intel Corporation Jitter detection method and apparatus
US5761254A (en) * 1996-01-31 1998-06-02 Advanced Micro Devices, Inc. Digital architecture for recovering NRZ/NRZI data
US5633899A (en) * 1996-02-02 1997-05-27 Lsi Logic Corporation Phase locked loop for high speed data capture of a serial data stream
US5694062A (en) * 1996-02-02 1997-12-02 Lsi Logic Corporation Self-timed phase detector and method
US5748020A (en) * 1996-02-02 1998-05-05 Lsi Logic Corporation High speed capture latch
US5805233A (en) * 1996-03-13 1998-09-08 In Focus Systems, Inc. Method and apparatus for automatic pixel clock phase and frequency correction in analog to digital video signal conversion
US6115769A (en) * 1996-06-28 2000-09-05 Lsi Logic Corporation Method and apparatus for providing precise circuit delays
US5818890A (en) * 1996-09-24 1998-10-06 Motorola, Inc. Method for synchronizing signals and structures therefor
US6072810A (en) * 1996-11-08 2000-06-06 Alcatel Method to transparently transport an incoming clock signal over a network segment, and related transmitter and receiver unit
US5886539A (en) * 1997-04-10 1999-03-23 Advanced Micro Devices, Ind Communication within an integrated circuit by data serialization through a metal plane
US5939912A (en) * 1997-06-18 1999-08-17 Lsi Logic Corporation Recovery circuit having long hold time and phase range
US5903521A (en) * 1997-07-11 1999-05-11 Advanced Micro Devices, Inc. Floating point timer
US6122278A (en) * 1997-08-07 2000-09-19 Advanced Micro Devices, Inc. Circuit and method for protocol header decoding and packet routing
US5890100A (en) * 1997-08-19 1999-03-30 Advanced Micro Devices, Inc. Chip temperature monitor using delay lines
US5943206A (en) * 1997-08-19 1999-08-24 Advanced Micro Devices, Inc. Chip temperature protection using delay lines
JP3286907B2 (ja) * 1997-10-30 2002-05-27 三菱電機株式会社 タイミング位相同期検出回路及び復調器
US6192069B1 (en) 1997-11-03 2001-02-20 Advanced Micro Devices, Inc. Circuit and methodology for transferring signals between semiconductor devices
US6084933A (en) * 1997-11-17 2000-07-04 Advanced Micro Devices, Inc. Chip operating conditions compensated clock generation
US6031473A (en) * 1997-11-17 2000-02-29 Advanced Micro Devices, Inc. Digital communications using serialized delay line
US5852616A (en) * 1997-11-17 1998-12-22 Advanced Micro Devices, Inc. On-chip operating condition recorder
US5942937A (en) * 1997-11-19 1999-08-24 Advanced Micro Devices, Inc. Signal detection circuit using a plurality of delay stages with edge detection logic
JP3109465B2 (ja) 1997-12-04 2000-11-13 日本電気株式会社 ディジタルｐｌｌ回路及び信号再生方法
US6064232A (en) * 1997-12-18 2000-05-16 Advanced Micro Devices, Inc. Self-clocked logic circuit and methodology
US6255969B1 (en) 1997-12-18 2001-07-03 Advanced Micro Devices, Inc. Circuit and method for high speed bit stream capture using a digital delay line
US6218880B1 (en) 1997-12-18 2001-04-17 Legerity Analog delay line implemented with a digital delay line technique
US6091348A (en) * 1997-12-18 2000-07-18 Advanced Micro Devices, Inc. Circuit and method for on-the-fly bit detection and substitution
US5900834A (en) * 1997-12-18 1999-05-04 Advanced Micro Devices, Inc. Doppler shift detector
US6178208B1 (en) 1997-12-18 2001-01-23 Legerity System for recovery of digital data from amplitude and phase modulated line signals using delay lines
US6078627A (en) * 1997-12-18 2000-06-20 Advanced Micro Devices, Inc. Circuit and method for multilevel signal decoding, descrambling, and error detection
US6160856A (en) * 1997-12-18 2000-12-12 Advanced Micro Devices, Inc. System for providing amplitude and phase modulation of line signals using delay lines
US6046620A (en) * 1997-12-18 2000-04-04 Advanced Micro Devices, Inc. Programmable delay line
US6157691A (en) * 1998-04-14 2000-12-05 Lsi Logic Corporation Fully integrated phase-locked loop with resistor-less loop filer
US6097767A (en) * 1998-04-17 2000-08-01 Advanced Micro Devices, Inc. Apparatus and method for determining an optimum equalizer setting for a signal equalizer in a communication network receiver
US6222392B1 (en) 1998-04-17 2001-04-24 Advanced Micro Devices, Inc. Signal monitoring circuit for detecting asynchronous clock loss
US6339833B1 (en) 1998-04-17 2002-01-15 Advanced Micro Devices, Inc. Automatic recovery from clock signal loss
US6374361B1 (en) 1998-04-23 2002-04-16 Silicon Image, Inc. Skew-insensitive low voltage differential receiver
US6584163B1 (en) * 1998-06-01 2003-06-24 Agere Systems Inc. Shared data and clock recovery for packetized data
US6430242B1 (en) 1998-06-15 2002-08-06 International Business Machines Corporation Initialization system for recovering bits and group of bits from a communications channel
FR2781943B1 (fr) * 1998-07-30 2000-09-15 Thomson Multimedia Sa Procede de recuperation d'horloge lors de l'echantillonnage de signaux de type numerique
US6557066B1 (en) 1999-05-25 2003-04-29 Lsi Logic Corporation Method and apparatus for data dependent, dual level output driver
US6294937B1 (en) 1999-05-25 2001-09-25 Lsi Logic Corporation Method and apparatus for self correcting parallel I/O circuitry
US6611217B2 (en) 1999-06-11 2003-08-26 International Business Machines Corporation Initialization system for recovering bits and group of bits from a communications channel
US6678408B1 (en) * 1999-11-17 2004-01-13 Infocus Corporation Noise reduction through comparative histograms
US6795515B1 (en) 2000-04-11 2004-09-21 International Business Machines Corporation Method and apparatus for locating sampling points in a synchronous data stream
GB2368651B (en) * 2000-10-31 2006-05-31 Consultronics Europ Ltd Method and apparatus for measurement of jitter
US6973148B2 (en) * 2000-11-30 2005-12-06 Adc Telecommunications, Inc. Clock recovery mechanism
US6990161B2 (en) * 2001-01-09 2006-01-24 International Business Machines Corporation Phase selection mechanism for optimal sampling of source synchronous clocking interface data
US6970529B2 (en) * 2001-01-16 2005-11-29 International Business Machines Corporation Unified digital architecture
US6704882B2 (en) 2001-01-22 2004-03-09 Mayo Foundation For Medical Education And Research Data bit-to-clock alignment circuit with first bit capture capability
KR100415193B1 (ko) * 2001-06-01 2004-01-16 삼성전자주식회사 반도체 메모리 장치에서의 내부클럭 발생방법 및 내부클럭발생회로
US6785622B2 (en) * 2001-10-29 2004-08-31 Agilent Technologies, Inc. Method and apparatus for performing eye diagram measurements
US7088767B1 (en) * 2002-03-01 2006-08-08 Xilinx, Inc. Method and apparatus for operating a transceiver in different data rates
US7035368B2 (en) * 2002-03-18 2006-04-25 Texas Instruments Incorporated High speed parallel link receiver
US7092471B2 (en) * 2002-05-22 2006-08-15 Lucent Technologies Inc. Digital phase synchronization circuit
US6950770B2 (en) * 2002-09-25 2005-09-27 Intel Corporation Method and apparatus for calibration of a delay element
JP4196657B2 (ja) * 2002-11-29 2008-12-17 株式会社日立製作所 データ再生方法およびデジタル制御型クロックデータリカバリ回路
EP1351067B1 (en) * 2003-02-25 2004-11-10 Agilent Technologies Inc Transition tracking
US7233636B2 (en) * 2003-03-14 2007-06-19 Thomson Licensing Technique for oversampling to reduce jitter
US7278080B2 (en) * 2003-03-20 2007-10-02 Arm Limited Error detection and recovery within processing stages of an integrated circuit
US8185812B2 (en) 2003-03-20 2012-05-22 Arm Limited Single event upset error detection within an integrated circuit
EP1604281B1 (en) * 2003-03-20 2006-08-09 ARM Limited Systematic and random error detection and recovery within processing stages of an integrated circuit
US8650470B2 (en) 2003-03-20 2014-02-11 Arm Limited Error recovery within integrated circuit
US7292662B2 (en) * 2003-03-26 2007-11-06 Infineon Technologies Ag Feed forward clock and data recovery unit
JP3960271B2 (ja) * 2003-07-02 2007-08-15 ソニー株式会社 位相誤差判定方法、デジタルｐｌｌ装置
US7292670B2 (en) * 2003-08-06 2007-11-06 Gennum Corporation System and method for automatically correcting duty cycle distortion
US7386080B2 (en) * 2003-09-30 2008-06-10 Intel Corportion High-speed data sampler for optical interconnect
US7668271B2 (en) * 2003-09-30 2010-02-23 Rambus Inc. Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data
US7236555B2 (en) * 2004-01-23 2007-06-26 Sunrise Telecom Incorporated Method and apparatus for measuring jitter
KR100603180B1 (ko) * 2004-08-06 2006-07-20 학교법인 포항공과대학교 주파수 트래킹 기법을 이용한 씨모오스 버스트 모드 클럭데이터 복원 회로
US7688928B2 (en) * 2006-09-05 2010-03-30 Lsi Corporation Duty cycle counting phase calibration scheme of an input/output (I/O) interface
TWI346460B (en) * 2006-10-31 2011-08-01 Realtek Semiconductor Corp A clock and data recovery circuit and a method for adjusting loop bandwidth used thereby
US20090033389A1 (en) * 2007-08-03 2009-02-05 Abadeer Wagdi W Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures
US7932552B2 (en) 2007-08-03 2011-04-26 International Business Machines Corporation Multiple source-single drain field effect semiconductor device and circuit
US7814449B2 (en) * 2007-10-17 2010-10-12 International Business Machines Corporation Design structure for multiple source-single drain field effect semiconductor device and circuit
JP5114244B2 (ja) * 2008-02-26 2013-01-09 オリンパス株式会社 クロック再生回路
US8171386B2 (en) * 2008-03-27 2012-05-01 Arm Limited Single event upset error detection within sequential storage circuitry of an integrated circuit
US8327196B2 (en) * 2008-07-16 2012-12-04 International Business Machines Corporation Identifying an optimized test bit pattern for analyzing electrical communications channel topologies
US8161367B2 (en) * 2008-10-07 2012-04-17 Arm Limited Correction of single event upset error within sequential storage circuitry of an integrated circuit
JP2012060606A (ja) * 2010-09-13 2012-03-22 Toshiba Corp 半導体集積回路および無線通信装置
US8493120B2 (en) 2011-03-10 2013-07-23 Arm Limited Storage circuitry and method with increased resilience to single event upsets
KR20160074339A (ko) * 2014-12-18 2016-06-28 에스케이하이닉스 주식회사 지연 회로
US10345339B2 (en) 2015-12-09 2019-07-09 Tektronix, Inc. Group delay based averaging
TWI690162B (zh) * 2019-08-30 2020-04-01 瑞昱半導體股份有限公司 時脈資料回復裝置及方法
US11063596B1 (en) * 2021-01-07 2021-07-13 Global Unichip Corporation Frame decoding circuit and method for performing frame decoding
CN114513293B (zh) * 2022-02-24 2022-10-14 中国水利水电科学研究院 一种秒脉冲延迟补偿系统及方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4010323A (en) * 1975-10-29 1977-03-01 Bell Telephone Laboratories, Incorporated Digital timing recovery
EP0185779B1 (en) * 1984-12-21 1990-02-28 International Business Machines Corporation Digital phase locked loop
NL8600889A (nl) * 1986-04-09 1987-11-02 Philips Nv Inrichting voor het terugwinnen van kanaalklokinformatie bij synchrone informatietransmissie en een inrichting voor het terugwinnen van de informatie voorzien van een dergelijke inrichting.
US4821297A (en) * 1987-11-19 1989-04-11 American Telephone And Telegraph Company, At&T Bell Laboratories Digital phase locked loop clock recovery scheme
US5052026A (en) * 1989-02-07 1991-09-24 Harris Corporation Bit synchronizer for short duration burst communications
US5068628A (en) * 1990-11-13 1991-11-26 Level One Communications, Inc. Digitally controlled timing recovery loop
US5208839A (en) * 1991-05-28 1993-05-04 General Electric Company Symbol synchronizer for sampled signals

Also Published As

Publication number Publication date
EP0614281A3 (en) 1995-07-19
DE69326882D1 (de) 1999-12-02
EP0614281B1 (en) 1999-10-27
EP0614281A2 (en) 1994-09-07
US5400370A (en) 1995-03-21
JPH06303224A (ja) 1994-10-28
KR940020698A (ko) 1994-09-16

Similar Documents

Publication Publication Date Title
TW236060B (enEXAMPLES)
EP0637889A3 (enEXAMPLES)
EP0637598A3 (enEXAMPLES)
IN187150B (enEXAMPLES)
TW275152B (enEXAMPLES)
FR2702252B1 (enEXAMPLES)
DK0611885T3 (enEXAMPLES)
TW286315B (enEXAMPLES)
EP0707697A4 (enEXAMPLES)
FR2714336B1 (enEXAMPLES)
FR2706733B1 (enEXAMPLES)
ECSDI930163S (enEXAMPLES)
ECSDI930115S (enEXAMPLES)
IN178048B (enEXAMPLES)
IN177209B (enEXAMPLES)
ECSDI930177S (enEXAMPLES)
IN176930B (enEXAMPLES)
IN176058B (enEXAMPLES)
IN189271B (enEXAMPLES)
DK52193D0 (enEXAMPLES)
DK46993D0 (enEXAMPLES)
ECSDI930176S (enEXAMPLES)
IN181306B (enEXAMPLES)
IN181171B (enEXAMPLES)
ECSDI930159S (enEXAMPLES)