TW226484B - - Google Patents
Download PDFInfo
- Publication number
- TW226484B TW226484B TW081108996A TW81108996A TW226484B TW 226484 B TW226484 B TW 226484B TW 081108996 A TW081108996 A TW 081108996A TW 81108996 A TW81108996 A TW 81108996A TW 226484 B TW226484 B TW 226484B
- Authority
- TW
- Taiwan
- Prior art keywords
- bit line
- contact
- configuration
- bsp
- bit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4139719A DE4139719C1 (enExample) | 1991-12-02 | 1991-12-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW226484B true TW226484B (enExample) | 1994-07-11 |
Family
ID=6446093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW081108996A TW226484B (enExample) | 1991-12-02 | 1992-11-10 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5315542A (enExample) |
| EP (1) | EP0545256B1 (enExample) |
| JP (1) | JP3304146B2 (enExample) |
| KR (1) | KR100279485B1 (enExample) |
| AT (1) | ATE158113T1 (enExample) |
| DE (2) | DE4139719C1 (enExample) |
| TW (1) | TW226484B (enExample) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2884962B2 (ja) * | 1992-10-30 | 1999-04-19 | 日本電気株式会社 | 半導体メモリ |
| US5864181A (en) | 1993-09-15 | 1999-01-26 | Micron Technology, Inc. | Bi-level digit line architecture for high density DRAMs |
| JP2638487B2 (ja) * | 1994-06-30 | 1997-08-06 | 日本電気株式会社 | 半導体記憶装置 |
| TW318281B (enExample) * | 1994-08-30 | 1997-10-21 | Mitsubishi Electric Corp | |
| US6043562A (en) | 1996-01-26 | 2000-03-28 | Micron Technology, Inc. | Digit line architecture for dynamic memory |
| US5864496A (en) * | 1997-09-29 | 1999-01-26 | Siemens Aktiengesellschaft | High density semiconductor memory having diagonal bit lines and dual word lines |
| TW417290B (en) * | 1998-06-26 | 2001-01-01 | Texas Instruments Inc | Relaxed layout for storage nodes for dynamic random access memories |
| US6249451B1 (en) | 1999-02-08 | 2001-06-19 | Kabushiki Kaisha Toshiba | Data line connections with twisting scheme technical field |
| US6282113B1 (en) * | 1999-09-29 | 2001-08-28 | International Business Machines Corporation | Four F-squared gapless dual layer bitline DRAM array architecture |
| JP4936582B2 (ja) * | 2000-07-28 | 2012-05-23 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| US9911693B2 (en) * | 2015-08-28 | 2018-03-06 | Micron Technology, Inc. | Semiconductor devices including conductive lines and methods of forming the semiconductor devices |
| US9553048B1 (en) * | 2015-09-04 | 2017-01-24 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method of semiconductor device |
| US10818729B2 (en) * | 2018-05-17 | 2020-10-27 | Macronix International Co., Ltd. | Bit cost scalable 3D phase change cross-point memory |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0760858B2 (ja) * | 1984-10-26 | 1995-06-28 | 三菱電機株式会社 | 半導体メモリ装置 |
| JPH01278065A (ja) * | 1988-04-28 | 1989-11-08 | Hitachi Ltd | 半導体記憶装置 |
| JPH07120714B2 (ja) * | 1989-05-23 | 1995-12-20 | 株式会社東芝 | 半導体記憶装置 |
| JP2974252B2 (ja) * | 1989-08-19 | 1999-11-10 | 富士通株式会社 | 半導体記憶装置 |
| US5107459A (en) * | 1990-04-20 | 1992-04-21 | International Business Machines Corporation | Stacked bit-line architecture for high density cross-point memory cell array |
-
1991
- 1991-12-02 DE DE4139719A patent/DE4139719C1/de not_active Expired - Fee Related
-
1992
- 1992-11-10 TW TW081108996A patent/TW226484B/zh active
- 1992-11-25 AT AT92120086T patent/ATE158113T1/de not_active IP Right Cessation
- 1992-11-25 EP EP92120086A patent/EP0545256B1/de not_active Expired - Lifetime
- 1992-11-25 DE DE59208890T patent/DE59208890D1/de not_active Expired - Fee Related
- 1992-11-27 JP JP34118192A patent/JP3304146B2/ja not_active Expired - Fee Related
- 1992-12-02 KR KR1019920023025A patent/KR100279485B1/ko not_active Expired - Fee Related
- 1992-12-02 US US07/984,376 patent/US5315542A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5315542A (en) | 1994-05-24 |
| JPH05243527A (ja) | 1993-09-21 |
| DE4139719C1 (enExample) | 1993-04-08 |
| DE59208890D1 (de) | 1997-10-16 |
| KR930014952A (ko) | 1993-07-23 |
| HK1000947A1 (en) | 1998-05-08 |
| ATE158113T1 (de) | 1997-09-15 |
| KR100279485B1 (ko) | 2001-03-02 |
| EP0545256A1 (de) | 1993-06-09 |
| JP3304146B2 (ja) | 2002-07-22 |
| EP0545256B1 (de) | 1997-09-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW226484B (enExample) | ||
| CN104898901B (zh) | 接垫结构以及触控面板 | |
| US20070132067A1 (en) | Wafer-to-wafer alignments | |
| US20180301835A1 (en) | Interposer Assembly and Method | |
| TW201727522A (zh) | Xor邏輯電路 | |
| JP3129836B2 (ja) | Vlsi回路の導体路配置 | |
| US8508017B2 (en) | Test device and semiconductor integrated circuit device | |
| CN107621715B (zh) | 一种显示面板及显示装置 | |
| CN109216455A (zh) | 半导体器件及其形成方法 | |
| JP2018004592A (ja) | 圧力センサ | |
| KR100300047B1 (ko) | 노이즈 간섭 방지를 위한 데이터라인 배열 구조를 갖는 반도체 메모리 소자 | |
| KR100462516B1 (ko) | 반도체 장치 | |
| CN204216010U (zh) | 接触孔偏移量测结构 | |
| CN116520210A (zh) | 一种精确度为0.3°的三轴霍尔角度传感器 | |
| JPS63170981A (ja) | 強磁性体磁気抵抗素子 | |
| US20100237394A1 (en) | Semiconductor memory device | |
| KR101101239B1 (ko) | 반도체 디바이스 테스트용 프로브 카드 | |
| CN113270392B (zh) | 一种对准标记结构以及半导体器件 | |
| US11061052B2 (en) | Probe including an alignment key protruded from a side of an alignment beam and a probe card including the same | |
| US6647619B2 (en) | Positioning arrangement and method | |
| TWI818428B (zh) | 通訊裝置及其通訊元件與此通訊元件的製造方法 | |
| JPH0431710A (ja) | 三次元測定プローブ | |
| KR100242991B1 (ko) | 반도체 웨이퍼의 오버레이 얼라인 키 | |
| JPH0230173B2 (enExample) | ||
| JPH06326332A (ja) | 静電容量型センサ |