TW214585B - Digital serializer and time delay regulator - Google Patents
Digital serializer and time delay regulator Download PDFInfo
- Publication number
- TW214585B TW214585B TW081109691A TW81109691A TW214585B TW 214585 B TW214585 B TW 214585B TW 081109691 A TW081109691 A TW 081109691A TW 81109691 A TW81109691 A TW 81109691A TW 214585 B TW214585 B TW 214585B
- Authority
- TW
- Taiwan
- Prior art keywords
- delay
- output
- unit
- delayed
- input
- Prior art date
Links
- 238000005070 sampling Methods 0.000 claims description 28
- 230000003111 delayed effect Effects 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 22
- 238000001514 detection method Methods 0.000 claims description 19
- 230000005540 biological transmission Effects 0.000 claims description 15
- 238000012937 correction Methods 0.000 claims description 11
- 230000001934 delay Effects 0.000 claims description 10
- 230000002079 cooperative effect Effects 0.000 claims description 9
- 125000002887 hydroxy group Chemical group [H]O* 0.000 claims description 6
- 238000003860 storage Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000009434 installation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000008901 benefit Effects 0.000 claims description 2
- 230000001174 ascending effect Effects 0.000 claims 1
- 230000001276 controlling effect Effects 0.000 claims 1
- 230000010006 flight Effects 0.000 claims 1
- 235000012907 honey Nutrition 0.000 claims 1
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 230000007704 transition Effects 0.000 description 39
- 230000000630 rising effect Effects 0.000 description 20
- 230000008859 change Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 7
- 238000011084 recovery Methods 0.000 description 6
- 101100406320 Caenorhabditis elegans dbt-1 gene Proteins 0.000 description 5
- 238000004891 communication Methods 0.000 description 5
- 238000012544 monitoring process Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 238000001914 filtration Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- IYZMXHQDXZKNCY-UHFFFAOYSA-N 1-n,1-n-diphenyl-4-n,4-n-bis[4-(n-phenylanilino)phenyl]benzene-1,4-diamine Chemical compound C1=CC=CC=C1N(C=1C=CC(=CC=1)N(C=1C=CC(=CC=1)N(C=1C=CC=CC=1)C=1C=CC=CC=1)C=1C=CC(=CC=1)N(C=1C=CC=CC=1)C=1C=CC=CC=1)C1=CC=CC=C1 IYZMXHQDXZKNCY-UHFFFAOYSA-N 0.000 description 2
- 240000002853 Nelumbo nucifera Species 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 2
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 241000196324 Embryophyta Species 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- RDYMFSUJUZBWLH-UHFFFAOYSA-N endosulfan Chemical compound C12COS(=O)OCC2C2(Cl)C(Cl)=C(Cl)C1(Cl)C2(Cl)Cl RDYMFSUJUZBWLH-UHFFFAOYSA-N 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/04—Distributors combined with modulators or demodulators
- H04J3/047—Distributors with transistors or integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Theoretical Computer Science (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Pulse Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/901,312 US5349612A (en) | 1992-06-19 | 1992-06-19 | Digital serializer and time delay regulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW214585B true TW214585B (en) | 1993-10-11 |
Family
ID=25413919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW081109691A TW214585B (en) | 1992-06-19 | 1992-12-03 | Digital serializer and time delay regulator |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5349612A (enExample) |
| EP (1) | EP0576150A2 (enExample) |
| JP (1) | JPH0661773A (enExample) |
| TW (1) | TW214585B (enExample) |
Families Citing this family (63)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5521499A (en) * | 1992-12-23 | 1996-05-28 | Comstream Corporation | Signal controlled phase shifter |
| US5465065A (en) * | 1993-03-31 | 1995-11-07 | Unisys Corporation | Gate compensation delay and delay lines |
| US5570294A (en) * | 1994-03-11 | 1996-10-29 | Advanced Micro Devices | Circuit configuration employing a compare unit for testing variably controlled delay units |
| US5621705A (en) * | 1994-05-02 | 1997-04-15 | Colorado Seminary | Programmable timing unit for generating multiple coherent timing signals |
| US5714904A (en) | 1994-06-06 | 1998-02-03 | Sun Microsystems, Inc. | High speed serial link for fully duplexed data communication |
| US5769311A (en) * | 1994-08-02 | 1998-06-23 | Toppan Printing Co., Ltd. | Heat insulating cup and method of manufacturing the same |
| US5572721A (en) * | 1994-12-13 | 1996-11-05 | Xerox Corporation | High speed serial interface between image enhancement logic and ros for implementation of image enhancement algorithms |
| JPH08330918A (ja) * | 1995-06-06 | 1996-12-13 | Mitsubishi Electric Corp | 可変遅延回路 |
| JPH0955667A (ja) * | 1995-08-10 | 1997-02-25 | Mitsubishi Electric Corp | マルチプレクサ，及びデマルチプレクサ |
| CA2161982A1 (en) * | 1995-11-02 | 1997-05-03 | Evan Arkas | Clock cleaner |
| US5822386A (en) * | 1995-11-29 | 1998-10-13 | Lucent Technologies Inc. | Phase recovery circuit for high speed and high density applications |
| US5818890A (en) * | 1996-09-24 | 1998-10-06 | Motorola, Inc. | Method for synchronizing signals and structures therefor |
| DE19652003C1 (de) * | 1996-12-13 | 1997-10-09 | Siemens Ag | Parallel/Seriell-Wandler |
| US5886539A (en) * | 1997-04-10 | 1999-03-23 | Advanced Micro Devices, Ind | Communication within an integrated circuit by data serialization through a metal plane |
| US5963074A (en) * | 1997-06-18 | 1999-10-05 | Credence Systems Corporation | Programmable delay circuit having calibratable delays |
| US5903521A (en) * | 1997-07-11 | 1999-05-11 | Advanced Micro Devices, Inc. | Floating point timer |
| US6122278A (en) * | 1997-08-07 | 2000-09-19 | Advanced Micro Devices, Inc. | Circuit and method for protocol header decoding and packet routing |
| US5890100A (en) * | 1997-08-19 | 1999-03-30 | Advanced Micro Devices, Inc. | Chip temperature monitor using delay lines |
| US5943206A (en) * | 1997-08-19 | 1999-08-24 | Advanced Micro Devices, Inc. | Chip temperature protection using delay lines |
| US6192069B1 (en) | 1997-11-03 | 2001-02-20 | Advanced Micro Devices, Inc. | Circuit and methodology for transferring signals between semiconductor devices |
| US6084933A (en) * | 1997-11-17 | 2000-07-04 | Advanced Micro Devices, Inc. | Chip operating conditions compensated clock generation |
| US5852616A (en) * | 1997-11-17 | 1998-12-22 | Advanced Micro Devices, Inc. | On-chip operating condition recorder |
| US6031473A (en) * | 1997-11-17 | 2000-02-29 | Advanced Micro Devices, Inc. | Digital communications using serialized delay line |
| US5942937A (en) * | 1997-11-19 | 1999-08-24 | Advanced Micro Devices, Inc. | Signal detection circuit using a plurality of delay stages with edge detection logic |
| US6160856A (en) * | 1997-12-18 | 2000-12-12 | Advanced Micro Devices, Inc. | System for providing amplitude and phase modulation of line signals using delay lines |
| US6218880B1 (en) | 1997-12-18 | 2001-04-17 | Legerity | Analog delay line implemented with a digital delay line technique |
| US6064232A (en) * | 1997-12-18 | 2000-05-16 | Advanced Micro Devices, Inc. | Self-clocked logic circuit and methodology |
| US6255969B1 (en) | 1997-12-18 | 2001-07-03 | Advanced Micro Devices, Inc. | Circuit and method for high speed bit stream capture using a digital delay line |
| US6178208B1 (en) | 1997-12-18 | 2001-01-23 | Legerity | System for recovery of digital data from amplitude and phase modulated line signals using delay lines |
| US6091348A (en) * | 1997-12-18 | 2000-07-18 | Advanced Micro Devices, Inc. | Circuit and method for on-the-fly bit detection and substitution |
| US5900834A (en) * | 1997-12-18 | 1999-05-04 | Advanced Micro Devices, Inc. | Doppler shift detector |
| US6046620A (en) * | 1997-12-18 | 2000-04-04 | Advanced Micro Devices, Inc. | Programmable delay line |
| US6078627A (en) * | 1997-12-18 | 2000-06-20 | Advanced Micro Devices, Inc. | Circuit and method for multilevel signal decoding, descrambling, and error detection |
| US6088415A (en) * | 1998-02-23 | 2000-07-11 | National Semiconductor Corporation | Apparatus and method to adaptively equalize duty cycle distortion |
| US6222392B1 (en) | 1998-04-17 | 2001-04-24 | Advanced Micro Devices, Inc. | Signal monitoring circuit for detecting asynchronous clock loss |
| US6339833B1 (en) | 1998-04-17 | 2002-01-15 | Advanced Micro Devices, Inc. | Automatic recovery from clock signal loss |
| US6246704B1 (en) * | 1998-04-30 | 2001-06-12 | Stmicroelectronics, Inc. | Automatic on-chip clock tuning methodology and circuitry |
| DE19830570A1 (de) * | 1998-07-08 | 2000-01-20 | Siemens Ag | Schaltung zur Ermittlung der Zeitdifferenz zwischen Flanken eines ersten und eines zweiten digitalen Signals |
| US6255878B1 (en) | 1998-09-18 | 2001-07-03 | Lsi Logic Corporation | Dual path asynchronous delay circuit |
| US6298315B1 (en) * | 1998-12-11 | 2001-10-02 | Wavecrest Corporation | Method and apparatus for analyzing measurements |
| US6446152B1 (en) * | 1999-03-03 | 2002-09-03 | Nortel Networks Limited | System and method for multi-coupling digital signals and a backplane data bus with multi-coupling of digital signals |
| JP3380206B2 (ja) | 1999-03-31 | 2003-02-24 | 沖電気工業株式会社 | 内部クロック発生回路 |
| JP4310036B2 (ja) * | 2000-09-07 | 2009-08-05 | 株式会社アドバンテスト | タイミング信号発生回路、及び、それを備えた半導体検査装置 |
| US6704882B2 (en) | 2001-01-22 | 2004-03-09 | Mayo Foundation For Medical Education And Research | Data bit-to-clock alignment circuit with first bit capture capability |
| KR100415193B1 (ko) * | 2001-06-01 | 2004-01-16 | 삼성전자주식회사 | 반도체 메모리 장치에서의 내부클럭 발생방법 및 내부클럭발생회로 |
| JP2003050738A (ja) * | 2001-08-03 | 2003-02-21 | Elpida Memory Inc | キャリブレーション方法及びメモリシステム |
| US7088767B1 (en) * | 2002-03-01 | 2006-08-08 | Xilinx, Inc. | Method and apparatus for operating a transceiver in different data rates |
| US20030212837A1 (en) * | 2002-04-25 | 2003-11-13 | Matsushita Elec Ind Co Ltd | Rate converter and rate conversion method |
| US7092471B2 (en) * | 2002-05-22 | 2006-08-15 | Lucent Technologies Inc. | Digital phase synchronization circuit |
| JP4332327B2 (ja) * | 2002-07-05 | 2009-09-16 | テクトロニクス・インターナショナル・セールス・ゲーエムベーハー | データ遅延回路 |
| US6686856B1 (en) * | 2002-11-20 | 2004-02-03 | Agilent Technologies, Inc. | Clocking domain conversion system and method |
| US20040239376A1 (en) * | 2003-05-30 | 2004-12-02 | Haeffele Jeffrey John | Continuously retraining sampler and method of use thereof |
| US7292670B2 (en) * | 2003-08-06 | 2007-11-06 | Gennum Corporation | System and method for automatically correcting duty cycle distortion |
| US7015838B1 (en) * | 2003-09-11 | 2006-03-21 | Xilinx, Inc. | Programmable serializing data path |
| EP1526648A1 (en) * | 2003-10-21 | 2005-04-27 | Mitsubishi Electric Information Technology Centre Europe B.V. | System and device for modulating UWB pulse sequences |
| CN1879171B (zh) * | 2003-11-12 | 2012-04-25 | Nxp股份有限公司 | 控制电子电路中的功耗峰值 |
| JP2005269147A (ja) * | 2004-03-18 | 2005-09-29 | Sanyo Electric Co Ltd | 遅延回路 |
| US7280930B2 (en) * | 2005-02-07 | 2007-10-09 | Lecroy Corporation | Sequential timebase |
| US7545848B2 (en) * | 2005-11-09 | 2009-06-09 | Agilent Technologies, Inc. | High resolution time stamps for periodic samples |
| CN102064927B (zh) * | 2010-09-21 | 2013-11-13 | 四川和芯微电子股份有限公司 | 时序纠错系统及方法 |
| US9800265B2 (en) * | 2016-03-28 | 2017-10-24 | Novatek Microelectronics Corp. | Data serialization circuit |
| JP7393079B2 (ja) * | 2019-03-26 | 2023-12-06 | ラピスセミコンダクタ株式会社 | 半導体装置 |
| US11695400B1 (en) * | 2022-08-12 | 2023-07-04 | Qualcomm Incorporated | Low-power inter-die communication using delay lines |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4524443A (en) * | 1983-12-22 | 1985-06-18 | Sperry Corporation | High speed solid state multiplexer |
| US4805195A (en) * | 1984-06-08 | 1989-02-14 | Amdahl Corporation | Selectable timing delay circuit |
| US4763327A (en) * | 1987-08-17 | 1988-08-09 | Unisys Corporation | Distributed digital signal process multiplexer |
| EP0364451A1 (en) * | 1988-03-26 | 1990-04-25 | BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap | Synchronizing circuit |
| US4899071A (en) * | 1988-08-02 | 1990-02-06 | Standard Microsystems Corporation | Active delay line circuit |
| DE3843261A1 (de) * | 1988-12-22 | 1990-06-28 | Ant Nachrichtentech | Schaltungsanordnung zur steuerung der phase eines taktsignals |
| EP0384918B1 (de) * | 1989-02-23 | 1994-08-24 | Siemens Aktiengesellschaft | Verfahren und Anordnung zum Anpassen eines Taktes an ein plesiochrones Datensignal und zu dessen Abtakten mit dem angepassten Takt |
| US5159205A (en) * | 1990-10-24 | 1992-10-27 | Burr-Brown Corporation | Timing generator circuit including adjustable tapped delay line within phase lock loop to control timing of signals in the tapped delay line |
| US5109394A (en) * | 1990-12-24 | 1992-04-28 | Ncr Corporation | All digital phase locked loop |
| US5146121A (en) * | 1991-10-24 | 1992-09-08 | Northern Telecom Limited | Signal delay apparatus employing a phase locked loop |
-
1992
- 1992-06-19 US US07/901,312 patent/US5349612A/en not_active Expired - Lifetime
- 1992-12-03 TW TW081109691A patent/TW214585B/zh active
-
1993
- 1993-05-26 EP EP93304079A patent/EP0576150A2/en not_active Withdrawn
- 1993-06-17 JP JP5146245A patent/JPH0661773A/ja not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| US5349612A (en) | 1994-09-20 |
| JPH0661773A (ja) | 1994-03-04 |
| EP0576150A3 (enExample) | 1994-04-13 |
| EP0576150A2 (en) | 1993-12-29 |
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