TW202343807A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW202343807A
TW202343807A TW112115013A TW112115013A TW202343807A TW 202343807 A TW202343807 A TW 202343807A TW 112115013 A TW112115013 A TW 112115013A TW 112115013 A TW112115013 A TW 112115013A TW 202343807 A TW202343807 A TW 202343807A
Authority
TW
Taiwan
Prior art keywords
conductor
insulator
transistor
oxide
memory unit
Prior art date
Application number
TW112115013A
Other languages
English (en)
Chinese (zh)
Inventor
大貫達也
國武寛司
中島基
Original Assignee
日商半導體能源研究所股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商半導體能源研究所股份有限公司 filed Critical 日商半導體能源研究所股份有限公司
Publication of TW202343807A publication Critical patent/TW202343807A/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW112115013A 2022-04-28 2023-04-21 半導體裝置 TW202343807A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022075007 2022-04-28
JP2022-075007 2022-04-28

Publications (1)

Publication Number Publication Date
TW202343807A true TW202343807A (zh) 2023-11-01

Family

ID=88518030

Family Applications (1)

Application Number Title Priority Date Filing Date
TW112115013A TW202343807A (zh) 2022-04-28 2023-04-21 半導體裝置

Country Status (6)

Country Link
US (1) US20250176155A1 (https=)
JP (1) JPWO2023209484A1 (https=)
KR (1) KR20250003661A (https=)
CN (1) CN119096713A (https=)
TW (1) TW202343807A (https=)
WO (1) WO2023209484A1 (https=)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9312257B2 (en) * 2012-02-29 2016-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10692869B2 (en) * 2016-11-17 2020-06-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
JP2018085357A (ja) * 2016-11-21 2018-05-31 株式会社半導体エネルギー研究所 記憶装置、及び電子機器
US20200342932A1 (en) * 2019-04-25 2020-10-29 John Bennett Nand connected gain cell memory
CN114424339A (zh) 2019-09-20 2022-04-29 株式会社半导体能源研究所 半导体装置及半导体装置的制造方法

Also Published As

Publication number Publication date
WO2023209484A1 (ja) 2023-11-02
US20250176155A1 (en) 2025-05-29
JPWO2023209484A1 (https=) 2023-11-02
CN119096713A (zh) 2024-12-06
KR20250003661A (ko) 2025-01-07

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