KR20250003661A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR20250003661A
KR20250003661A KR1020247036308A KR20247036308A KR20250003661A KR 20250003661 A KR20250003661 A KR 20250003661A KR 1020247036308 A KR1020247036308 A KR 1020247036308A KR 20247036308 A KR20247036308 A KR 20247036308A KR 20250003661 A KR20250003661 A KR 20250003661A
Authority
KR
South Korea
Prior art keywords
conductor
insulator
transistor
oxide
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020247036308A
Other languages
English (en)
Korean (ko)
Inventor
타츠야 오누키
히토시 쿠니타케
모토키 나카시마
Original Assignee
가부시키가이샤 한도오따이 에네루기 켄큐쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 한도오따이 에네루기 켄큐쇼 filed Critical 가부시키가이샤 한도오따이 에네루기 켄큐쇼
Publication of KR20250003661A publication Critical patent/KR20250003661A/ko
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B99/00Subject matter not provided for in other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]

Landscapes

  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020247036308A 2022-04-28 2023-04-14 반도체 장치 Pending KR20250003661A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2022075007 2022-04-28
JPJP-P-2022-075007 2022-04-28
PCT/IB2023/053816 WO2023209484A1 (ja) 2022-04-28 2023-04-14 半導体装置

Publications (1)

Publication Number Publication Date
KR20250003661A true KR20250003661A (ko) 2025-01-07

Family

ID=88518030

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247036308A Pending KR20250003661A (ko) 2022-04-28 2023-04-14 반도체 장치

Country Status (6)

Country Link
US (1) US20250176155A1 (https=)
JP (1) JPWO2023209484A1 (https=)
KR (1) KR20250003661A (https=)
CN (1) CN119096713A (https=)
TW (1) TW202343807A (https=)
WO (1) WO2023209484A1 (https=)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021053473A1 (ja) 2019-09-20 2021-03-25 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9312257B2 (en) * 2012-02-29 2016-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10692869B2 (en) * 2016-11-17 2020-06-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
JP2018085357A (ja) * 2016-11-21 2018-05-31 株式会社半導体エネルギー研究所 記憶装置、及び電子機器
US20200342932A1 (en) * 2019-04-25 2020-10-29 John Bennett Nand connected gain cell memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021053473A1 (ja) 2019-09-20 2021-03-25 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
H. Fujiwara et al., "Surrounding Gate Vertical-Channel FET with Gate Length of 40 nm Using BEOL Compatible High-Thermal-Tolerance In-Al-Zn Oxide Channel", 2020 Symposium on VLSI Technology, TH2.2
M. Oota et al., "3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm", IEDM Tech. Dig., 2019, pp. 50-53
X. Duan et al., "Novel Vertical Channel-All-Around(CAA) IGZO FETs for 2T0C DRAM with High Density beyond 4F2 by Monolithic Stacking", IEDM Tech. Dig., 2021, pp. 222-225

Also Published As

Publication number Publication date
WO2023209484A1 (ja) 2023-11-02
US20250176155A1 (en) 2025-05-29
TW202343807A (zh) 2023-11-01
JPWO2023209484A1 (https=) 2023-11-02
CN119096713A (zh) 2024-12-06

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Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20241030

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application