TW202339195A - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

Info

Publication number
TW202339195A
TW202339195A TW111128493A TW111128493A TW202339195A TW 202339195 A TW202339195 A TW 202339195A TW 111128493 A TW111128493 A TW 111128493A TW 111128493 A TW111128493 A TW 111128493A TW 202339195 A TW202339195 A TW 202339195A
Authority
TW
Taiwan
Prior art keywords
wafer
semiconductor device
base substrate
electrode
resin film
Prior art date
Application number
TW111128493A
Other languages
English (en)
Other versions
TWI854265B (zh
Inventor
本郷悟史
右田達夫
豊田現
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202339195A publication Critical patent/TW202339195A/zh
Application granted granted Critical
Publication of TWI854265B publication Critical patent/TWI854265B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0912—Layout
    • H01L2224/0915—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Micromachines (AREA)

Abstract

本發明提供一種可實現半導體裝置之窄節距化之半導體裝置及半導體裝置之製造方法。  本實施形態之半導體裝置包含：基底基板，其包含配線層；第1晶片，其設置於前述基底基板之上；第2晶片，其設置於前述第1晶片之上；及樹脂膜，其設置於前述第1晶片之側面、前述第1晶片之與前述基底基板相向之面之相反側之面、及前述第2晶片之側面；且自前述第1晶片之側面沿著垂直之方向即第1方向的前述樹脂膜之厚度，較自前述第2晶片之側面沿著前述第1方向的前述樹脂膜之厚度厚。

Description

半導體裝置及半導體裝置之製造方法
本實施形態係半導體裝置及半導體裝置之製造方法。
作為半導體裝置及半導體裝置之製造方法之一例，已知一種積層元件晶片及積層元件晶片之製造方法。
提供一種可實現半導體裝置之窄節距化之半導體裝置及半導體裝置之製造方法。
本實施形態之半導體裝置包含：基底基板，其包含配線層；第1晶片，其設置於前述基底基板之上；第2晶片，其設置於前述第1晶片之上；及樹脂膜，其設置於前述第1晶片之側面、前述第1晶片之與前述基底基板相向之面之相反側之面、及前述第2晶片之側面；且自前述第1晶片之側面沿著垂直之方向即第1方向的前述樹脂膜之厚度，較自前述第2晶片之側面沿著前述第1方向的前述樹脂膜之厚度厚。
以下，一面參照附圖一面對於本實施形態進行說明。為了將說明之理解容易化，而在各圖面中對於同一構成要件儘可能地賦予同一符號，且省略重複之說明。
圖1係用於說明第1實施形態之半導體記憶裝置E之構造之剖視圖。半導體記憶裝置E包含基底基板B、及晶片C1、C2、C3、C4、C5、C6。在基底基板B上接合有晶片C1。在基底基板B，在與接合有晶片C1之面為相反側之面接合有複數個金屬球BE。
在晶片C1，在與接合於基底基板B之面為相反側之面接合有晶片C2。在晶片C2，在與接合於晶片C1之面為相反側之面接合有晶片C3。在晶片C3，在與接合於晶片C2之面為相反側之面接合有晶片C4。在晶片C4，在與接合於晶片C3之面為相反側之面接合有晶片C5。在晶片C5，在與接合於晶片C4之面為相反側之面接合有晶片C6。如此般，在基底基板B上，積層有晶片C1、C2、C3、C4、C5、C6。
以覆蓋晶片C1、C2、C3、C4、C5、C6之側面之方式設置保護膜P。保護膜P亦覆蓋基底基板B之至少一部分。在本實施形態中，作為一例，設置為保護膜P在晶片C1側相對變厚，在晶片C6側相對變薄。保護膜P之厚度並不限定於此，亦可設置為均一。保護膜P亦可設置為在晶片C6側相對變厚，在晶片C1側相對變薄。亦可去除保護膜P。以覆蓋保護膜P之方式設置模製樹脂層M。
繼而，一面參照圖2至圖9，一面對於半導體記憶裝置E之製造方法進行說明。圖2至圖9係製造2個半導體記憶裝置E之圖，但亦可同時製造3個以上之多數個半導體記憶裝置E。
如圖2所示般，準備在支持基板SB上貼合有基底基板B者。再者，亦可藉由在支持基板SB上形成配線層而作為基底基板B。在基底基板B上之特定之位置接合特定數目之單片化之晶片C1。在各晶片C1中矽C1a成為較厚之狀態。自晶片C1延伸之貫通電極(TSV：Through-Silicon Via，矽穿孔)T1成為埋入矽C1a內之狀態。
繼而，如圖3所示般，對矽C1a進行反應性離子蝕刻(RIE：Reactive Ion Etching)，進行貫通電極T1之冒出。
繼而，如圖4所示般，以覆蓋晶片C1、矽C1a、及基底基板B之方式形成保護膜P1。保護膜P1係包含藉由化學蒸鍍(CVD：Chemical vapor deposition，化學氣相沈積)而形成之氧化物、氮化物、碳化物之樹脂膜。保護膜P1例如可使用SiO 2、SiOC、SiN、SiCN之膜。保護膜P1可由塗佈形成之絕緣膜構成。塗佈形成之絕緣膜可為由有機膜或聚合物材料構成。在塗佈上，可使用旋轉塗佈、噴墨、絲網印刷等。無論是塗佈形成還是化學蒸鍍，保護膜P1皆沿著晶片C1之外形保形地形成。保護膜P1可具有黏著性。
繼而，如圖5所示般，將保護膜P1藉由化學機械研磨(CMP：Chemical Mechanical Polishing)而薄膜化。藉由進行CMP，而貫通電極T1與保護膜P1形成為同一面。貫通電極T1及保護膜P1成為貼合面。貫通電極T1之節距例如可為10 μm～50 μm。貫通電極T1之直徑為5 μm～30 μm。關於貫通電極T1與保護膜P1，貫通電極T1可較保護膜P1突出0～數 μm左右。藉由最終之研磨而晶片C1之厚度成為數十 μm左右。較佳為20 μm～70 μm左右。研磨後之貼合面上之保護膜P1之厚度可為3 μm～5 μm左右。
繼而，如圖6所示般，在晶片C1之貼合面接合下一晶片C2。以後，重複一面參照圖2至圖5一面說明之程序，疊積晶片C3、C4、C5、C6而形成晶片積層體。如圖7所示般，因保護膜在每對晶片進行積層時形成，故積層晶片C6時之保護膜P中，與晶片C6之側面相比，晶片C1之側面更厚。在晶片C2之與晶片C1之貼合面相向之面形成電極，在電極之周邊形成絕緣膜。電極與絕緣膜可形成同一面。關於電極與絕緣膜，電極可較絕緣膜突出0～數 μm左右。在晶片C2之與晶片C1之貼合面相向之面形成之絕緣膜可為有機膜或聚合物材料，亦可為如氧化膜或氮化膜之無機膜。在晶片C1之貼合面、及晶片C2之與晶片C1之貼合面相向之面形成之絕緣膜，可為相同材料，亦可不同。
圖8顯示將圖7之XI部放大後之圖。如圖8所示般，保護膜P1、保護膜P2、保護膜P3、保護膜P4、保護膜P5、保護膜P6依序積層。保護膜P1如上述般係在設置晶片C1時積層之積層膜。保護膜P2係在晶片C1上設置晶片C2時積層之積層膜。保護膜P3係在晶片C2上設置晶片C3時積層之積層膜。保護膜P4係在晶片C3上設置晶片C4時積層之積層膜。保護膜P5係在晶片C4上設置晶片C5時積層之積層膜。保護膜P6係在晶片C5上設置晶片C6時積層之積層膜。在設置至晶片C6後，可將所接觸之電極彼此藉由金屬擴散而進行將結合牢固化之加熱處理。加熱處理例如於在晶片C1積層晶片C2後進行，進而，亦可於在晶片C2積層晶片C3後進行。然而，該情形下，因晶片C1暴露於複數次之加熱處理，故較佳的是在將所有晶片積層後進行一次加熱。
在晶片C1之側面，如圖8所示般，設置6層積層保護膜而成之積層膜。在基底基板B之上亦同樣地，設置6層積層保護膜而成之積層膜。
因在晶片C2之側面，未形成保護膜P1，而自保護膜P2起積層，故設置5層積層保護膜而成之積層膜。因在晶片C3之側面，除了不形成保護膜P1外亦不形成保護膜P2，而自保護膜P3起積層，故設置4層積層保護膜而成之積層膜。
因在晶片C4之側面，未形成保護膜P1、P2、P3，而自保護膜P4起積層，故設置3層積層保護膜而成之積層膜。因在晶片C5之側面，未形成保護膜P1、P2、P3、P4，而自保護膜P5起積層，故設置2層積層保護膜而成之積層膜。因在晶片C6之側面，未形成保護膜P1、P2、P3、P4、P5，而積層保護膜P6，故設置1層積層保護膜而成之積層膜。
此時，因在最上層之晶片C6處，無使貫通電極T1連接者，故無需將晶片C6薄化。該情形下，在晶片C6之側面，未設置積層膜。因此，未形成圖8所示之保護膜P6。在晶片C1之側面，設置5層保護膜。該情形下，在基底基板B之上設置5層保護膜。
繼而，如圖9所示般，形成模製樹脂層M。其後，藉由去除支持基板SB且單片化，而成為圖1所示之半導體記憶裝置E。保護膜P之一部分自模製樹脂M之側面露出。露出之保護膜P係沿著與基底基板B之表面垂直之方向、複數次重複SiN而成之積層膜。重複之次數可與積層之晶片數相同或者較其少一次。可在形成模製樹脂層M之前，削除基底基板B之上之保護膜P。此時，保護膜P不自模製樹脂層M之側面露出。
繼而，一面參照圖10一面進一步說明晶片C1。圖10係晶片C1之剖視圖，係一面參照圖2一面說明之狀態之剖視圖。如圖10所示般，晶片C1係貼合陣列晶片1與電路晶片2而成之三維記憶體。
陣列晶片1包含記憶胞陣列11、絕緣膜12、基板13、及絕緣膜14。記憶胞陣列11包含複數個記憶胞。絕緣膜12設置於記憶胞陣列11下。基板13設置於絕緣膜12下。絕緣膜14設置於基板13下。
陣列晶片1進一步包含層間絕緣膜15及絕緣膜16。層間絕緣膜15設置於記憶胞陣列11上。絕緣膜16設置於層間絕緣膜15上。絕緣膜12、14、16例如為矽氧化膜或矽氮化膜。基板13例如為矽基板等半導體基板。
電路晶片2設置於陣列晶片1上。符號S表示陣列晶片1與電路晶片2之貼合面。在將陣列晶片1與電路晶片2分別形成後，相互貼合。電路晶片2包含絕緣膜17、層間絕緣膜18、及半導體19。層間絕緣膜18設置於絕緣膜17上。半導體19設置於層間絕緣膜18上。絕緣膜17例如為矽氧化膜或矽氮化膜。
圖10顯示與基板13之表面S1、S2或半導體19之表面S3、基板60之表面S4平行、且相互垂直之X方向及Y方向、和與表面S1、S2或表面S3、S4垂直之Z方向。在本說明書中，將+Z方向視為上方向，將-Z方向視為下方向。例如，記憶胞陣列11位於基板60之下方、且位於基板13之上方。-Z方向可與重力方向一致亦可不一致。
陣列晶片1具備作為記憶胞陣列11內之電極層之複數個字元線WL、背閘極BG、及選擇閘極SG。圖10顯示記憶胞陣列11之階梯構造部21。陣列晶片1與電路晶片2相互接合。
如圖10所示般，各字元線WL經由接觸插塞22與字元配線層23電性連接。背閘極BG經由接觸插塞24與背閘極配線層25電性連接。選擇閘極SG經由接觸插塞26與選擇閘極配線層27電性連接。以貫通選擇閘極SG之方式設置柱狀部CL。字元線WL、背閘極BG、及柱狀部CL經由插塞28與位元線BL電性連接、且與基板13電性連接。
電路晶片2包含複數個電晶體31。各電晶體31包含閘極電極32、未圖示之源極擴散層、及未圖示之汲極擴散層。閘極電極32經由未圖示之閘極絕緣膜設置於半導體19上。源極擴散層及汲極擴散層設置於半導體19內。
電路晶片2進一步包含插塞33、配線層34、及配線層35。複數個插塞33設置於各電晶體31之源極擴散層或汲極擴散層上。複數個配線層34設置於該等插塞33上，包含複數條配線。複數個配線層35設置於該等配線層34上，包含複數條配線。
電路晶片2進一步包含通孔插塞36、及金屬墊37。複數個通孔插塞36設置在配線層35上。複數個金屬墊37在絕緣膜17內設置於該等通孔插塞36上。
電路晶片2進一步包含基板60及貫通電極61。基板60設置於半導體19之表面S4上。基板60例如為矽氧化膜或矽等之半導體基板。貫通電極61設置於層間絕緣膜18、半導體19及基板60內，且設置於配線層34上。基板60相當於圖2等中之矽C1a。貫通電極61相當於圖2等中之貫通電極T1。貫通電極61例如以在形成配線層34前埋入基板60之方式形成。電路晶片2包含控制陣列晶片1之CMOS控制電路(邏輯電路)。
陣列晶片1包含金屬墊41、通孔插塞42、及配線層43。複數個金屬墊41在絕緣膜16內設置於金屬墊37上。複數個通孔插塞42設置於金屬墊41上。複數個配線層43設置於該等通孔插塞42上，包含複數條配線。各字元線WL或各位元線BL與配線層43內之對應之配線電性連接。
陣列晶片1進一步包含插塞44，插塞46、及金屬墊47。插塞44設置於層間絕緣膜15或絕緣膜12內，且設置於配線層43上。插塞46經由絕緣膜45設置於基板13或絕緣膜14內，且設置於插塞44上。金屬墊47設置於絕緣膜14內，且設置於插塞46上。金屬墊47以與絕緣膜14之下表面成為同一平面之方式設置。金屬墊47係晶片C1之外部連接墊。
圖11係顯示在基底基板B藉由接合而接合晶片C1之狀態之剖視圖。基底基板B包含外部端子70、配線層71、插塞72、及金屬墊73。外部端子70在基底基板B下設置複數個。外部端子70係用於外部連接之金屬端子，發揮與一面參照圖1一面說明之金屬球BE相同之作用。
配線層71設置於基底基板B內部，包含複數條配線。插塞72設置於基底基板B內部，且設置於配線層71上。金屬墊73設置於插塞72上。金屬墊73設置於基底基板B內部，以與基底基板B之上表面成為同一平面之方式設置。
晶片C1之金屬墊47、與基底基板B之金屬墊73的配置於對應之位置之墊彼此對向配置，藉由接合而接合。
亦可在基底基板內部設置控制器。圖12係在內部設置有控制器74之基底基板Ba之例。控制器74係用於控制晶片C1等之控制器。控制器74與金屬墊73藉由插塞72連接。
圖13係顯示在圖11所示之晶片C1進一步藉由接合而接合晶片C2之狀態之剖視圖。自圖11所示之狀態，藉由一面參照圖3至圖6一面說明之方法進行晶片C1之貫通電極61之冒出，而將晶片C1載置於晶片C2。晶片C1之貫通電極61、與晶片C2之金屬墊47的配置於對應之位置之貫通電極及金屬墊彼此對向配置，藉由接合而接合。晶片C2之與晶片C1側相向之面例如係由氧化矽膜等絕緣膜形成，可與墊47形成於同一平面。晶片C1之與晶片C2側相向之面例如係由氧化矽膜等絕緣膜形成，可與貫通電極61形成於同一平面。
如圖14所示般，舉出配置晶片C1之貫通電極61與晶片C2之金屬墊47之情形為例進行說明。在圖14中，顯示晶片C1之上表面、及晶片C2之下表面。在圖14所例示之情形下，貫通電極61a與金屬墊47a對應，貫通電極61b與金屬墊47b對應。以該等對應之貫通電極與金屬墊彼此對向配置之方式，將晶片C2載置於晶片C1並進行接合。
在圖15中，對於在基底基板B接合晶片C1之情形進行說明。在圖15中，顯示基底基板B之上表面、及晶片C1之下表面。在圖15所例示之情形下，金屬墊73a與金屬墊47a對應，金屬墊73b與金屬墊47b對應。以該等對應之金屬墊彼此對向配置之方式，將晶片C1置於基底基板B並進行接合。
在圖15中，對於金屬墊73沿著基底基板B之短邊直線配置、金屬墊47亦沿著晶片C1之短邊直線配置之例進行了說明，但金屬墊73及金屬墊47之配置態樣並不限定於此。
如圖16所示般，金屬墊可為無規則性之配置態樣。在圖16中，顯示基底基板BD之上表面、及晶片C1D之下表面。在圖16所例示之情形下，金屬墊73Da與金屬墊47Da對應，金屬墊73Db與金屬墊47Db對應。以該等對應之金屬墊彼此對向配置之方式，將晶片C1D置於基底基板BD並進行接合。再者，可如圖16所例示般，與基底基板BD之金屬墊之配置態樣相應地改變晶片C1之金屬墊之配置態樣，亦可在圖15所例示之晶片C1之金屬墊之配置態樣不變下進行再配線而對應。
圖17係用於說明使用一面參照圖12一面說明之基底基板Ba之半導體記憶裝置E1之圖。如圖17所示般，基底基板Ba在內部具備控制器74。在基底基板Ba之內部設置配線層71。在基底基板Ba上，積層有晶片C。晶片C並不限於如一面參照圖10等一面說明之晶片C1般將記憶體基板與CMOS(Complementary Metal-oxide Semiconductor，互補式金屬氧化物半導體)接合之態樣，例如亦可為僅由記憶體基板構成。在積層之複數個晶片C之外周設置有保護膜P。在保護膜P之周圍設置模製樹脂層M。
圖18係用於說明第2實施形態之半導體記憶裝置E2之構造之剖視圖。半導體記憶裝置E2包含基底基板B、及複數個晶片C。在基底基板B上，晶片C受接著部81支持且被保持。基底基板B與晶片C藉由連接電極82電性連接。在基底基板B，在與接合有晶片C之面為相反側之面接合有複數個金屬球BE。
在複數個晶片C分別設置貫通電極T。以覆蓋複數個晶片C之側面之方式設置保護膜P。亦可去除保護膜P。以覆蓋保護膜P之方式設置模製樹脂層M。
繼而，一面參照圖19至圖28，一面對於半導體記憶裝置E2之製造方法進行說明。圖19至圖28對於搭載2個晶片C之例進行說明。
如圖19所示般，準備支持基板SB。支持基板SB係在製造中途被去除之基板。
繼而，如圖20所示般，將晶片C藉由接著劑等接合於支持基板SB上。在晶片C內部設置貫通電極T。
繼而，如圖21所示般，在接合於支持基板SB上之晶片C設置保護膜P，進行冒出而使貫通電極T露出，而接合下一晶片C。所接合之晶片C之貫通電極T相互接合。晶片C彼此之接合藉由接合而進行。
繼而，如圖22所示般，在配置於上方之晶片C上設置保護膜P，進行冒出而使貫通電極T露出。
繼而，如圖23所示般，在配置於上方之晶片C連接控制晶片CT。控制晶片CT與配置於上方之晶片C之貫通電極T接合。
繼而，如圖24所示般，準備基底基板B。基底基板B具備未圖示之配線層。基底基板B在上方具備金屬墊83。使圖23所示之支持基板SB及晶片C上下反轉，接著於基底基板B。接著藉由接著部81進行。接著部81成為將晶片C相對於基底基板B空開特定間隔而保持之支持體。晶片C與基底基板B藉由電極82電性連接。電極82與貫通電極T及金屬墊83相連。
繼而，如圖25所示般，去除支持基板SB。繼而，如圖26所示般，以覆蓋基底基板B上之晶片C之方式填充模製樹脂，形成模製樹脂層M。
繼而，如圖27所示般，在基底基板B之下方接合金屬球BE。金屬球BE接合於設置在基底基板B之下表面之金屬墊83。繼而，如圖28所示般，藉由沿著切割線L切斷、單片化而成為半導體記憶裝置E2。此時，保護膜P之一部分可自模製樹脂層M之側面露出。與圖1之半導體裝置E不同，保護膜P自最遠離基底基板B之晶片C之端部附近露出。亦可在形成模製樹脂層M之前削除保護膜P。該情形下，保護膜P不自模製樹脂層M露出。
上述實施形態之半導體裝置E、E1、E2包含：基底基板B，其包含配線層；及複數個晶片C，其在基底基板B上積層；且在複數個晶片間設置電極及保護膜P，並且在晶片C之側面亦設置保護膜P。
保護膜P含有SiO 2、SiOC、SiN、SiCN之至少一者。保護膜P係經塗佈形成之絕緣膜。
設置於晶片C之側面之保護膜P的基底基板B側之厚度與晶片C上端側之厚度不同。設置於晶片C之側面之保護膜P設置複數層。
上述實施形態之半導體裝置E、E1、E2之製造方法包含：準備包含配線層之基底基板B，在基底基板B上接合包含電極之晶片C，在晶片C形成保護膜P，對晶片C進行保護膜P之薄化加工，對晶片C進行電極冒出加工。
以上，一面參照具體例一面對於本實施形態進行了說明。然而，本揭示並不限定於該等具體例。由本領域技術人員對於該等具體例適當施加設計變更者，只要具備本揭示之特徵，亦包含於本揭示之範圍內。前述之各具體例所具備之各要件及其配置、條件、形狀等並不限定於例示者，而可適當變更。前述之各具體例所具備之各要件，只要不產生技術矛盾，亦可適當改變組合。
[相關申請案]  本申請案享有以日本專利申請案2022-045424號(申請日：2022年3月22日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之所有內容。
1:陣列晶片 2:電路晶片 11:記憶胞陣列 12, 14, 16, 17, 45:絕緣膜 13:基板 15, 18:層間絕緣膜 19:半導體 21:階梯構造部 22, 24, 26:接觸插塞 23:字元配線層 25:背閘極配線層 27:選擇閘極配線層 28, 33, 44, 46, 72:插塞 31:電晶體 32:閘極電極 34, 35, 43:配線層 36, 42:通孔插塞 37, 41, 47, 47a, 47b, 47Da, 47Db, 73, 73a, 73b, 73Da, 73Db, 83:金屬墊 60:基板 61, 61a, 61b:貫通電Z極 70:外部端子 71:配線層 74:控制器 81:接著部 82:電極 B, Ba, BD:基底基板 BE:金屬球 BG:背閘極 BL:位元線 C, C1, C1D, C2, C3, C4, C5, C6:晶片 C1a:矽 CL:柱狀部 CT:控制晶片 E, E1, E2:半導體記憶裝置 L:切割線 M:模製樹脂層 P, P1, P2, P3, P4, P5, P6:保護膜 S:貼合面 S1, S2, S3, S4:表面 SB:支持基板 SG:選擇閘極 T, T1:貫通電極 WL:字元線 XI:部 X, Y, Z:方向
圖1係用於說明第1實施形態之半導體記憶裝置之構成之圖。  圖2係用於說明圖1所示之半導體記憶裝置之製造方法之圖。  圖3係用於說明圖1所示之半導體記憶裝置之製造方法之圖。  圖4係用於說明圖1所示之半導體記憶裝置之製造方法之圖。  圖5係用於說明圖1所示之半導體記憶裝置之製造方法之圖。  圖6係用於說明圖1所示之半導體記憶裝置之製造方法之圖。  圖7係用於說明圖1所示之半導體記憶裝置之製造方法之圖。  圖8係放大地顯示圖7之XI部之圖。  圖9係用於說明圖1所示之半導體記憶裝置之製造方法之圖。  圖10係用於說明圖1所示之半導體記憶裝置所含之晶片之圖。  圖11係用於說明將圖10所示之晶片接合於基底基板之狀態之圖。  圖12係用於說明圖11所示之基底基板之變化例之圖。  圖13係用於說明在圖11之晶片進一步接合晶片之狀態之圖。  圖14係用於說明在晶片接合晶片之狀態之圖。  圖15係用於說明在基板接合晶片之狀態之圖。  圖16係用於說明在基板接合晶片之狀態之圖。  圖17係用於說明變化例之半導體記憶裝置之構成之圖。  圖18係用於說明第2實施形態之半導體記憶裝置之構成之圖。  圖19係用於說明圖18所示之半導體記憶裝置之製造方法之圖。  圖20係用於說明圖18所示之半導體記憶裝置之製造方法之圖。  圖21係用於說明圖18所示之半導體記憶裝置之製造方法之圖。  圖22係用於說明圖18所示之半導體記憶裝置之製造方法之圖。  圖23係用於說明圖18所示之半導體記憶裝置之製造方法之圖。  圖24係用於說明圖18所示之半導體記憶裝置之製造方法之圖。  圖25係用於說明圖18所示之半導體記憶裝置之製造方法之圖。  圖26係用於說明圖18所示之半導體記憶裝置之製造方法之圖。  圖27係用於說明圖18所示之半導體記憶裝置之製造方法之圖。  圖28係用於說明圖18所示之半導體記憶裝置之製造方法之圖。
B:基底基板
BE:金屬球
C1,C2,C3,C4,C5,C6:晶片
E:半導體記憶裝置
M:模製樹脂層
P:保護膜

Claims (17)

  1. 一種半導體裝置，其包含：基底基板，其包含配線層； 第1晶片，其設置於前述基底基板之上； 第2晶片，其設置於前述第1晶片之上；及 樹脂膜，其設置於前述第1晶片之側面、前述第1晶片之與前述基底基板相向之面之相反側之面、及前述第2晶片之側面；且 自前述第1晶片之側面沿著垂直之方向即第1方向的前述樹脂膜之厚度，較自前述第2晶片之側面沿著前述第1方向的前述樹脂膜之厚度厚。
  2. 如請求項1之半導體裝置，其中設置於前述第1晶片之與前述基底基板相向之面之相反側之面的樹脂膜、與設置於前述第1晶片之與前述基底基板相向之面之相反側之面的第1電極為同一平面。
  3. 如請求項2之半導體裝置，其中在前述第2晶片之與前述第1晶片相向之面，設置絕緣膜， 前述絕緣膜、與設置於前述第2晶片之與前述第1晶片相向之面之第2電極為同一平面。
  4. 如請求項3之半導體裝置，其中前述絕緣膜為無機膜。
  5. 如請求項3之半導體裝置，其中前述絕緣膜為有機樹脂膜。
  6. 如請求項3之半導體裝置，其中前述樹脂膜與前述絕緣膜為同一材料。
  7. 如請求項3之半導體裝置，其中前述第1電極、與前述第2電極直接接合。
  8. 如請求項3之半導體裝置，其中前述第1電極、及前述第2電極之直徑為5 μm～30 μm。
  9. 如請求項1之半導體裝置，其中設置於前述第1晶片之與前述基底基板相向之面之相反側之面的樹脂膜之厚度為3 μm～5 μm。
  10. 如請求項1之半導體裝置，其中前述樹脂膜設置於前述基底基板之上。
  11. 如請求項1之半導體裝置，其具備密封樹脂，該密封樹脂覆蓋前述基底基板、前述第1晶片、前述第2晶片、及前述樹脂膜。
  12. 如請求項11之半導體裝置，其中前述樹脂膜之一部分自前述密封樹脂之側面露出。
  13. 一種半導體裝置之製造方法，其包含：在基底基板設置第1晶片，該第1晶片具有第1面、與前述第1面為相反側之面即第2面、及第1電極； 將前述第1晶片薄化，直至前述第1電極自前述第2面側露出； 在前述第2面與前述第1晶片之側面、及前述基底基板形成樹脂膜； 將前述樹脂膜薄化，直至前述第1電極自前述樹脂膜露出； 將具有第3面、設置於前述第3面之第2電極、及與前述第3面為相反側之面即第4面之第2晶片以露出之前述第1電極與前述第2電極連接之方式接合於前述第1晶片。
  14. 如請求項13之半導體裝置之製造方法，其中在將前述樹脂膜薄化，直至前述第1電極自前述樹脂膜露出時， 將前述樹脂膜與前述第1電極設為同一平面。
  15. 如請求項13之半導體裝置之製造方法，其在前述第1晶片與前述第2晶片之接合後形成密封樹脂， 自前述第1晶片去除前述基底基板。
  16. 如請求項13之半導體裝置之製造方法，其中在前述第3面設置無機絕緣膜， 前述無機絕緣膜與前述第2電極為同一平面。
  17. 如請求項13之半導體裝置之製造方法，其形成密封樹脂，該密封樹脂覆蓋前述基底基板、前述第1晶片、前述第2晶片、及前述樹脂膜。
TW111128493A 2022-03-22 2022-07-29 半導體裝置及半導體裝置之製造方法 TWI854265B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022045424A JP2023139736A (ja) 2022-03-22 2022-03-22 半導体装置及び半導体装置の製造方法
JP2022-045424 2022-03-22

Publications (2)

Publication Number Publication Date
TW202339195A true TW202339195A (zh) 2023-10-01
TWI854265B TWI854265B (zh) 2024-09-01

Family

ID=

Also Published As

Publication number Publication date
JP2023139736A (ja) 2023-10-04
US20230307415A1 (en) 2023-09-28
CN116847663A (zh) 2023-10-03

Similar Documents

Publication Publication Date Title
US10840217B2 (en) Stacked chip package and methods of manufacture thereof
TWI768158B (zh) 半導體結構、形成其的方法及用於半導體的裝置
TWI735008B (zh) 積體電路裝置的封裝及其形成方法
TWI750576B (zh) 半導體裝置及其製造方法
JP5984134B2 (ja) 半導体装置およびその製造方法、電子部品
TWI776616B (zh) 半導體裝置及其製造方法
TW202013667A (zh) 半導體結構、封裝結構及其製造方法
JP2018148071A (ja) 記憶装置
JP5994167B2 (ja) 半導体装置およびその製造方法、電子部品
KR20170011366A (ko) 반도체 칩 및 이를 가지는 반도체 패키지
JP5998459B2 (ja) 半導体装置およびその製造方法、電子部品
US8704358B2 (en) Method for forming an integrated circuit
CN112420647A (zh) 半导体装置及其制造方法
TWI854265B (zh) 半導體裝置及半導體裝置之製造方法
TW202339195A (zh) 半導體裝置及半導體裝置之製造方法
TWI832156B (zh) 半導體裝置及半導體裝置之製造方法
TWI739413B (zh) 半導體裝置及其製造方法
TWI822153B (zh) 封裝結構及其形成方法
CN112510011B (zh) 半导体装置及其制造方法
CN113437029B (zh) 半导体装置及其制造方法
KR102720771B1 (ko) 반도체 패키지 및 반도체 패키지 제조 방법
US20240284685A1 (en) Semiconductor device and manufacturing method thereof
JP2024083024A (ja) 半導体装置
TW202349522A (zh) 形成封裝體的方法
CN118540957A (zh) 半导体装置及半导体装置的制造方法