TW202333286A - 半導體製造裝置用構件 - Google Patents

半導體製造裝置用構件 Download PDF

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TW202333286A
TW202333286A TW111147931A TW111147931A TW202333286A TW 202333286 A TW202333286 A TW 202333286A TW 111147931 A TW111147931 A TW 111147931A TW 111147931 A TW111147931 A TW 111147931A TW 202333286 A TW202333286 A TW 202333286A
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井上靖也
久野達也
宮本寛大
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日商日本碍子股份有限公司
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Abstract

半導體製造裝置用構件10包含：陶瓷板20；金屬接合層40及冷卻板30（導電性基材），設置於陶瓷板20之底面；第一孔24，在上下方向貫穿陶瓷板20；貫通孔42及氣體孔34（第二孔），在上下方向貫穿導電性構件，連通於第一孔24。多孔塞50之頂面露出於第一孔24之頂部開口，多孔塞50之底面位於導電性基材之頂面以下位置。絕緣管60之頂面相較於晶圓載置面21下方，絕緣管60之底面相較於多孔塞50之底面下方。一體化構件As係多孔塞50與絕緣管60一體化而成者，其外周面利用從第一孔24之頂面直到第二孔之內部的黏接層70固定於第一孔24及第二孔。

Description

半導體製造裝置用構件
本發明有關於半導體製造裝置用構件。
以往，作為半導體製造裝置用構件，具備頂面有晶圓載置面之靜電吸盤的半導體製造裝置用構件為人所知。例如，專利文獻1揭示一種靜電吸盤，該靜電吸盤包含：陶瓷板，吸附固持住晶圓；穿通孔，形成於陶瓷板；多孔塞，配置於穿通孔；及導電性冷卻板，黏接於陶瓷板之底面。多孔塞之底面係與陶瓷板之底面齊平。以電漿對載置於晶圓載置面之晶圓進行處理時，對冷卻板、與配置於晶圓上部的平行板電極之間施加射頻功率，在晶圓上部產生電漿。與此同時，為了提高晶圓與陶瓷板之熱傳導，藉由多孔塞對晶圓背面供給作為傳熱氣體之氦氣。若無多孔塞的話，伴隨著氦電離所產生之電子加速而碰撞其他氦，因此產生電弧放電。若有多孔塞，則電子在碰撞其他氦之前會先碰撞多孔塞，因此可抑制電弧放電。 [先前技術文獻]
[專利文獻1] 日本特開2019－29384號公報
[發明欲解決之課題]
然而，伴隨處理之高功率化，晶圓與冷卻板之間產生的電位差變大，上述靜電吸盤中，由於多孔塞本身之耐受電壓較低，因此多孔塞內會產生火花放電，導致晶圓變質。
本發明係為解決此課題而完成，主要目的為：在具備多孔塞之半導體製造裝置用構件中，抑制晶圓與導電性基材之間產生電弧放電及火花放電。 [解決課題之手段]
本發明之半導體製造裝置用構件，包含： 陶瓷板，頂面具有晶圓載置面； 導電性基材，設置於該陶瓷板之底面； 第一孔，在上下方向貫穿該陶瓷板； 第二孔，在上下方向貫穿該導電性基材，連通於該第一孔； 多孔塞，頂面露出於該第一孔之頂部開口，底面位於該導電性基材之頂面以下位置； 絕緣管，頂面相較於該晶圓載置面下方，底面相較於該多孔塞之底面下方；及 一體化構件，該多孔塞與該絕緣管一體化而構成，外周面利用從該第一孔之頂面直到該第二孔之內部的黏接層固定於該第一孔及該第二孔。
該半導體製造裝置用構件中，多孔塞之底面位於導電性基材之頂面以下位置。（較佳為相較於導電性基材之頂面下方）。多孔塞之底面相較於導電性基材之頂面上方的話，多孔塞之底面與導電性基材之間產生電弧放電。相對於此，多孔塞之底面位於導電性基材之頂面以下位置時，可抑制此電弧放電。又，絕緣管之底面相較於多孔塞之底面下方。因此，相較於沒有此絕緣管之情形，從晶圓到導電性基材為止之沿面距離變長，可抑制多孔塞內之火花放電。因此，具備多孔塞之半導體製造裝置用構件中，可抑制晶圓與導電性基材之間產生電弧放電及火花放電。
又，本說明書中，有時利用上下、左右或前後等用語來說明本發明，但上下、左右、前後只不過是相對位置關係。因此，若改變半導體製造裝置用構件之方位的話，上下會變成左右，左右會變成上下，但此種情形亦包含於本發明之技術範圍。
本發明之半導體製造裝置用構件中，相較於該第一孔之內部，該第二孔之內部中該黏接層之寬度在半徑外側方向較寬亦可。如此一來，以黏接劑形成黏接層之際，可以抑制氣泡進入位於第二孔內部之黏接劑的方式，充填黏接劑。
本發明之半導體製造裝置用構件中，該第二孔之內周面亦可具有直徑從下往上變大之擴徑部，該擴徑部與該絕緣管之間亦可存在該黏接層。以此方式，以黏接劑形成黏接層之際，同樣容易防止氣泡進入位於第二孔內部之黏接劑。
本發明之半導體製造裝置用構件中，該絕緣管亦可在管頂部具備有底孔，該多孔塞在插入該有底孔之狀態下受固持亦可。如此一來，沒有必要對較易損壞之多孔塞施加複雜之形狀加工。
本發明之半導體製造裝置用構件中，該晶圓載置面亦可具有用以支持晶圓之多個小突起，該多孔塞之頂面亦可相較於該小突起之頂面較低。如此一來，不會發生以多孔塞之頂面將晶圓往上推之情況。此時，該多孔塞之頂面可以和該晶圓載置面中未設置該小突起之基準面相同高度，亦可在相差0.2mm以下之範圍低於該基準面。如此一來，晶圓之背面與多孔塞之頂面間的空間之高度被壓制得較低，故可防止在此空間產生電弧放電。
接著，針對本發明之最佳實施態樣，利用圖式進行說明。圖1係半導體製造裝置用構件10之縱剖面圖，圖2係陶瓷板20之俯視圖，圖3係圖1之部分放大圖。
半導體製造裝置用構件10具備：陶瓷板20、冷卻板30、金屬接合層40、多孔塞50、及絕緣管60。
陶瓷板20為氧化鋁燒結體或氮化鋁燒結體等陶瓷製的圓板（例如直徑300mm、厚度5mm）。陶瓷板20之頂面為晶圓載置面21。陶瓷板20內設有電極22。於陶瓷板20之晶圓載置面21，如圖2所示，沿外周緣形成有密封環帶21a，整面形成有複數之圓形小突起21b。密封環帶21a與圓形小突起21b有相同高度，其高度為例如數μm～數十μm。電極22為使用作靜電電極之平面狀網格電極，可施加直流電壓。當對此電極22施加直流電壓時，晶圓W被靜電吸附力吸附固定於晶圓載置面21（具體而言為密封環帶21a之頂面及圓形小突起21b之頂面）。當停止施加直流電壓時，晶圓W不再吸附固定於晶圓載置面21。又，晶圓載置面21中未設置有密封環帶21a及圓形小突起21b之部分，稱為基準面21c。
陶瓷板20設有第一孔24。第一孔24為在上下方向貫穿陶瓷板20及電極22之貫通孔。如圖3所示，第一孔24為帶有段差之孔，孔頂部24a較細，孔底部24b較粗。亦即，第一孔24為小直徑圓柱狀之孔頂部24a與大直徑圓柱狀之孔底部24b相連而成的孔。第一孔24設於陶瓷板20之複數處（例如沿周向等間隔設置之複數處）。
冷卻板30為導熱係數佳之圓板（與陶瓷板20相同直徑或直徑大於陶瓷板20之圓板）。冷卻板30之內部，形成有冷媒循環其中之冷媒通道32、及對多孔塞50供給氣體之氣體孔34。冷媒通道32以俯視觀察時遍佈冷卻板30的整面、從入口到出口一筆劃之方式形成。氣體孔34為圓柱孔，以和第一孔24同軸之方式連通於第一孔24。氣體孔34之直徑大於第一孔24之孔底部24b之直徑。冷卻板30之材料，可舉例如金屬材料或金屬基複合材料（MMC）等。金屬材料可舉例如Al、Ti、Mo或其等之合金等。MMC可舉例如含有Si、SiC及Ti之材料（亦稱為SiSiCTi）、或使Al及／或Si浸漬於SiC多孔質體而成之材料等。冷卻板30之材料，較佳係選用熱膨脹係數接近陶瓷板20之材料者。冷卻板30亦使用作射頻電極。具體而言，在晶圓載置面21之上方配置有上部電極（未圖示），對於由該上部電極與冷卻板30構成的平行板電極間施加射頻功率時，即產生電漿。
金屬接合層40將陶瓷板20之底面與冷卻板30之頂面接合起來。金屬接合層40以例如熱壓接合法（TCB，Thermal compression bonding）形成。TCB法為一公知方法，將金屬接合材料夾入接合對象的兩個構件之間，在加熱至金屬接合材料之固相線溫度以下溫度之狀態下，加壓接合兩個構件。金屬接合層40設有貫通孔42。貫通孔42以連通於陶瓷板20之第一孔24及冷卻板30之氣體孔34的方式，在上下方向貫通。貫通孔42之直徑相同於氣體孔34之直徑。本實施態樣之金屬接合層40與冷卻板30相當於本發明之導電性基材，本實施態樣之貫通孔42與氣體孔34相當於本發明之第二孔。
多孔塞50為讓氣體在上下方向流通之多孔質圓柱構件。多孔塞50以例如氧化鋁等電絕緣材料形成。多孔塞50之頂面50a露出於第一孔24之頂部開口，與基準面21c形成同一平面。又，所謂「同一」，除了完全同一之外，也包含實質上同一（例如公差範圍內等）（以下亦同）。多孔塞50之底面50b位於金屬接合層40之頂面40a以下，在此位於貫通孔42之內部（相較於金屬接合層40之頂面40a下方）。
絕緣管60為以緻密陶瓷形成之圓筒管，內部具有氣體通路62。絕緣管60之頂部設置有底孔64，有底孔64之直徑大於氣體通路62之直徑。絕緣管60之頂面60a相較於晶圓載置面21下方。絕緣管60之底面60b相較於多孔塞50之底面50b下方，在此位於冷卻板30之氣體孔34之內部。絕緣管60與多孔塞50一體化，構成一體化構件As。一體化構件As為於多孔塞50插入到絕緣管60之有底孔64的狀態下利用由黏接劑構成之固持層52固持而成者。有底孔64之底面與多孔塞50之底面50b間存在空隙。藉由設置此空隙，將容易調整多孔塞50之高度。
一體化構件As插入氣體孔34、貫通孔42及第一孔24。一體化構件As之外周面利用由黏接劑構成之黏接層70固定於第一孔24、貫通孔42及氣體孔34，該黏接層70從陶瓷板20之第一孔24之頂部開口緣直到冷卻板30之氣體孔34內部形成。黏接層70之水平方向寬度，在第一孔24之孔頂部24a較狹，在貫通孔42及氣體孔34較寬，在第一孔24之孔底部24b則居中。亦即，相較於第一孔24內部之黏接層70之寬度，貫通孔42及氣體孔34內部之黏接層70之寬度在半徑外側方向較寬。因此，可使氣泡較不易進入氣體孔34內部之黏接層70中。關於此設計詳述如後。
接著，針對如此構成之半導體製造裝置用構件10之使用例子進行說明。首先，在未圖示之腔室內設置半導體製造裝置用構件10之狀態下，在晶圓載置面21載置晶圓W。然後，以真空泵使腔室內減壓成為預定之真空度，對陶瓷板20之電極22施加直流電壓而產生靜電吸附力，將晶圓W吸附固定於晶圓載置面21（具體而言為密封環帶21a之頂面及圓形小突起21b之頂面）。接著，將腔室內設定成預定壓力（例如數十～數百Pa）之反應氣體環境氣氛，此狀態下，對於設在腔室內之頂棚部分的未圖示之上部電極、與半導體製造裝置用構件10之冷卻板30間施加高頻電壓而產生電漿。晶圓W表面利用所產生之電漿進行處理。冷卻板30之冷媒通道32有冷媒循環於其中。對氣體孔34，從未圖示之貯氣瓶導入背面氣體於其中。背面氣體使用傳熱氣體（例如氦氣等）。背面氣體通過氣體孔34、絕緣管60及多孔塞50，供給充填於晶圓W之背面與晶圓載置面21之基準面21c間之空間。因為存在此背面氣體，故晶圓W與陶瓷板20之熱傳導有效率地進行。
接著，利用圖4及圖5，說明半導體製造裝置用構件10之製造例子。圖4係一體化構件As之製程圖，圖5係半導體製造裝置用構件10之製程圖。首先，準備多孔塞50及絕緣管60（圖4A），在絕緣管60之有底孔64之內周面塗佈黏接劑，將多孔塞50插入該有底孔64黏接起來，藉以形成為一體化構件As（圖4B）。黏接劑硬化成固持層52。
另一方面，準備陶瓷板20、冷卻板30及金屬接合材料90（圖5A）。陶瓷板20內設有電極22，具有第一孔24。冷卻板30內設有冷媒通道32，具有氣體孔34。金屬接合材料90預先在相當於貫通孔42之位置形成預備孔92。
然後，利用TCB法使陶瓷板20之底面與冷卻板30之頂面彼此接合，得到接合體94（圖5B）。TCB法以例如下述方式進行。首先，將金屬接合材料90夾入陶瓷板20之底面與冷卻板30之頂面間，形成為疊層體。此時，陶瓷板20之第一孔24、金屬接合材料90之預備孔92、與冷卻板30之氣體孔34以彼此同軸方式堆疊起來。然後，在金屬接合材料90之固相線溫度以下（例如從固相線溫度減去20℃之溫度以上固相線溫度以下）之溫度，加壓接合疊層體，再回到室溫。藉此，金屬接合材料90變成金屬接合層40，預備孔92變成貫通孔42，可得到以金屬接合層40接合陶瓷板20與冷卻板30而得之接合體94。此時之金屬接合材料，可使用Al－Mg系接合材料或Al－Si－Mg系接合材料。例如，使用Al－Si－Mg系接合材料進行TCB法時，在真空環境氣氛下加熱之狀態，將疊層體加壓。金屬接合材料90之厚度較佳為100μm左右。
接著，在陶瓷板20 之第一孔24之內周面、金屬接合層40之貫通孔42之內周面、及冷卻板30之氣體孔34之內周面塗佈黏接劑。然後，在關閉第一孔24之頂部開口之狀態下，藉由將第一孔24、貫通孔42及氣體孔34抽真空而使黏接劑脫泡，同時將一體化構件As插入此等孔34、42、24。在此，相較於第一孔24之內周面與一體化構件As之外周面的間隙，貫通孔42之內周面與一體化構件As之外周面的間隙、氣體孔34之內周面與一體化構件As之外周面的間隙較寬。因此，位於貫通孔42及氣體孔34之黏接劑較容易脫泡。當一體化構件As之絕緣管60之頂面60a碰撞到第一孔24之段差時，多孔塞50之頂面50a與晶圓載置面21之基準面21c（參照圖3）同一平面。其後，黏接劑硬化成黏接層70，得到半導體製造裝置用構件10（圖5C）。
以上詳述之半導體製造裝置用構件10中，多孔塞50之底面50b位於金屬接合層40之頂面40a以下位置。多孔塞50之底面50b相較於金屬接合層40之頂面40a上方的話，多孔塞50之底面50b與導電性基材（金屬接合層40及冷卻板30）之間產生電弧放電。相對於此，多孔塞50之底面50b位於金屬接合層40之頂面40a以下位置時，可抑制此電弧放電。又，絕緣管60之底面60b相較於多孔塞50之底面50b下方。因此，相較於沒有此絕緣管之情形，從晶圓W到導電性基材為止之沿面距離變長，可抑制多孔塞50內之火花放電。因此，可抑制晶圓W與導電性基材之間產生電弧放電及火花放電。
又，相較於第一孔24內部，金屬接合層40之貫通孔42內部及冷卻板30之氣體孔34內部中，黏接層70之寬度在半徑外側方向較寬。因此，以黏接劑形成黏接層70之際，可抑制氣泡進入位於貫通孔42及氣體孔34之黏接劑而充填黏接劑。因此，可使得位於貫通孔42及氣體孔34之黏接層70之氣孔比例較低。
再者，絕緣管60在管頂部具備有底孔64，多孔塞50在插入有底孔64之狀態下黏接固定。因此，沒有必要對較易損壞之多孔塞50施加形狀加工。
又再者，多孔塞50之頂面50a相較於密封環帶21a之頂面及圓形小突起21b之頂面較低。因此，不會發生以多孔塞50之頂面50a將晶圓W往上推之情況。
另外，多孔塞50之頂面50a和晶圓載置面21之基準面21c相同高度。因此，晶圓W之底面與多孔塞50 之頂面50a間的空間之高度被壓制得較低，故可防止在此空間產生電弧放電。
又，絕緣管60使用氣體通路62之直徑小於有底孔64之直徑者。因此，相較於氣體通路62之內徑和有底孔64之內徑相同的情形，氣體傳熱量降低（絕緣管60相較於氦氣容易傳熱，由於該絕緣管60之體積加大，因此氣體傳熱量降低），晶圓W之熱均勻性改善。同時，由於可確保從氣體通路62到冷卻板30為止之絕緣距離，因此絕緣耐受電壓上升。
又，本發明完全不限定於上述實施態樣，只要屬於本發明之技術範圍，可以各種態樣實施，係屬當然。
上述實施態樣中，如圖6所示，亦可將冷卻板30之氣體孔34的頂部開口之周緣34a設計為形成有C倒角之形狀。形成有C倒角之周緣34a為直徑從下往上變大之擴徑部。周緣34a與絕緣管60之間存在黏接層170。第二孔（金屬接合層40之貫通孔42及冷卻板30之氣體孔34）之內周面具有作為擴徑部之周緣34a。以此方式，在以黏接劑形成黏接層170之際，也將容易防止氣泡進入位於金屬接合層40之貫通孔42內部及冷卻板30之氣體孔34內部之黏接劑。周緣34a之C倒角較佳在C0.1以上。又，絕緣管60之側面與氣體孔34之側面之距離d較佳在2 mm以上。如此一來，從晶圓W到冷卻板30為止之沿面距離充分變長。又，從陶瓷板20之底面到黏接層170之底面為止之距離L，較佳在1mm以上，3mm以上更佳。如此一來，從晶圓W到冷卻板30為止之沿面距離充分變長。又，由於可將冷卻板30與絕緣管60之間的空間（隔熱層）以熱傳導優於該空間之黏接層170充分地充填，熱能容易從絕緣管60往冷卻板30傳導，因此晶圓W之熱均勻性提高。圖6中，亦可使用樹脂黏接層取代金屬接合層40。同樣地，此時第二孔（冷卻板30之氣體孔34）之內周面具有作為擴徑部之周緣34a。
上述實施態樣中，多孔塞50之頂面50a設計為和晶圓載置面21之基準面21c相同高度，但不限定於此。例如圖7所示，亦可設計為從晶圓載置面21之基準面21c高度減去多孔塞50之頂面50a高度而得之差Δh在0.2mm以下（較佳為0.1mm以下）。換言之，在相差0.2mm以下（較佳為0.1mm以下）之範圍，將多孔塞50之頂面50a配置在低於晶圓載置面21之基準面21c之位置亦可。以此方式，晶圓W之底面與多孔塞50 之頂面50a間的空間之高度同樣被壓制得較低，故可防止在此空間產生電弧放電。
上述實施態樣中，將多孔塞50之底面50b設計成位於金屬接合層40之貫通孔42之內部（亦即相較於金屬接合層40之頂面40a下方），但不限定於此。例如圖8所示，亦可將多孔塞50之底面50b設計成位於冷卻板30之氣體孔34之內部（亦即相較於冷卻板30之頂面下方）。以此方式，也能得到和上述實施態樣同樣之效果。此種構成在使用樹脂黏接層取代金屬接合層40之情形有其功效。其原因為：多孔塞50之底面50b位於樹脂黏接層之貫通孔之內部時，多孔塞50之底面50b與冷卻板30之間產生電位差，但以圖8之方式構成的話，將沒有此電位差。圖8中，使用樹脂黏接層取代金屬接合層40時，冷卻板30即相當於本發明之導電性基材，氣體孔34即相當於第二孔。
上述實施態樣中，將多孔塞50插入設在絕緣管60之管頂部之有底孔64而黏接固定，但不限定於此。例如圖9所示，亦可在多孔塞250之底面設置有底孔252，將直徑小於多孔塞250之絕緣管260插入該有底孔252而黏接固定。此時，多孔塞250與絕緣管260之一體化構件藉由黏接層270黏接固定，該黏接層270設於多孔塞250之外周面與各個孔（陶瓷板220之第一孔224、金屬接合層240之貫通孔242、及冷卻板230之氣體孔234）之內周面間。多孔塞250之底面（除有底孔之外）也形成有黏接層270。亦可使用圖10之非等徑之多孔塞350取代圖9之圓柱狀之多孔塞250。
上述實施態樣中，作為內設於陶瓷板20之電極22，例示靜電電極，但不限定於此。例如，亦可於陶瓷板20內設加熱電極（電阻發熱體）取代電極22，或除電極22之外，進一步內設加熱電極（電阻發熱體）。
本申請案以2021年12月22日申請之日本專利申請案第2021－208054號為主張優先權之基礎案，其全部內容引用記載於本說明書。
10:半導體製造裝置用構件 20:陶瓷板 21:晶圓載置面 21a:密封環帶 21b:圓形小突起 21c:基準面 22:電極 24:第一孔 24a:孔頂部 24b:孔底部 30:冷卻板 32:冷媒通道 34:氣體孔 34a:周緣 40:金屬接合層 40a:頂面 42:貫通孔 50:多孔塞 50a:頂面 50b:底面 52:固持層 60:絕緣管 60a:頂面 60b:底面 62:氣體通路 64:有底孔 70:黏接層 90:金屬接合材料 92:預備孔 94:接合體 170:黏接層 220:陶瓷板 224:第一孔 230:冷卻板 234:氣體孔 240:金屬接合層 242:貫通孔 250:多孔塞 252:有底孔 260:絕緣管 270:黏接層 350:多孔塞 As:一體化構件 d,L:距離 W:晶圓 Δh:差
【圖1】半導體製造裝置用構件10之縱剖面圖。 【圖2】陶瓷板20之俯視圖。 【圖3】圖1之部分放大圖。 【圖4】圖4A、圖4B一體化構件As之製程圖。 【圖5】圖5A~圖5C半導體製造裝置用構件10之製程圖。 【圖6】顯示黏接層170及其周邊之部分放大圖。 【圖7】顯示多孔塞50之變形例之部分放大圖。 【圖8】顯示多孔塞50之變形例之部分放大圖。 【圖9】顯示多孔塞250及其周邊之部分放大圖。 【圖10】顯示多孔塞350及其周邊之部分放大圖。
10:半導體製造裝置用構件
20:陶瓷板
21:晶圓載置面
22:電極
24:第一孔
30:冷卻板
32:冷媒通道
34:氣體孔
40:金屬接合層
40a:頂面
42:貫通孔
50:多孔塞
60:絕緣管
70:黏接層
As:一體化構件
W:晶圓

Claims (6)

  1. 一種半導體製造裝置用構件，包含： 陶瓷板，其頂面具有晶圓載置面； 導電性基材，設置於該陶瓷板之底面； 第一孔，在上下方向貫穿該陶瓷板； 第二孔，在上下方向貫穿該導電性基材，且連通於該第一孔； 多孔塞，其頂面露出於該第一孔之頂部開口，而其底面位於該導電性基材之頂面以下位置； 絕緣管，其頂面位於較該晶圓載置面更下方，而其底面位於較該多孔塞之底面更下方；及 一體化構件，由該多孔塞與該絕緣管一體化而構成，其外周面利用從該第一孔之頂面直到該第二孔之內部的黏接層固定於該第一孔及該第二孔。
  2. 如請求項1之半導體製造裝置用構件，其中， 相較於在該第一孔之內部，在該第二孔之內部中該黏接層之寬度於半徑外側方向較寬。
  3. 如請求項1或2之半導體製造裝置用構件，其中， 該第二孔之內周面具有直徑從下往上變大之擴徑部， 該擴徑部與該絕緣管之間存在該黏接層。
  4. 如請求項1或2之半導體製造裝置用構件，其中， 該絕緣管在管頂部具備有底孔， 該多孔塞在插入該有底孔之狀態下受固持。
  5. 如請求項1或2之半導體製造裝置用構件，其中， 該晶圓載置面具有支持晶圓之多個小突起， 該多孔塞之頂面較該小突起之頂面位在較低位置。
  6. 如請求項5之半導體製造裝置用構件，其中， 該多孔塞之頂面係和該晶圓載置面中未設置該小突起之基準面相同高度、或在較該基準面低0.2mm以下之範圍的位置。
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US11456161B2 (en) 2018-06-04 2022-09-27 Applied Materials, Inc. Substrate support pedestal
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